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FMC TDC 1ns 5cha
Commit 1251d7a5 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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wip: applied the convention (spec_base_wr) to the top level of the design; 

updated submodules;
added missing sim files
parent 7d68c05f
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Showing with 1705 additions and 2116 deletions
.gitmodules
View file @ 1251d7a5
[submodule "ip-cores/general-cores"]
[submodule "hdl/ip-cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
\ No newline at end of file
ddr3-sp6-core @ 1a129390
Subproject commit 8618c1e154c322be34cb069b62d8293527744dda
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores @ 96728bc0
Subproject commit 4d36bf859fa6071acf11d86e1d57ab3a65a5f776
Subproject commit 96728bc02801f5343597e2a7bb916fde33dc0139
gn4124-core @ 91d5efac
Subproject commit 017ef8c1453664414e871a7992496e15951f32fe
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ b3d2bfc2
Subproject commit b3d2bfc24e01b95acef5d4240cb476c3f2f42566
wr-cores @ 25deb517
Subproject commit 5bb966b6868537eb1bf1acf3dd04df95985966bb
Subproject commit 25deb51759cf467df4fdeeca3bd10e4e793f71ca
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 1251d7a5
......@@ -645,7 +645,7 @@ begin
i2c_scl_oen_o <= sys_scl_oe_n;
i2c_scl_o <= sys_scl_out;
U_OnewireIF : gc_ds182x_interface
U_OnewireIF : gc_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62500,
g_USE_INTERNAL_PPS => true)
......
hdl/rtl/tdc_core_pkg.vhd
View file @ 1251d7a5
......@@ -336,8 +336,8 @@ package tdc_core_pkg is
-- corresponds to:
constant c_STARTING_UTC_ADR : std_logic_vector(7 downto 0) := x"20"; -- address 0x51080 of GN4124 BAR 0
constant c_ACAM_INPUTS_EN_ADR : std_logic_vector(7 downto 0) := x"21"; -- address 0x51084 of GN4124 BAR 0
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_FMC_ID_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_SPARE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
......
hdl/syn/spec/Makefile
View file @ 1251d7a5
......@@ -7,8 +7,8 @@ TOP_MODULE := wr_spec_tdc
PWD := $(shell pwd)
PROJECT := wr_spec_tdc
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH := /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
TCL_INTERPRETER := xtclsh
TOOL_PATH := C:\Xilinx\14.7\ISE_DS\ISE\bin\nt
TCL_INTERPRETER := xtclsh.exe
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
......@@ -29,241 +29,277 @@ endif
#target for performing local synthesis
all: bitstream
SOURCES_NGCFile := \
../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc \
../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc \
../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc
SOURCES_UCFFile := \
../../top/spec/wr_spec_tdc.ucf
SOURCES_VerilogFile := \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
SOURCES_VHDLFile := \
../../rtl/tdc_dma_channel.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd \
../../rtl/clks_rsts_manager.vhd \
../../rtl/reg_ctrl.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/wr-cores/board/spec/wr_spec_pkg.vhd \
../../rtl/tdc_core_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../rtl/acam_databus_interface.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd \
../../rtl/timestamp_fifo_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd \
../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../top/spec/wr_spec_tdc.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
../../rtl/tdc_eic.vhd \
../../rtl/timestamp_fifo_wb.vhd \
../../rtl/fmc_tdc_core.vhd \
../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../rtl/timestamp_fifo.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../rtl/timestamp_convert_filter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd \
../../rtl/fmc_tdc_wrapper.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
../../rtl/leds_manager.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
../../ip_cores/gn4124-core/hdl/rtl/wbmaster32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd \
../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
../../rtl/tdc_dma_engine.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
../../rtl/data_formatting.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../rtl/wrabbit_sync.vhd \
../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd \
../../rtl/tdc_buffer_control_regs_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd \
../../rtl/carrier_info.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
../../rtl/leds_manager.vhd \
../../rtl/incr_counter.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../rtl/local_pps_gen.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/xwb_gn4124_core.vhd \
../../rtl/tdc_buffer_control_regs.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../rtl/decr_counter.vhd \
../../rtl/data_engine.vhd \
../../rtl/timestamp_fifo.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd \
../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../rtl/tdc_dma_channel.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../rtl/tdc_onewire_wbgen2_pkg.vhd \
../../rtl/tdc_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
../../rtl/tdc_ts_sub.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/gn4124-core/hdl/rtl/p2l_decode32.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
../../rtl/fmc_tdc_wrapper.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd \
../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../rtl/tdc_dma_engine.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../rtl/decr_counter.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../rtl/fmc_tdc_direct_readout_slave.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd \
../../rtl/tdc_core_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/gn4124_core_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../rtl/tdc_buffer_control_regs.vhd \
../../rtl/timestamp_fifo_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd \
../../ip_cores/spec/hdl/rtl/spec_base_wr.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
../../rtl/tdc_ts_addsub.vhd \
../../rtl/fmc_tdc_direct_readout_slave.vhd \
../../rtl/acam_timecontrol_interface.vhd \
../../rtl/acam_databus_interface.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../rtl/wrabbit_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../rtl/wbgen2_eic_nomask.vhd \
../../rtl/clks_rsts_manager.vhd \
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd \
../../rtl/timestamp_fifo_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../rtl/timestamp_convert_filter.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/wr-cores/board/spec/wr_spec_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd \
../../rtl/reg_ctrl.vhd \
../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd \
../../rtl/fmc_tdc_core.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
../../top/spec/synthesis_descriptor.vhd \
../../rtl/free_counter.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd \
../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../top/spec/wr_spec_tdc.vhd \
../../rtl/incr_counter.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../rtl/tdc_onewire_wb.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../ip_cores/spec/hdl/rtl/spec_base_regs.vhd \
../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd \
buildinfo_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/p2l_des.vhd \
../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../rtl/start_retrig_ctrl.vhd \
../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
../../ip_cores/gn4124-core/hdl/rtl/l2p_arbiter.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd \
../../ip_cores/gn4124-core/hdl/rtl/p2l_dma_master.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/gn4124-core/hdl/rtl/l2p_dma_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd \
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd \
../../rtl/fmc_tdc_mezzanine.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../rtl/free_counter.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
../../ip_cores/gn4124-core/hdl/rtl/dma_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../rtl/acam_timecontrol_interface.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../rtl/data_engine.vhd \
../../rtl/local_pps_gen.vhd \
../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../rtl/data_formatting.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../rtl/start_retrig_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd \
../../top/spec/synthesis_descriptor.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd \
../../rtl/fmc_tdc_direct_readout.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/gn4124-core/hdl/rtl/dma_controller_regs.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd \
../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../rtl/tdc_buffer_control_regs_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../ip_cores/gn4124-core/hdl/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
../../rtl/fmc_tdc_mezzanine.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd
SOURCES_VerilogFile := \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
SOURCES_UCFFile := \
../../top/spec/wr_spec_tdc.ucf \
../../ip_cores/spec/hdl/syn/common/spec_base_ddr3.ucf \
../../ip_cores/spec/hdl/syn/common/spec_base_common.ucf \
../../ip_cores/spec/hdl/syn/common/spec_base_spi.ucf \
../../ip_cores/spec/hdl/syn/common/spec_base_onewire.ucf \
../../ip_cores/spec/hdl/syn/common/spec_base_wr.ucf
SOURCES_NGCFile := \
../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_icon.ngc \
../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_ila.ngc
files.tcl:
@$(foreach sourcefile, $(SOURCES_NGCFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_UCFFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_VerilogFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo xfile add $(sourcefile) >> $@ &)
@$(foreach sourcefile, $(SOURCES_VerilogFile), echo xfile add $(sourcefile) >> $@ &)
@$(foreach sourcefile, $(SOURCES_UCFFile), echo xfile add $(sourcefile) >> $@ &)
@$(foreach sourcefile, $(SOURCES_NGCFile), echo xfile add $(sourcefile) >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_POST_PROJECT_CMD := $(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
......@@ -282,14 +318,15 @@ SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo project set "family" "$(SYN_FAMILY)" >> $@
echo project set "device" "$(SYN_DEVICE)" >> $@
echo project set "package" "$(SYN_PACKAGE)" >> $@
echo project set "speed" "$(SYN_GRADE)" >> $@
echo project set \"Manual Implementation Compile Order\" "false" >> $@
echo project set \"Auto Implementation Top\" "false" >> $@
echo project set \"Create Binary Configuration File\" "true" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
......@@ -299,14 +336,14 @@ project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
type nul >> $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo process run $$process >> $@
echo set result [process get $$process status] >> $@
echo if { $$result == "errors" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
......@@ -316,14 +353,14 @@ synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
type nul >> $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo process run $$process >> $@
echo set result [process get $$process status] >> $@
echo if { $$result == "errors" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
......@@ -333,14 +370,14 @@ translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
type nul >> $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo process run $$process >> $@
echo set result [process get $$process status] >> $@
echo if { $$result == "errors" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
......@@ -350,14 +387,14 @@ map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
type nul >> $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo set process {Place ^& Route} >> $@
echo process run $$process >> $@
echo set result [process get $$process status] >> $@
echo if { $$result == "errors" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
......@@ -367,14 +404,14 @@ par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
type nul >> $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo process run $$process >> $@
echo set result [process get $$process status] >> $@
echo if { $$result == "errors" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
......@@ -384,16 +421,17 @@ bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
type nul >> $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
del /s /q /f $(CLEAN_TARGETS)
@-rmdir /s /q $(CLEAN_TARGETS) >nul 2>&1
del /s /q /f project synthesize translate map par bitstream
del /s /q /f project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
del /s /q /f *.bit *.bin *.mcs
.PHONY: mrproper clean all
hdl/syn/spec/Manifest.py
View file @ 1251d7a5
board = "spec"
target = "xilinx"
action = "synthesis"
......@@ -11,5 +12,19 @@ syn_project = "wr_spec_tdc.xise"
syn_tool = "ise"
top_module = "wr_spec_tdc"
files = ["buildinfo_pkg.vhd"]
modules = { "local" : [ "../../top/spec" ] }
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
ctrls = ["bank3_32b_32b"]
hdl/syn/spec/wr_spec_tdc.xise
View file @ 1251d7a5
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/include/timestamp_fifo_regs.vh 0 → 100644
View file @ 1251d7a5
`define ADDR_TSF_DELTA1 6'h0
`define ADDR_TSF_DELTA2 6'h4
`define ADDR_TSF_DELTA3 6'h8
`define ADDR_TSF_OFFSET1 6'hc
`define ADDR_TSF_OFFSET2 6'h10
`define ADDR_TSF_OFFSET3 6'h14
`define ADDR_TSF_CSR 6'h18
`define TSF_CSR_DELTA_READY_OFFSET 0
`define TSF_CSR_DELTA_READY 32'h00000001
`define TSF_CSR_DELTA_READ_OFFSET 1
`define TSF_CSR_DELTA_READ 32'h00000002
`define TSF_CSR_RST_SEQ_OFFSET 2
`define TSF_CSR_RST_SEQ 32'h00000004
`define TSF_CSR_DELTA_REF_OFFSET 3
`define TSF_CSR_DELTA_REF 32'h00000038
`define TSF_CSR_RAW_MODE_OFFSET 6
`define TSF_CSR_RAW_MODE 32'h00000040
`define ADDR_TSF_FIFO_R0 6'h1c
`define TSF_FIFO_R0_TS0_OFFSET 0
`define TSF_FIFO_R0_TS0 32'hffffffff
`define ADDR_TSF_FIFO_R1 6'h20
`define TSF_FIFO_R1_TS1_OFFSET 0
`define TSF_FIFO_R1_TS1 32'hffffffff
`define ADDR_TSF_FIFO_R2 6'h24
`define TSF_FIFO_R2_TS2_OFFSET 0
`define TSF_FIFO_R2_TS2 32'hffffffff
`define ADDR_TSF_FIFO_R3 6'h28
`define TSF_FIFO_R3_TS3_OFFSET 0
`define TSF_FIFO_R3_TS3 32'hffffffff
`define ADDR_TSF_FIFO_CSR 6'h2c
`define TSF_FIFO_CSR_FULL_OFFSET 16
`define TSF_FIFO_CSR_FULL 32'h00010000
`define TSF_FIFO_CSR_EMPTY_OFFSET 17
`define TSF_FIFO_CSR_EMPTY 32'h00020000
`define TSF_FIFO_CSR_CLEAR_BUS_OFFSET 18
`define TSF_FIFO_CSR_CLEAR_BUS 32'h00040000
`define TSF_FIFO_CSR_USEDW_OFFSET 0
`define TSF_FIFO_CSR_USEDW 32'h0000003f
hdl/testbench/spec/Manifest.py
View file @ 1251d7a5
......@@ -8,8 +8,29 @@ target = "xilinx"
fetchto = "../../ip_cores"
include_dirs=[ "../../sim", "../include" ]
vcom_opt = "-mixedsvvh l"
files = [ "main.sv" ]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }
include_dirs = [
"../include",
"../../sim",
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim",
fetchto + "/general-cores/modules/wishbone/wb_lm32/src",
fetchto + "/wr-cores/sim",
fetchto + "/general-cores/modules/wishbone/wb_spi",
]
ctrls = ["bank3_32b_32b"]
\ No newline at end of file
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm" ] }
ctrls = ["bank3_32b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
\ No newline at end of file
hdl/testbench/spec/buildinfo_pkg.vhd 0 → 100644
View file @ 1251d7a5
-- Buildinfo for project main
--
-- This file was automatically generated; do not edit
package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:7d68c05fc60844172732a01f54f436f71e7d76c6" & LF
& "syntool:modelsim" & LF
& "syndate:2019-09-26, 17:01 CEST" & LF
& "synauth:Evangelia Gousiou" & LF;
end buildinfo_pkg;
hdl/testbench/spec/main.sv
View file @ 1251d7a5
......@@ -8,6 +8,7 @@ import tdc_core_pkg::*;
`include "vhd_wishbone_master.svh"
`include "acam_model.svh"
`include "softpll_regs_ng.vh"
`include "gn4124_bfm.svh"
typedef struct {
uint32_t tai;
......@@ -45,14 +46,19 @@ class FmcTdcDriver;
task automatic init();
uint32_t d;
readl('h000000, d);
readl('h20000, d);
$display("address 0x20000: %x", d);
if( d != 'h5344422d )
begin
$error("!!!!address 0x0 %x!!!!", d);
$error("Can't read the SDB signature.");
$stop;
end
writel('h20a0, 1234); // set UTC
writel('h20fc, 1<<9); // load UTC
......@@ -172,14 +178,14 @@ module main;
.D(tdc_data)
);
IGN4124PCIMaster Host
(
);
wr_spec_tdc
#(
.g_with_wr_phy(0),
.g_simulation(1),
.g_calib_soft_ip(0),
.g_sim_bypass_gennum(1)
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
......@@ -187,57 +193,70 @@ module main;
.clk_125m_gtp_n_i(~clk_125m),
.tdc_clk_125m_p_i(clk_125m),
.tdc_clk_125m_n_i(~clk_125m),
.fmc0_tdc_clk_125m_p_i(clk_125m),
.fmc0_tdc_clk_125m_n_i(~clk_125m),
.acam_refclk_p_i(clk_acam),
.acam_refclk_n_i(~clk_acam),
.fmc0_tdc_acam_refclk_p_i(clk_acam),
.fmc0_tdc_acam_refclk_n_i(~clk_acam),
.clk_20m_vcxo_i(clk_20m),
.pll_status_i(1'b1),
.fmc0_tdc_pll_status_i(1'b1),
.ef1_i(tdc_ef1),
.ef2_i(tdc_ef2),
.err_flag_i(tdc_err_flag),
.int_flag_i(tdc_int_flag),
.rd_n_o(tdc_rd_n),
.wr_n_o(tdc_wr_n),
.oe_n_o(tdc_oe_n),
.cs_n_o(tdc_cs_n),
.data_bus_io(tdc_data),
.address_o(tdc_addr),
.start_from_fpga_o(tdc_start),
.start_dis_o(tdc_start_dis),
.stop_dis_o(tdc_stop_dis[1]),
.fmc0_tdc_ef1_i(tdc_ef1),
.fmc0_tdc_ef2_i(tdc_ef2),
.fmc0_tdc_err_flag_i(tdc_err_flag),
.fmc0_tdc_int_flag_i(tdc_int_flag),
.fmc0_tdc_rd_n_o(tdc_rd_n),
.fmc0_tdc_wr_n_o(tdc_wr_n),
.fmc0_tdc_oe_n_o(tdc_oe_n),
.fmc0_tdc_cs_n_o(tdc_cs_n),
.fmc0_tdc_data_bus_io(tdc_data),
.fmc0_tdc_address_o(tdc_addr),
.fmc0_tdc_start_from_fpga_o(tdc_start),
.fmc0_tdc_start_dis_o(tdc_start_dis),
.fmc0_tdc_stop_dis_o(tdc_stop_dis[1]),
.sim_wb_i(Host.out),
.sim_wb_o(Host.in)
`GENNUM_WIRE_SPEC_BTRAIN_REF(Host)
);
assign tdc_stop_dis[4] = tdc_stop_dis[1];
assign tdc_stop_dis[3] = tdc_stop_dis[1];
assign tdc_stop_dis[2] = tdc_stop_dis[1];
IVHDWishboneMaster Host
(
.clk_i (DUT.clk_sys_62m5),
.rst_n_i (DUT.rst_sys_62m5_n)
);
// IVHDWishboneMaster Host
// (
// .clk_i (DUT.clk_sys_62m5),
// .rst_n_i (DUT.rst_sys_62m5_n)
// );
initial
begin
CBusAccessor acc;
FmcTdcDriver drv;
const uint64_t tdc1_base = 'h40000;
const uint64_t tdc1_base = 'h20000;
uint64_t d;
acc = Host.get_accessor();
#10us;
$display("Un-reset FMCs...");
acc.write('h02000c, 'h3);
//$display("Un-reset FMCs...");
//acc.write('h02000c, 'h3);
acc.read('h20000, d);
$display("address 0x20000: %x", d);
acc.read('h22004, d);
$display("address 0x22004: %x", d);
acc.write('h2208c, 1234); // test
acc.read('h2208c, d);
$display("address 0x2208c: %x", d);
acc.write('h22080, 1234); // starting UTC
acc.write('h220fc, 1<<9); // load UTC
drv = new (acc, 'h40000, 0 );
......
hdl/top/spec/Manifest.py
View file @ 1251d7a5
......@@ -6,11 +6,12 @@ fetchto = "../../ip_cores"
modules = {
"local" : [ "../../rtl/",
"../../ip_cores/gn4124-core",
"../../ip_cores/general-cores",
"../../ip_cores/gn4124-core",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/ddr3-sp6-core"
"../../ip_cores/ddr3-sp6-core",
"../../ip_cores/spec"
]
}
hdl/top/spec/wr_spec_tdc.ucf
View file @ 1251d7a5
#===============================================================================
# FMC0 IO Location Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "tdc_clk_125m_p_i" LOC = "L20";
NET "tdc_clk_125m_p_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_p_i" TNM_NET = "tdc_clk_125m_p_i";
TIMESPEC TStdc_clk_125m_p_i = PERIOD "tdc_clk_125m_p_i" 8 ns HIGH 50%;
NET "tdc_clk_125m_n_i" LOC = "L22";
NET "tdc_clk_125m_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_n_i" TNM_NET = "tdc_clk_125m_n_i";
TIMESPEC TS_tdc_clk_125m_n_i = PERIOD "tdc_clk_125m_n_i" 8 ns HIGH 50%;
#####################################################################
### Gennum ports
#####################################################################
NET "gn_rst_n" LOC = N20;
NET "gn_rst_n" IOSTANDARD = "LVCMOS18";
NET "gn_gpio[1]" LOC = U16;
NET "gn_gpio[1]" IOSTANDARD = "LVCMOS25";
NET "gn_gpio[0]" LOC = AB19;
NET "gn_gpio[0]" IOSTANDARD = "LVCMOS25";
NET "gn_p2l_rdy" LOC = J16;
NET "gn_p2l_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_clkn" LOC = M19;
NET "gn_p2l_clkn" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clkp" LOC = M20;
NET "gn_p2l_clkp" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_data[0]" LOC = K20;
NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[1]" LOC = H22;
NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[2]" LOC = H21;
NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[3]" LOC = L17;
NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[4]" LOC = K17;
NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[5]" LOC = G22;
NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[6]" LOC = G20;
NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[7]" LOC = K18;
NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[8]" LOC = K19;
NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[9]" LOC = H20;
NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[10]" LOC = J19;
NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[11]" LOC = E22;
NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[12]" LOC = E20;
NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[13]" LOC = F22;
NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[14]" LOC = F21;
NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[15]" LOC = H19;
NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe" LOC = J22;
NET "gn_p2l_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid" LOC = L19;
NET "gn_p2l_valid" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[0]" LOC = M22;
NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[1]" LOC = M21;
NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[0]" LOC = L15;
NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[1]" LOC = K16;
NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error" LOC = J17;
NET "gn_rx_error" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[0]" LOC = P16;
NET "gn_l2p_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[1]" LOC = P21;
NET "gn_l2p_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[2]" LOC = P18;
NET "gn_l2p_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[3]" LOC = T20;
NET "gn_l2p_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[4]" LOC = V21;
NET "gn_l2p_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[5]" LOC = V19;
NET "gn_l2p_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[6]" LOC = W22;
NET "gn_l2p_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[7]" LOC = Y22;
NET "gn_l2p_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[8]" LOC = P22;
NET "gn_l2p_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[9]" LOC = R22;
NET "gn_l2p_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[10]" LOC = T21;
NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[11]" LOC = T19;
NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[12]" LOC = V22;
NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[13]" LOC = V20;
NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[14]" LOC = W20;
NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[15]" LOC = Y21;
NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_dframe" LOC = U22;
NET "gn_l2p_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid" LOC = T18;
NET "gn_l2p_valid" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clkn" LOC = K22;
NET "gn_l2p_clkn" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clkp" LOC = K21;
NET "gn_l2p_clkp" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_edb" LOC = U20;
NET "gn_l2p_edb" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy" LOC = U19;
NET "gn_l2p_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[0]" LOC = R20;
NET "gn_l_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[1]" LOC = T22;
NET "gn_l_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[0]" LOC = N16;
NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[1]" LOC = P19;
NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error" LOC = M17;
NET "gn_tx_error" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[0]" LOC = B21;
NET "gn_vc_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[1]" LOC = B22;
NET "gn_vc_rdy[1]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# FMC slot
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "acam_refclk_p_i" LOC = "E16";
NET "acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "acam_refclk_n_i" LOC = "F16";
NET "acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_led_trig1_o" LOC = "W18";
NET "tdc_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig2_o" LOC = "B20";
NET "tdc_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig3_o" LOC = "A20";
NET "tdc_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "term_en_1_o" LOC = "Y11";
NET "term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "term_en_2_o" LOC = "AB11";
NET "term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "ef1_i" LOC = "W12";
NET "ef1_i" IOSTANDARD = "LVCMOS25";
NET "ef2_i" LOC = "Y12";
NET "ef2_i" IOSTANDARD = "LVCMOS25";
NET "term_en_3_o" LOC = "R11";
NET "term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "term_en_4_o" LOC = "T11";
NET "term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "term_en_5_o" LOC = "R13";
NET "term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_status_o" LOC = "T14";
NET "tdc_led_status_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig4_o" LOC = "D17";
NET "tdc_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig5_o" LOC = "C18";
NET "tdc_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "pll_sclk_o" LOC = "AA16";
NET "pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "pll_dac_sync_o" LOC = "AB16";
NET "pll_dac_sync_o" IOSTANDARD = "LVCMOS25";
NET "pll_cs_o" LOC = "Y17";
NET "pll_cs_o" IOSTANDARD = "LVCMOS25";
NET "cs_n_o" LOC = "AB17";
NET "cs_n_o" IOSTANDARD = "LVCMOS25";
NET "err_flag_i" LOC = "V11";
NET "err_flag_i" IOSTANDARD = "LVCMOS25";
NET "int_flag_i" LOC = "W11";
NET "int_flag_i" IOSTANDARD = "LVCMOS25";
NET "start_dis_o" LOC = "T15";
NET "start_dis_o" IOSTANDARD = "LVCMOS25";
NET "stop_dis_o" LOC = "U15";
NET "stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "pll_sdo_i" LOC = "AB18";
NET "pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "pll_status_i" LOC = "Y18";
NET "pll_status_i" IOSTANDARD = "LVCMOS25";
NET "pll_sdi_o" LOC = "AA18";
NET "pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "start_from_fpga_o" LOC = "W17";
NET "start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "start_from_fpga_o" SLEW = SLOW;
NET "start_from_fpga_o" DRIVE = 4;
NET "data_bus_io[27]" LOC = "AB4";
NET "data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[26]" LOC = "AA4";
NET "data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[25]" LOC = "AB9";
NET "data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[24]" LOC = "Y9";
NET "data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[23]" LOC = "Y10";
NET "data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[22]" LOC = "W10";
NET "data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[21]" LOC = "U10";
NET "data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[20]" LOC = "T10";
NET "data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[19]" LOC = "AB8";
NET "data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[18]" LOC = "AA8";
NET "data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[17]" LOC = "AB7";
NET "data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[16]" LOC = "Y7";
NET "data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[15]" LOC = "V9";
NET "data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[14]" LOC = "U9";
NET "data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[13]" LOC = "AB6";
NET "data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[12]" LOC = "AA6";
NET "data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[11]" LOC = "R8";
NET "data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[10]" LOC = "R9";
NET "data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[9]" LOC = "AB5";
NET "data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[8]" LOC = "Y5";
NET "data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[7]" LOC = "AB12";
NET "data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[6]" LOC = "U8";
NET "data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[5]" LOC = "AA12";
NET "data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[4]" LOC = "T8";
NET "data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[3]" LOC = "W8";
NET "data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[2]" LOC = "V7";
NET "data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[1]" LOC = "Y6";
NET "data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[0]" LOC = "W6";
NET "data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "address_o[3]" LOC = "AB15";
NET "address_o[3]" IOSTANDARD = "LVCMOS25";
NET "address_o[2]" LOC = "Y15";
NET "address_o[2]" IOSTANDARD = "LVCMOS25";
NET "address_o[1]" LOC = "U12";
NET "address_o[1]" IOSTANDARD = "LVCMOS25";
NET "address_o[0]" LOC = "T12";
NET "address_o[0]" IOSTANDARD = "LVCMOS25";
NET "oe_n_o" LOC = "V13";
NET "oe_n_o" IOSTANDARD = "LVCMOS25";
NET "oe_n_o" SLEW = SLOW;
NET "oe_n_o" DRIVE = 4;
NET "rd_n_o" LOC = "AB13";
NET "rd_n_o" IOSTANDARD = "LVCMOS25";
NET "rd_n_o" SLEW = SLOW;
NET "rd_n_o" DRIVE = 4;
NET "wr_n_o" LOC = "Y13";
NET "wr_n_o" IOSTANDARD = "LVCMOS25";
NET "wr_n_o" SLEW = SLOW;
NET "wr_n_o" DRIVE = 4;
NET "enable_inputs_o" LOC = "C19";
NET "enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "mezz_onewire_b" LOC = "A19";
NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
NET "mezz_sys_scl_b" LOC = "F7";
NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
NET "mezz_sys_sda_b" LOC = "F8";
NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
#----------------------------------------
NET "prsnt_m2c_n_i" LOC = AB14;
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# TDC IN FPGA (not used)
#----------------------------------------
NET "tdc_in_fpga_1_i" LOC = V17;
NET "tdc_in_fpga_1_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier Generic Stuff
#----------------------------------------
NET "led_act_o" LOC = D5;
NET "led_act_o" IOSTANDARD = "LVCMOS25";
NET "led_link_o" LOC = E5;
NET "led_link_o" IOSTANDARD = "LVCMOS25";
NET "wr_25dac_cs_n_o" LOC = A3;
NET "wr_25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "wr_20dac_cs_n_o" LOC = B3;
NET "wr_20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "wr_dac_din_o" LOC = C4;
NET "wr_dac_din_o" IOSTANDARD = "LVCMOS25";
NET "wr_dac_sclk_o" LOC = A4;
NET "wr_dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "button1_i" LOC = C22;
NET "button1_i" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# SFP
#----------------------------------------
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = A17;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
NET "fmc0_tdc_clk_125m_p_i" LOC = "L20";
NET "fmc0_tdc_clk_125m_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_clk_125m_p_i" TNM_NET = "tdc_clk_125m_p_i";
TIMESPEC TS_fmc0_tdc_clk_125m_p_i = PERIOD "fmc0_tdc_clk_125m_p_i" 8 ns HIGH 50%;
NET "fmc0_tdc_clk_125m_n_i" LOC = "L22";
NET "fmc0_tdc_clk_125m_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_clk_125m_n_i" TNM_NET = "tdc_clk_125m_n_i";
TIMESPEC TS_fmc0_tdc_clk_125m_n_i = PERIOD "fmc0_tdc_clk_125m_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Others
#----------------------------------------
NET "fmc0_tdc_acam_refclk_p_i" LOC = "E16";
NET "fmc0_tdc_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_acam_refclk_n_i" LOC = "F16";
NET "fmc0_tdc_acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_led_trig1_o" LOC = "W18";
NET "fmc0_tdc_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig2_o" LOC = "B20";
NET "fmc0_tdc_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig3_o" LOC = "A20";
NET "fmc0_tdc_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_1_o" LOC = "Y11";
NET "fmc0_tdc_term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_2_o" LOC = "AB11";
NET "fmc0_tdc_term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef1_i" LOC = "W12";
NET "fmc0_tdc_ef1_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef2_i" LOC = "Y12";
NET "fmc0_tdc_ef2_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_3_o" LOC = "R11";
NET "fmc0_tdc_term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_4_o" LOC = "T11";
NET "fmc0_tdc_term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_5_o" LOC = "R13";
NET "fmc0_tdc_term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_status_o" LOC = "T14";
NET "fmc0_tdc_led_status_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig4_o" LOC = "D17";
NET "fmc0_tdc_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig5_o" LOC = "C18";
NET "fmc0_tdc_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sclk_o" LOC = "AA16";
NET "fmc0_tdc_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_dac_sync_o" LOC = "AB16";
NET "fmc0_tdc_pll_dac_sync_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_cs_o" LOC = "Y17";
NET "fmc0_tdc_pll_cs_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_cs_n_o" LOC = "AB17";
NET "fmc0_tdc_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_err_flag_i" LOC = "V11";
NET "fmc0_tdc_err_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_int_flag_i" LOC = "W11";
NET "fmc0_tdc_int_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_dis_o" LOC = "T15";
NET "fmc0_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_stop_dis_o" LOC = "U15";
NET "fmc0_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdo_i" LOC = "AB18";
NET "fmc0_tdc_pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_status_i" LOC = "Y18";
NET "fmc0_tdc_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdi_o" LOC = "AA18";
NET "fmc0_tdc_pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" LOC = "W17";
NET "fmc0_tdc_start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" SLEW = SLOW;
NET "fmc0_tdc_start_from_fpga_o" DRIVE = 4;
NET "fmc0_tdc_data_bus_io[27]" LOC = "AB4";
NET "fmc0_tdc_data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[26]" LOC = "AA4";
NET "fmc0_tdc_data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[25]" LOC = "AB9";
NET "fmc0_tdc_data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[24]" LOC = "Y9";
NET "fmc0_tdc_data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[23]" LOC = "Y10";
NET "fmc0_tdc_data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[22]" LOC = "W10";
NET "fmc0_tdc_data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[21]" LOC = "U10";
NET "fmc0_tdc_data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[20]" LOC = "T10";
NET "fmc0_tdc_data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[19]" LOC = "AB8";
NET "fmc0_tdc_data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[18]" LOC = "AA8";
NET "fmc0_tdc_data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[17]" LOC = "AB7";
NET "fmc0_tdc_data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[16]" LOC = "Y7";
NET "fmc0_tdc_data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[15]" LOC = "V9";
NET "fmc0_tdc_data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[14]" LOC = "U9";
NET "fmc0_tdc_data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[13]" LOC = "AB6";
NET "fmc0_tdc_data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[12]" LOC = "AA6";
NET "fmc0_tdc_data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[11]" LOC = "R8";
NET "fmc0_tdc_data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[10]" LOC = "R9";
NET "fmc0_tdc_data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[9]" LOC = "AB5";
NET "fmc0_tdc_data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[8]" LOC = "Y5";
NET "fmc0_tdc_data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[7]" LOC = "AB12";
NET "fmc0_tdc_data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[6]" LOC = "U8";
NET "fmc0_tdc_data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[5]" LOC = "AA12";
NET "fmc0_tdc_data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[4]" LOC = "T8";
NET "fmc0_tdc_data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[3]" LOC = "W8";
NET "fmc0_tdc_data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[2]" LOC = "V7";
NET "fmc0_tdc_data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[1]" LOC = "Y6";
NET "fmc0_tdc_data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[0]" LOC = "W6";
NET "fmc0_tdc_data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[3]" LOC = "AB15";
NET "fmc0_tdc_address_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[2]" LOC = "Y15";
NET "fmc0_tdc_address_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[1]" LOC = "U12";
NET "fmc0_tdc_address_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[0]" LOC = "T12";
NET "fmc0_tdc_address_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" LOC = "V13";
NET "fmc0_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" SLEW = SLOW;
NET "fmc0_tdc_oe_n_o" DRIVE = 4;
NET "fmc0_tdc_rd_n_o" LOC = "AB13";
NET "fmc0_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_rd_n_o" SLEW = SLOW;
NET "fmc0_tdc_rd_n_o" DRIVE = 4;
NET "fmc0_tdc_wr_n_o" LOC = "Y13";
NET "fmc0_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_wr_n_o" SLEW = SLOW;
NET "fmc0_tdc_wr_n_o" DRIVE = 4;
NET "fmc0_tdc_enable_inputs_o" LOC = "C19";
NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_onewire_b" LOC = "A19";
NET "fmc0_tdc_onewire_b" IOSTANDARD = "LVCMOS25";
### TDC IN FPGA (not used):
NET "fmc0_tdc_in_fpga_1_i" LOC = V17;
NET "fmc0_tdc_in_fpga_1_i" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Terminations
# Timing constraints and exceptions
#===============================================================================
# DDR3
NET "DDR3_DQ[*]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;
#----------------------------------------
# Flash memory SPI interface
#----------------------------------------
NET "flash_ncs_o" LOC = AA3;
NET "flash_ncs_o" IOSTANDARD = "LVCMOS25";
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "gn_rst_n" TIG;
#NET "gen_with_gennum/cmp_gn4124_core/rst_*" TIG;
#NET "gen_with_gennum/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
TIMESPEC ts_ignore_crossclock = FROM "clk_sys_62m5" TO "tdc_clk_125m_p_i" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_crossclock2 = FROM "tdc_clk_125m_p_i" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "clk_125m_pllref_n_i" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_x3 = FROM "clk_sys_62m5" TO "U_GTP_ch1_rx_divclk" 20ns DATAPATHONLY;
TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_sys_62m5" 20ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2017/12/06
NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
#NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/07/26
NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "gn_rst_n" TIG;
# NET "*/cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/08/24
NET "gen_with_gennum.cmp_gn4124_core/rst_reg_d" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/08/27
hdl/top/spec/wr_spec_tdc.vhd
View file @ 1251d7a5
......@@ -131,25 +131,30 @@ use UNISIM.vcomponents.all;
entity wr_spec_tdc is
generic
(g_simulation : boolean := false;
g_CALIB_SOFT_IP : boolean := true;
g_sim_bypass_gennum : boolean := false;
(g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
g_simulation : boolean := false;
g_use_dma_readout : boolean := true;
g_use_fake_timestamps_for_sim : boolean := false
g_use_fake_timestamps_for_sim : boolean := false -- when instantiated in a test-bench
);
-- when instantiated in a test-bench
port(
-- Reset button
button1_n_i : in std_logic := '1';
-- Clocks
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
wr_dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
wr_dac_din_o : out std_logic;
wr_25dac_cs_n_o : out std_logic;
wr_20dac_cs_n_o : out std_logic;
-- DAC interface 20MHz and 25MHz VCXO
pll25dac_cs_n_o : out std_logic; -- 25MHz VCXO
pll20dac_cs_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- SFP
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
......@@ -162,130 +167,134 @@ entity wr_spec_tdc is
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
-- SPEC 1-wire interface
onewire_b : inout std_logic; -- DS18B20 thermometer + uniqueID
-- SPEC front panel leds
led_act_o : out std_logic;
led_link_o : out std_logic;
-- SPEC PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- UART
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
carrier_onewire_b : inout std_logic; -- SPEC 1-wire
button1_i : in std_logic := '1';
-- DDR3 interface
DDR3_CAS_N : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_ZIO : inout std_logic;
DDR3_RZQ : inout std_logic;
------------------------------------------------------------------------
-- GN4124 PCI bridge pins
------------------------------------------------------------------------
gn_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gn_gpio : out std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- Flash SPI
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := 'L';
-- DDR (bank 3)
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
-- GN4124 interface
gn_rst_n_i : in std_logic; -- reset from gn4124 (rstout18_n)
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- pcie to local [inbound data] - rx
gn_p2l_rdy : out std_logic; -- rx buffer full flag
gn_p2l_clkn : in std_logic; -- receiver source synchronous clock-
gn_p2l_clkp : in std_logic; -- receiver source synchronous clock+
gn_p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
gn_p2l_dframe : in std_logic; -- receive frame
gn_p2l_valid : in std_logic; -- receive data valid
gn_p2l_rdy_o : out std_logic; -- rx buffer full flag
gn_p2l_clk_n_i : in std_logic; -- receiver source synchronous clock-
gn_p2l_clk_p_i : in std_logic; -- receiver source synchronous clock+
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- parallel receive data
gn_p2l_dframe_i : in std_logic; -- receive frame
gn_p2l_valid_i : in std_logic; -- receive data valid
-- inbound buffer request/status
gn_p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
gn_rx_error : out std_logic; -- receive error
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- pcie write request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- pcie write ready
gn_rx_error_o : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
gn_l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
gn_l2p_dframe : out std_logic; -- transmit data frame
gn_l2p_valid : out std_logic; -- transmit data valid
gn_l2p_clkn : out std_logic; -- transmitter source synchronous clock-
gn_l2p_clkp : out std_logic; -- transmitter source synchronous clock+
gn_l2p_edb : out std_logic; -- packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- parallel transmit data
gn_l2p_dframe_o : out std_logic; -- transmit data frame
gn_l2p_valid_o : out std_logic; -- transmit data valid
gn_l2p_clk_n_o : out std_logic; -- transmitter source synchronous clock-
gn_l2p_clk_p_o : out std_logic; -- transmitter source synchronous clock+
gn_l2p_edb_o : out std_logic; -- packet termination and discard
-- outbound buffer status
gn_l2p_rdy : in std_logic; -- tx buffer full flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
gn_tx_error : in std_logic; -- transmit error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
gn_l2p_rdy_i : in std_logic; -- tx buffer full flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- local-to-pcie write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
gn_tx_error_i : in std_logic; -- transmit error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
------------------------------------------------------------------------
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
-- FMC slot
------------------------------------------------------------------------
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
fmc0_tdc_pll_sclk_o : out std_logic; -- SPI clock
fmc0_tdc_pll_sdi_o : out std_logic; -- data line for PLL and DAC
fmc0_tdc_pll_cs_o : out std_logic; -- PLL chip select
fmc0_tdc_pll_dac_sync_o : out std_logic; -- DAC chip select
fmc0_tdc_pll_sdo_i : in std_logic; -- not used for the moment
fmc0_tdc_pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
fmc0_tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
fmc0_tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
fmc0_tdc_acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
fmc0_tdc_acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
-- Timing interface with the ACAM on TDC mezzanine
start_from_fpga_o : out std_logic; -- start signal
err_flag_i : in std_logic; -- error flag
int_flag_i : in std_logic; -- interrupt flag
start_dis_o : out std_logic; -- start disable, not used
stop_dis_o : out std_logic; -- stop disable, not used
fmc0_tdc_start_from_fpga_o : out std_logic; -- start signal
fmc0_tdc_err_flag_i : in std_logic; -- error flag
fmc0_tdc_int_flag_i : in std_logic; -- interrupt flag
fmc0_tdc_start_dis_o : out std_logic; -- start disable, not used
fmc0_tdc_stop_dis_o : out std_logic; -- stop disable, not used
-- Data interface with the ACAM on TDC mezzanine
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic; -- chip select for ACAM
oe_n_o : out std_logic; -- output enable for ACAM
rd_n_o : out std_logic; -- read signal for ACAM
wr_n_o : out std_logic; -- write signal for ACAM
ef1_i : in std_logic; -- empty flag iFIFO1
ef2_i : in std_logic; -- empty flag iFIFO2
fmc0_tdc_data_bus_io : inout std_logic_vector(27 downto 0);
fmc0_tdc_address_o : out std_logic_vector(3 downto 0);
fmc0_tdc_cs_n_o : out std_logic; -- chip select for ACAM
fmc0_tdc_oe_n_o : out std_logic; -- output enable for ACAM
fmc0_tdc_rd_n_o : out std_logic; -- read signal for ACAM
fmc0_tdc_wr_n_o : out std_logic; -- write signal for ACAM
fmc0_tdc_ef1_i : in std_logic; -- empty flag iFIFO1
fmc0_tdc_ef2_i : in std_logic; -- empty flag iFIFO2
-- Enable of input Logic on TDC mezzanine
enable_inputs_o : out std_logic; -- enables all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
fmc0_tdc_enable_inputs_o : out std_logic; -- enables all 5 inputs
fmc0_tdc_term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
fmc0_tdc_term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
fmc0_tdc_term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
fmc0_tdc_term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
fmc0_tdc_term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
fmc0_tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
fmc0_tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
fmc0_tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
fmc0_tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
fmc0_tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
fmc0_tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
fmc0_tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
fmc0_tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
fmc0_tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
fmc0_tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
fmc0_tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
fmc0_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
fmc0_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
-- 1-wire interface on TDC mezzanine
mezz_onewire_b : inout std_logic; -- Mezzanine presence (active low)
-- font panel leds
led_act_o : out std_logic;
led_link_o : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic
fmc0_tdc_onewire_b : inout std_logic; -- Mezzanine presence (active low)
-- Presence of a mezzanine
fmc0_prsnt_m2c_n_i : in std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0)
-- Bypass GN4124 core, useful only in simulation
-- Feed fake timestamps bypassing acam - used only in simulation
-- synthesis translate_off
......@@ -297,7 +306,6 @@ entity wr_spec_tdc is
sim_timestamp_valid_i : in std_logic := '0';
sim_timestamp_ready_o : out std_logic
-- synthesis translate_on
);
end wr_spec_tdc;
......@@ -307,108 +315,6 @@ end wr_spec_tdc;
--=================================================================================================
architecture rtl of wr_spec_tdc is
component ddr3_ctrl is
generic (
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
status_o : out std_logic_vector(31 downto 0);
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_odt_o : out std_logic;
ddr3_rst_n_o : out std_logic;
ddr3_cke_o : out std_logic;
ddr3_dm_o : out std_logic;
ddr3_udm_o : out std_logic;
ddr3_dqs_p_b : inout std_logic;
ddr3_dqs_n_b : inout std_logic;
ddr3_udqs_p_b : inout std_logic;
ddr3_udqs_n_b : inout std_logic;
ddr3_clk_p_o : out std_logic;
ddr3_clk_n_o : out std_logic;
ddr3_rzq_b : inout std_logic;
ddr3_zio_b : inout std_logic;
wb0_rst_n_i : in std_logic;
wb0_clk_i : in std_logic;
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
wb0_cyc_i : in std_logic;
wb0_stb_i : in std_logic;
wb0_we_i : in std_logic;
wb0_addr_i : in std_logic_vector(31 downto 0);
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_ack_o : out std_logic;
wb0_stall_o : out std_logic;
p0_cmd_empty_o : out std_logic;
p0_cmd_full_o : out std_logic;
p0_rd_full_o : out std_logic;
p0_rd_empty_o : out std_logic;
p0_rd_count_o : out std_logic_vector(6 downto 0);
p0_rd_overflow_o : out std_logic;
p0_rd_error_o : out std_logic;
p0_wr_full_o : out std_logic;
p0_wr_empty_o : out std_logic;
p0_wr_count_o : out std_logic_vector(6 downto 0);
p0_wr_underrun_o : out std_logic;
p0_wr_error_o : out std_logic;
wb1_rst_n_i : in std_logic;
wb1_clk_i : in std_logic;
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(31 downto 0);
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic;
p1_cmd_empty_o : out std_logic;
p1_cmd_full_o : out std_logic;
p1_rd_full_o : out std_logic;
p1_rd_empty_o : out std_logic;
p1_rd_count_o : out std_logic_vector(6 downto 0);
p1_rd_overflow_o : out std_logic;
p1_rd_error_o : out std_logic;
p1_wr_full_o : out std_logic;
p1_wr_empty_o : out std_logic;
p1_wr_count_o : out std_logic_vector(6 downto 0);
p1_wr_underrun_o : out std_logic;
p1_wr_error_o : out std_logic);
end component ddr3_ctrl;
function f_bool2int (x : boolean) return integer is
begin
if(x) then
......@@ -419,120 +325,55 @@ architecture rtl of wr_spec_tdc is
end f_bool2int;
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPEC.CSR ")));
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 6;
constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
constant c_WB_SLAVE_DMA : integer := 3;
constant c_WB_SLAVE_DMA_EIC : integer := 4;
constant c_WB_SLAVE_WRC : integer := 5; -- White Rabbit PTP core
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_wb_dma_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_wb_dma_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"12000661",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.InterruptCtr")));
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(7 downto 0) :=
(0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00050000"),
4 => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00060000"),
5 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
6 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
7 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
-- Number of masters attached to the primary wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 2;
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00043000",
1 => x"00043001");
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_GENNUM : integer := 0;
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- Clocks and resets
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal rst_ref_125_n : std_logic;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC_TDC : integer := 1; -- TDC core configuration(??)
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- DAC configuration through PCIe/VME
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FMC_TDC => x"0002_0000");
-- mask is 18 bits long and is active-low
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes : not(0x40 -1) = not(0x3F) = c0
c_WB_SLAVE_FMC_TDC => x"0002_0000"); -- 0x20000 bytes : not(0x6200 -1) = not(0x1FFF) = e0000
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Clocks and resets
signal clk_sys_62m5, rst_sys_62m5_n : std_logic;
signal clk_ref_125m, rst_ref_125m_n : std_logic;
signal tdc0_clk_125m : std_logic; -- WR aux cloxk
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Carrier CSR info
signal gn4124_status : std_logic_vector(31 downto 0);
-- VIC
signal irq_to_gn4124 : std_logic;
-- WRabbit time
-- WRPC TM interface and status
signal tm_link_up, tm_time_valid : std_logic;
signal tm_dac_wr_p : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
......@@ -540,18 +381,20 @@ architecture rtl of wr_spec_tdc is
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_clk_aux_lock_en : std_logic;
signal tm_clk_aux_locked : std_logic;
-- EEPROM on mezzanine
signal wrabbit_en, pps_led : std_logic;
-- Interrupts and status
signal ddr_wr_fifo_empty : std_logic; -- not used
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(0 downto 0);
signal gn4124_access : std_logic;
-- FMC TDC
signal tdc_scl_oen, tdc_scl_in : std_logic;
signal tdc_sda_oen, tdc_sda_in : std_logic;
-- SFP EEPROM on mezzanine
signal sfp_scl_out, sfp_scl_in : std_logic;
signal sfp_sda_out, sfp_sda_in : std_logic;
-- Carrier 1-Wire
signal wrc_owr_oe, wrc_owr_data : std_logic;
-- aux
signal tdc0_irq : std_logic;
signal tdc0_clk_125m : std_logic;
signal tdc0_soft_rst_n : std_logic;
signal ddr3_tdc_adr : std_logic_vector(31 downto 0);
......@@ -559,29 +402,19 @@ architecture rtl of wr_spec_tdc is
signal powerup_rst_cnt : unsigned(7 downto 0) := "00000000";
signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
-- GN4124 core DMA port to DDR wishbone bus
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector(31 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
signal wb_dma_sel : std_logic_vector(3 downto 0);
signal wb_dma_cyc : std_logic;
signal wb_dma_stb : std_logic;
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic;
signal wb_dma_stall : std_logic;
signal wb_dma_err : std_logic;
signal wb_dma_rty : std_logic;
signal wb_dma_int : std_logic;
signal tdc_dma_out : t_wishbone_master_out;
signal tdc_dma_in : t_wishbone_master_in;
signal clk_ddr_333m : std_logic;
signal ddr3_calib_done : std_logic;
signal dma_irq : std_logic_vector(1 downto 0);
signal ddr_wr_fifo_empty : std_logic;
signal dma_eic_irq : std_logic;
-- Wishbone buses from FMC ADC cores to DDR controller
signal fmc0_wb_ddr_in : t_wishbone_master_in;
signal fmc0_wb_ddr_out : t_wishbone_master_out;
-- Simulation
signal sim_ts_valid, sim_ts_ready : std_logic;
signal sim_ts : t_tdc_timestamp;
signal ddr3_status : std_logic_vector(31 downto 0);
......@@ -595,8 +428,7 @@ architecture rtl of wr_spec_tdc is
end f_to_string;
signal dma_reg_adr : std_logic_vector(31 downto 0);
signal sim_ts_valid, sim_ts_ready : std_logic;
signal sim_ts : t_tdc_timestamp;
--=================================================================================================
......@@ -610,217 +442,226 @@ begin
sim_timestamp_ready_o <= sim_ts_ready;
-- synthesis translate_on
tdc0_soft_rst_n <= carrier_info_fmc_rst(0) and rst_sys_62m5_n;
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574E_0001", -- WRTD Node (WN) 1
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
-------------------------------------------------------------------------------
-- SPEC Board Wrapper --
-------------------------------------------------------------------------------
cmp_xwrc_board_spec : xwrc_board_spec
inst_spec_base : entity work.spec_base_wr
generic map (
g_simulation => f_bool2int(g_simulation),
g_with_external_clock_input => false,
g_aux_clks => 1,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_fabric_iface => PLAIN,
g_enable_wr_core => true)
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 32,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 1,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 1,
g_FABRIC_IFACE => PLAIN,
g_SIMULATION => g_SIMULATION)
port map (
areset_n_i => button1_i,
areset_edge_n_i => gn_rst_n,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_ddr_o => clk_ddr_333m,
clk_ref_125m_o => clk_ref_125m,
clk_sys_62m5_o => clk_sys_62m5,
clk_aux_i(0) => tdc0_clk_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125_n,
plldac_sclk_o => wr_dac_sclk_o,
plldac_din_o => wr_dac_din_o,
pll25dac_cs_n_o => wr_25dac_cs_n_o,
pll20dac_cs_n_o => wr_20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
onewire_i => wrc_owr_data,
onewire_oen_o => wrc_owr_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
wb_slave_o => cnx_master_in(c_WB_SLAVE_WRC),
wb_slave_i => cnx_master_out(c_WB_SLAVE_WRC),
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr_p,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for 1-wire thermometer
carrier_onewire_b <= '0' when wrc_owr_oe = '1' else 'Z';
wrc_owr_data <= carrier_onewire_b;
---------------------------------------------------------
-- Clocks/ Resets
---------------------------------------------------------
-- 20MHz VCXO
clk_20m_vcxo_i => clk_20m_vcxo_i,
-- 125MHz PLL reference
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
-- 125MHz GTP reference
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
-- 62.5MHz System Clk generated from Xilinx internal PLL
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- 125Hz Ref Clk generated from Xilinx internal PLL
clk_125m_ref_o => clk_ref_125m,
rst_125m_ref_n_o => rst_ref_125m_n,
---------------------------------------------------------
-- GN4124
---------------------------------------------------------
-- Reset from gn4124 (rstout18_n)
gn_rst_n_i => gn_rst_n_i,
-- PCIe-2-Local inbound data - rx
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
-- PCIe-2-Local inbound buffer request/status
gn_p_wr_req_i => gn_p_wr_req_i,
gn_rx_error_o => gn_rx_error_o,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
-- Local-2-Parallel outbound data - tx
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
-- Local-2-Parallel outbound buffer status
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
-- GPIO
gn_gpio_b => gn_gpio_b,
---------------------------------------------------------
-- Carrier peripherals
---------------------------------------------------------
-- LEDs and Buttons
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
-- PCB version
pcbrev_i => pcbrev_i,
-- 1-wire
onewire_b => onewire_b,
-- SPI flash
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
-- UART
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
---------------------------------------------------------
-- SFP
---------------------------------------------------------
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
---------------------------------------------------------
-- DDR (bank 3)
---------------------------------------------------------
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
----------------------------------
ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_wb_cyc_i => fmc0_wb_ddr_out.cyc,
ddr_dma_wb_stb_i => fmc0_wb_ddr_out.stb,
ddr_dma_wb_adr_i => fmc0_wb_ddr_out.adr,
ddr_dma_wb_sel_i => fmc0_wb_ddr_out.sel,
ddr_dma_wb_we_i => fmc0_wb_ddr_out.we,
ddr_dma_wb_dat_i => fmc0_wb_ddr_out.dat,
ddr_dma_wb_ack_o => fmc0_wb_ddr_in.ack,
ddr_dma_wb_stall_o => fmc0_wb_ddr_in.stall,
ddr_dma_wb_dat_o => fmc0_wb_ddr_in.dat,
ddr_wr_fifo_empty_o => ddr_wr_fifo_empty, -- not used
---------------------------------------------------------
-- IRQ
---------------------------------------------------------
irq_user_i => irq_vector,
---------------------------------------------------------
-- White Rabbit
---------------------------------------------------------
wrf_src_o => open,
wrf_src_i => open,
wrf_snk_o => open,
wrf_snk_i => open,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => open,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
-- Aux clocks control
clk_aux_i(0) => tdc0_clk_125m,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr_p,
tm_clk_aux_lock_en_i(0)=> tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0)=> tm_clk_aux_locked,
---------------------------------------------------------
-- FMC TDC application
---------------------------------------------------------
-- FMC EEPROM I2C
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
-- FMC presence
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
-- FMC TDC application
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- 0x00000 -> SDB
-- 0x10000 -> Carrier 1-wire master
-- 0x20000 -> Carrier CSR information
-- 0x30000 -> Vector Interrupt Controller
-- 0x40000 -> TDC mezzanine SDB
-- 0x10000 -> TDC core configuration (including ACAM regs)
-- 0x11000 -> TDC Mezzanine 1-wire master
-- 0x12000 -> TDC Mezzanine Embedded Interrupt Controller
-- 0x13000 -> TDC Mezzanine I2C master
-- 0x14000 -> TDC core timestamps retrieval from memory
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
gen_with_gennum : if g_sim_bypass_gennum = false generate
cmp_gn4124_core : gn4124_core
port map
(rst_n_a_i => gn_rst_n,
status_o => gn4124_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => gn_p2l_clkp,
p2l_clk_n_i => gn_p2l_clkn,
p2l_data_i => gn_p2l_data,
p2l_dframe_i => gn_p2l_dframe,
p2l_valid_i => gn_p2l_valid,
-- P2L Control
p2l_rdy_o => gn_p2l_rdy,
p_wr_req_i => gn_p_wr_req,
p_wr_rdy_o => gn_p_wr_rdy,
rx_error_o => gn_rx_error,
vc_rdy_i => gn_vc_rdy,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => gn_l2p_clkp,
l2p_clk_n_o => gn_l2p_clkn,
l2p_data_o => gn_l2p_data,
l2p_dframe_o => gn_l2p_dframe,
l2p_valid_o => gn_l2p_valid,
-- L2P Control
l2p_edb_o => gn_l2p_edb,
l2p_rdy_i => gn_l2p_rdy,
l_wr_rdy_i => gn_l_wr_rdy,
p_rd_d_rdy_i => gn_p_rd_d_rdy,
tx_error_i => gn_tx_error,
dma_irq_o => dma_irq,
irq_p_i => '0',
irq_p_o => open,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_sys_62m5,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => '0',
csr_rty_i => '0',
dma_clk_i => clk_ref_125m,
dma_adr_o => wb_dma_adr,
dma_dat_o => wb_dma_dat_o,
dma_sel_o => wb_dma_sel,
dma_stb_o => wb_dma_stb,
dma_we_o => wb_dma_we,
dma_cyc_o => wb_dma_cyc,
dma_dat_i => wb_dma_dat_i,
dma_ack_i => wb_dma_ack,
dma_stall_i => wb_dma_stall,
dma_err_i => wb_dma_err,
dma_rty_i => wb_dma_rty,
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => clk_sys_62m5,
dma_reg_adr_i => dma_reg_adr,
dma_reg_dat_i => cnx_master_out(c_WB_SLAVE_DMA).dat,
dma_reg_sel_i => cnx_master_out(c_WB_SLAVE_DMA).sel,
dma_reg_stb_i => cnx_master_out(c_WB_SLAVE_DMA).stb,
dma_reg_we_i => cnx_master_out(c_WB_SLAVE_DMA).we,
dma_reg_cyc_i => cnx_master_out(c_WB_SLAVE_DMA).cyc,
dma_reg_dat_o => cnx_master_in(c_WB_SLAVE_DMA).dat,
dma_reg_ack_o => cnx_master_in(c_WB_SLAVE_DMA).ack,
dma_reg_stall_o => cnx_master_in(c_WB_SLAVE_DMA).stall
);
dma_reg_adr <= "00" & cnx_master_out(c_WB_SLAVE_DMA).adr(31 downto 2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
end generate gen_with_gennum;
gen_without_gennum : if g_sim_bypass_gennum generate
-- synthesis translate_off
cnx_slave_in(c_MASTER_GENNUM) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_GENNUM);
wb_dma_cyc <= '0';
-- synthesis translate_on
end generate gen_without_gennum;
cmp_tdc_mezzanine : entity work.fmc_tdc_wrapper
-- 0x20000 -> TDC mezzanine SDBfmc
-- 0x21000 -> TDC Mezzanine 1-wire master
-- 0x22000 -> TDC core configuration (including ACAM regs)
-- 0x23000 -> TDC Mezzanine Embedded Interrupt Controller
-- 0x24000 -> TDC Mezzanine I2C master
-- 0x25000 -> TDC core FIFO ch1 timestamps retrieval
-- 0x25100 -> TDC core FIFO ch1 timestamps retrieval
-- 0x25200 -> TDC core FIFO ch1 timestamps retrieval
-- 0x25300 -> TDC core FIFO ch1 timestamps retrieval
-- 0x25400 -> TDC core FIFO ch1 timestamps retrieval
cmp_crossbar : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
cmp_fmc_tdc_mezzanine : entity work.fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false,
......@@ -830,47 +671,50 @@ begin
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => tdc0_soft_rst_n,
pll_sclk_o => pll_sclk_o,
pll_sdi_o => pll_sdi_o,
pll_cs_o => pll_cs_o,
pll_dac_sync_o => pll_dac_sync_o,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
tdc_clk_125m_p_i => tdc_clk_125m_p_i,
tdc_clk_125m_n_i => tdc_clk_125m_n_i,
acam_refclk_p_i => acam_refclk_p_i,
acam_refclk_n_i => acam_refclk_n_i,
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
rst_n_a_i => rst_sys_62m5_n, ------------ to be removed
pll_sclk_o => fmc0_tdc_pll_sclk_o,
pll_sdi_o => fmc0_tdc_pll_sdi_o,
pll_cs_o => fmc0_tdc_pll_cs_o,
pll_dac_sync_o => fmc0_tdc_pll_dac_sync_o,
pll_sdo_i => fmc0_tdc_pll_sdo_i,
pll_status_i => fmc0_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc0_tdc_clk_125m_p_i,
tdc_clk_125m_n_i => fmc0_tdc_clk_125m_n_i,
acam_refclk_p_i => fmc0_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc0_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc0_tdc_start_from_fpga_o,
err_flag_i => fmc0_tdc_err_flag_i,
int_flag_i => fmc0_tdc_int_flag_i,
start_dis_o => fmc0_tdc_start_dis_o,
stop_dis_o => fmc0_tdc_stop_dis_o,
data_bus_io => fmc0_tdc_data_bus_io,
address_o => fmc0_tdc_address_o,
cs_n_o => fmc0_tdc_cs_n_o,
oe_n_o => fmc0_tdc_oe_n_o,
rd_n_o => fmc0_tdc_rd_n_o,
wr_n_o => fmc0_tdc_wr_n_o,
ef1_i => fmc0_tdc_ef1_i,
ef2_i => fmc0_tdc_ef2_i,
enable_inputs_o => fmc0_tdc_enable_inputs_o,
term_en_1_o => fmc0_tdc_term_en_1_o,
term_en_2_o => fmc0_tdc_term_en_2_o,
term_en_3_o => fmc0_tdc_term_en_3_o,
term_en_4_o => fmc0_tdc_term_en_4_o,
term_en_5_o => fmc0_tdc_term_en_5_o,
tdc_led_status_o => fmc0_tdc_led_status_o,
tdc_led_trig1_o => fmc0_tdc_led_trig1_o,
tdc_led_trig2_o => fmc0_tdc_led_trig2_o,
tdc_led_trig3_o => fmc0_tdc_led_trig3_o,
tdc_led_trig4_o => fmc0_tdc_led_trig4_o,
tdc_led_trig5_o => fmc0_tdc_led_trig5_o,
mezz_scl_o => tdc_scl_oen,
mezz_sda_o => tdc_sda_oen,
mezz_scl_i => tdc_scl_in,
mezz_sda_i => tdc_sda_in,
mezz_one_wire_b => mezz_onewire_b,
mezz_one_wire_b => fmc0_tdc_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
......@@ -880,209 +724,56 @@ begin
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr_p,
slave_i => cnx_master_out(c_WB_SLAVE_TDC),
slave_o => cnx_master_in(c_WB_SLAVE_TDC),
dma_wb_o => tdc_dma_out,
dma_wb_i => tdc_dma_in,
irq_o => tdc0_irq,
clk_125m_tdc_o => tdc0_clk_125m);
slave_i => cnx_slave_in(c_WB_SLAVE_FMC_TDC),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC_TDC),
dma_wb_i => fmc0_wb_ddr_in,
dma_wb_o => fmc0_wb_ddr_out,
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => tdc0_irq,
irqs_i(1) => dma_eic_irq,
irq_master_o => irq_to_gn4124);
gn_gpio(0) <= irq_to_gn4124;
gn_gpio(1) <= irq_to_gn4124;
irq_o => irq_vector(0),
clk_125m_tdc_o => tdc0_clk_125m);
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
cmp_dma_eic : entity work.dma_eic
port map(
rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).stall,
wb_int_o => dma_eic_irq,
irq_dma_done_i => dma_irq(0),
irq_dma_error_i => dma_irq(1)
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
fmc0_wb_ddr_in.err <= '0';
fmc0_wb_ddr_in.rty <= '0';
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_info : carrier_info
port map
(rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).stall,
carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
-- SPEC board wrapper releases rst_sys_62m5_n only when system clock pll is
-- locked. Therefore we report here '1' - pll locked
carrier_info_stat_sys_pll_lck_i => '1',
carrier_info_stat_ddr3_cal_done_i => ddr3_calib_done,
carrier_info_stat_reserved_i => x"0000000",
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
carrier_info_ctrl_reserved_o => open,
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => carrier_info_fmc_rst);
-- Tristates for TDC mezzanine EEPROM
fmc0_scl_b <= '0' when (tdc_scl_oen = '0') else 'Z';
fmc0_sda_b <= '0' when (tdc_sda_oen = '0') else 'Z';
tdc_scl_in <= fmc0_scl_b;
tdc_sda_in <= fmc0_sda_b;
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
-- Carrier LEDs
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "SPEC_BANK3_32B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => f_to_string(g_SIMULATION),
g_CALIB_SOFT_IP => f_to_string(g_CALIB_SOFT_IP),
g_P0_MASK_SIZE => 4,
g_P0_DATA_PORT_SIZE => 32,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
cmp_pci_access_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => clk_ddr_333m,
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_GENNUM).cyc,
extended_o => gn4124_access);
status_o => ddr3_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_rst_n_i => rst_sys_62m5_n,
wb0_clk_i => clk_sys_62m5,
wb0_sel_i => tdc_dma_out.sel,
wb0_cyc_i => tdc_dma_out.cyc,
wb0_stb_i => tdc_dma_out.stb,
wb0_we_i => tdc_dma_out.we,
wb0_addr_i => ddr3_tdc_adr,
wb0_data_i => tdc_dma_out.dat,
wb0_data_o => open,
wb0_ack_o => tdc_dma_in.ack,
wb0_stall_o => tdc_dma_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_ref_125_n,
wb1_clk_i => clk_ref_125m,
wb1_sel_i => wb_dma_sel,
wb1_cyc_i => wb_dma_cyc,
wb1_stb_i => wb_dma_stb,
wb1_we_i => wb_dma_we,
wb1_addr_i => wb_dma_adr,
wb1_data_i => wb_dma_dat_o,
wb1_data_o => wb_dma_dat_i,
wb1_ack_o => wb_dma_ack,
wb1_stall_o => wb_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr3_tdc_adr <= "00" & tdc_dma_out.adr(31 downto 2);
ddr3_calib_done <= ddr3_status(0);
-- unused Wishbone signals
wb_dma_err <= '0';
wb_dma_rty <= '0';
wb_dma_int <= '0';
aux_leds_o(0) <= not gn4124_access;
aux_leds_o(1) <= '1';
aux_leds_o(2) <= not tm_time_valid;
aux_leds_o(3) <= not pps_led;
------------------------------------------------------------------------------
-- check if they are needed
------------------------------------------------------------------------------
-------------ddr3_tdc_adr <= "00" & tdc_dma_out.adr(31 downto 2);
-------------dma_reg_adr <= "00" & cnx_master_out(c_WB_SLAVE_DMA).adr(31 downto 2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
-- Convert 32-bit word address into byte address for crossbar
------------cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for TDC mezzanine EEPROM
mezz_sys_scl_b <= '0' when (tdc_scl_oen = '0') else 'Z';
mezz_sys_sda_b <= '0' when (tdc_sda_oen = '0') else 'Z';
tdc_scl_in <= mezz_sys_scl_b;
tdc_sda_in <= mezz_sys_sda_b;
end rtl;
----------------------------------------------------------------------------------------------------
......
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