hdl/testbench/spec/main.sv · 1251d7a5ab18cdaae25b2b66749b26c419bbc53b · Projects / FMC TDC 1ns 5cha · Open Hardware Repository

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wip: applied the convention (spec_base_wr) to the top level of the design; · 1251d7a5
Evangelia Gousiou authored Sep 27, 2019
```
updated submodules;
added missing sim files
```
1251d7a5

main.sv 5.9 KB