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FMC TDC 1ns 5cha
Commit 1251d7a5 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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wip: applied the convention (spec_base_wr) to the top level of the design; 

updated submodules;
added missing sim files
parent 7d68c05f
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.gitmodules
View file @ 1251d7a5
[submodule "ip-cores/general-cores"]
[submodule "hdl/ip-cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
\ No newline at end of file
ddr3-sp6-core @ 1a129390
Subproject commit 8618c1e154c322be34cb069b62d8293527744dda
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores @ 96728bc0
Subproject commit 4d36bf859fa6071acf11d86e1d57ab3a65a5f776
Subproject commit 96728bc02801f5343597e2a7bb916fde33dc0139
gn4124-core @ 91d5efac
Subproject commit 017ef8c1453664414e871a7992496e15951f32fe
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ b3d2bfc2
Subproject commit b3d2bfc24e01b95acef5d4240cb476c3f2f42566
wr-cores @ 25deb517
Subproject commit 5bb966b6868537eb1bf1acf3dd04df95985966bb
Subproject commit 25deb51759cf467df4fdeeca3bd10e4e793f71ca
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 1251d7a5
......@@ -645,7 +645,7 @@ begin
i2c_scl_oen_o <= sys_scl_oe_n;
i2c_scl_o <= sys_scl_out;
U_OnewireIF : gc_ds182x_interface
U_OnewireIF : gc_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62500,
g_USE_INTERNAL_PPS => true)
......
hdl/rtl/tdc_core_pkg.vhd
View file @ 1251d7a5
......@@ -336,8 +336,8 @@ package tdc_core_pkg is
-- corresponds to:
constant c_STARTING_UTC_ADR : std_logic_vector(7 downto 0) := x"20"; -- address 0x51080 of GN4124 BAR 0
constant c_ACAM_INPUTS_EN_ADR : std_logic_vector(7 downto 0) := x"21"; -- address 0x51084 of GN4124 BAR 0
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_FMC_ID_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_SPARE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
......
hdl/syn/spec/Makefile
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hdl/syn/spec/Manifest.py
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board = "spec"
target = "xilinx"
action = "synthesis"
......@@ -11,5 +12,19 @@ syn_project = "wr_spec_tdc.xise"
syn_tool = "ise"
top_module = "wr_spec_tdc"
files = ["buildinfo_pkg.vhd"]
modules = { "local" : [ "../../top/spec" ] }
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
ctrls = ["bank3_32b_32b"]
hdl/syn/spec/wr_spec_tdc.xise
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This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/include/timestamp_fifo_regs.vh 0 → 100644
View file @ 1251d7a5
`define ADDR_TSF_DELTA1 6'h0
`define ADDR_TSF_DELTA2 6'h4
`define ADDR_TSF_DELTA3 6'h8
`define ADDR_TSF_OFFSET1 6'hc
`define ADDR_TSF_OFFSET2 6'h10
`define ADDR_TSF_OFFSET3 6'h14
`define ADDR_TSF_CSR 6'h18
`define TSF_CSR_DELTA_READY_OFFSET 0
`define TSF_CSR_DELTA_READY 32'h00000001
`define TSF_CSR_DELTA_READ_OFFSET 1
`define TSF_CSR_DELTA_READ 32'h00000002
`define TSF_CSR_RST_SEQ_OFFSET 2
`define TSF_CSR_RST_SEQ 32'h00000004
`define TSF_CSR_DELTA_REF_OFFSET 3
`define TSF_CSR_DELTA_REF 32'h00000038
`define TSF_CSR_RAW_MODE_OFFSET 6
`define TSF_CSR_RAW_MODE 32'h00000040
`define ADDR_TSF_FIFO_R0 6'h1c
`define TSF_FIFO_R0_TS0_OFFSET 0
`define TSF_FIFO_R0_TS0 32'hffffffff
`define ADDR_TSF_FIFO_R1 6'h20
`define TSF_FIFO_R1_TS1_OFFSET 0
`define TSF_FIFO_R1_TS1 32'hffffffff
`define ADDR_TSF_FIFO_R2 6'h24
`define TSF_FIFO_R2_TS2_OFFSET 0
`define TSF_FIFO_R2_TS2 32'hffffffff
`define ADDR_TSF_FIFO_R3 6'h28
`define TSF_FIFO_R3_TS3_OFFSET 0
`define TSF_FIFO_R3_TS3 32'hffffffff
`define ADDR_TSF_FIFO_CSR 6'h2c
`define TSF_FIFO_CSR_FULL_OFFSET 16
`define TSF_FIFO_CSR_FULL 32'h00010000
`define TSF_FIFO_CSR_EMPTY_OFFSET 17
`define TSF_FIFO_CSR_EMPTY 32'h00020000
`define TSF_FIFO_CSR_CLEAR_BUS_OFFSET 18
`define TSF_FIFO_CSR_CLEAR_BUS 32'h00040000
`define TSF_FIFO_CSR_USEDW_OFFSET 0
`define TSF_FIFO_CSR_USEDW 32'h0000003f
hdl/testbench/spec/Manifest.py
View file @ 1251d7a5
......@@ -8,8 +8,29 @@ target = "xilinx"
fetchto = "../../ip_cores"
include_dirs=[ "../../sim", "../include" ]
vcom_opt = "-mixedsvvh l"
files = [ "main.sv" ]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }
include_dirs = [
"../include",
"../../sim",
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim",
fetchto + "/general-cores/modules/wishbone/wb_lm32/src",
fetchto + "/wr-cores/sim",
fetchto + "/general-cores/modules/wishbone/wb_spi",
]
ctrls = ["bank3_32b_32b"]
\ No newline at end of file
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm" ] }
ctrls = ["bank3_32b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
\ No newline at end of file
hdl/testbench/spec/buildinfo_pkg.vhd 0 → 100644
View file @ 1251d7a5
-- Buildinfo for project main
--
-- This file was automatically generated; do not edit
package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:7d68c05fc60844172732a01f54f436f71e7d76c6" & LF
& "syntool:modelsim" & LF
& "syndate:2019-09-26, 17:01 CEST" & LF
& "synauth:Evangelia Gousiou" & LF;
end buildinfo_pkg;
hdl/testbench/spec/main.sv
View file @ 1251d7a5
......@@ -8,6 +8,7 @@ import tdc_core_pkg::*;
`include "vhd_wishbone_master.svh"
`include "acam_model.svh"
`include "softpll_regs_ng.vh"
`include "gn4124_bfm.svh"
typedef struct {
uint32_t tai;
......@@ -45,14 +46,19 @@ class FmcTdcDriver;
task automatic init();
uint32_t d;
readl('h000000, d);
readl('h20000, d);
$display("address 0x20000: %x", d);
if( d != 'h5344422d )
begin
$error("!!!!address 0x0 %x!!!!", d);
$error("Can't read the SDB signature.");
$stop;
end
writel('h20a0, 1234); // set UTC
writel('h20fc, 1<<9); // load UTC
......@@ -172,14 +178,14 @@ module main;
.D(tdc_data)
);
IGN4124PCIMaster Host
(
);
wr_spec_tdc
#(
.g_with_wr_phy(0),
.g_simulation(1),
.g_calib_soft_ip(0),
.g_sim_bypass_gennum(1)
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
......@@ -187,57 +193,70 @@ module main;
.clk_125m_gtp_n_i(~clk_125m),
.tdc_clk_125m_p_i(clk_125m),
.tdc_clk_125m_n_i(~clk_125m),
.fmc0_tdc_clk_125m_p_i(clk_125m),
.fmc0_tdc_clk_125m_n_i(~clk_125m),
.acam_refclk_p_i(clk_acam),
.acam_refclk_n_i(~clk_acam),
.fmc0_tdc_acam_refclk_p_i(clk_acam),
.fmc0_tdc_acam_refclk_n_i(~clk_acam),
.clk_20m_vcxo_i(clk_20m),
.pll_status_i(1'b1),
.fmc0_tdc_pll_status_i(1'b1),
.ef1_i(tdc_ef1),
.ef2_i(tdc_ef2),
.err_flag_i(tdc_err_flag),
.int_flag_i(tdc_int_flag),
.rd_n_o(tdc_rd_n),
.wr_n_o(tdc_wr_n),
.oe_n_o(tdc_oe_n),
.cs_n_o(tdc_cs_n),
.data_bus_io(tdc_data),
.address_o(tdc_addr),
.start_from_fpga_o(tdc_start),
.start_dis_o(tdc_start_dis),
.stop_dis_o(tdc_stop_dis[1]),
.fmc0_tdc_ef1_i(tdc_ef1),
.fmc0_tdc_ef2_i(tdc_ef2),
.fmc0_tdc_err_flag_i(tdc_err_flag),
.fmc0_tdc_int_flag_i(tdc_int_flag),
.fmc0_tdc_rd_n_o(tdc_rd_n),
.fmc0_tdc_wr_n_o(tdc_wr_n),
.fmc0_tdc_oe_n_o(tdc_oe_n),
.fmc0_tdc_cs_n_o(tdc_cs_n),
.fmc0_tdc_data_bus_io(tdc_data),
.fmc0_tdc_address_o(tdc_addr),
.fmc0_tdc_start_from_fpga_o(tdc_start),
.fmc0_tdc_start_dis_o(tdc_start_dis),
.fmc0_tdc_stop_dis_o(tdc_stop_dis[1]),
.sim_wb_i(Host.out),
.sim_wb_o(Host.in)
`GENNUM_WIRE_SPEC_BTRAIN_REF(Host)
);
assign tdc_stop_dis[4] = tdc_stop_dis[1];
assign tdc_stop_dis[3] = tdc_stop_dis[1];
assign tdc_stop_dis[2] = tdc_stop_dis[1];
IVHDWishboneMaster Host
(
.clk_i (DUT.clk_sys_62m5),
.rst_n_i (DUT.rst_sys_62m5_n)
);
// IVHDWishboneMaster Host
// (
// .clk_i (DUT.clk_sys_62m5),
// .rst_n_i (DUT.rst_sys_62m5_n)
// );
initial
begin
CBusAccessor acc;
FmcTdcDriver drv;
const uint64_t tdc1_base = 'h40000;
const uint64_t tdc1_base = 'h20000;
uint64_t d;
acc = Host.get_accessor();
#10us;
$display("Un-reset FMCs...");
acc.write('h02000c, 'h3);
//$display("Un-reset FMCs...");
//acc.write('h02000c, 'h3);
acc.read('h20000, d);
$display("address 0x20000: %x", d);
acc.read('h22004, d);
$display("address 0x22004: %x", d);
acc.write('h2208c, 1234); // test
acc.read('h2208c, d);
$display("address 0x2208c: %x", d);
acc.write('h22080, 1234); // starting UTC
acc.write('h220fc, 1<<9); // load UTC
drv = new (acc, 'h40000, 0 );
......
hdl/top/spec/Manifest.py
View file @ 1251d7a5
......@@ -6,11 +6,12 @@ fetchto = "../../ip_cores"
modules = {
"local" : [ "../../rtl/",
"../../ip_cores/gn4124-core",
"../../ip_cores/general-cores",
"../../ip_cores/gn4124-core",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/ddr3-sp6-core"
"../../ip_cores/ddr3-sp6-core",
"../../ip_cores/spec"
]
}
hdl/top/spec/wr_spec_tdc.ucf
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hdl/top/spec/wr_spec_tdc.vhd
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