Programming languages used in this repository
-
VHDL
69.34 %
-
C
9.8 %
-
SystemVerilog
9.8 %
-
Stata
7.38 %
-
Python
2.39 %
-
Makefile
0.55 %
-
Lua
0.47 %
-
Tcl
0.12 %
-
Verilog
0.09 %
-
Shell
0.04 %
-
sed
0.03 %
Commit statistics for master Mar 09 - Nov 17
- Total: 1070 commits
- Average per day: 0.3 commits
- Authors: 20
Commits per day of month
Commits per weekday
Commits per day hour (UTC)