hdl/top/spec/wr_spec_tdc.vhd · a76db15936683ebbf190bf4980e3856b08df2493 · Projects / FMC TDC 1ns 5cha - Gateware · Open Hardware Repository

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wr_spec_tdc: two fixes in DDR DMA connection: · a76db159
Tomasz Wlostowski authored May 07, 2020
```
- the clock should be clk_sys_62m5
- DDR controller in the SPEC assumes WORD addressing on Wishbone
```
a76db159

wr_spec_tdc.vhd 37.6 KB