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FMC DEL 1ns 4cha
Commit ecd0bb00 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'tom-spec-convention' into proposed_master

parents eca0894f 32f77963
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.gitmodules
View file @ ecd0bb00
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
doc/design-notes/fd_main_regs.in
View file @ ecd0bb00
......@@ -125,19 +125,27 @@ Timestamp Buffer Debug Values Register
REG @tab
@code{TSBR_ADVANCE} @tab
Timestamp Buffer Advance Register
@item @code{0x7c} @tab
REG @tab
@code{FMC_SLOT_ID} @tab
FMC Slot ID Register
@item @code{0x80} @tab
REG @tab
@code{IODELAY_ADJ} @tab
I/O Delay Adjust Register
@item @code{0xa0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x84} @tab
@item @code{0xa4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x88} @tab
@item @code{0xa8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0x8c} @tab
@item @code{0xac} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
......@@ -354,6 +362,11 @@ Stop disable
@code{ALUTRIG}
@tab @code{0} @tab
Pulse <code>Alutrigger</code> line
@item @code{8}
@tab W/O @tab
@code{IDELAY_CE}
@tab @code{0} @tab
IDELAY CE (pulse)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -365,6 +378,7 @@ Pulse <code>Alutrigger</code> line
@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@item @code{IDELAY_CE} @tab Write 1 to pulse the IDELAY CE line for 1 clock tick.
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
......@@ -791,6 +805,26 @@ Debug value
@tab @code{0} @tab
Advance buffer readout
@end multitable
@regsection @code{FMC_SLOT_ID} - FMC Slot ID Register
Index of the hardware FMC slot the card is in.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{SLOT_ID}
@tab @code{X} @tab
Slot ID
@end multitable
@regsection @code{IODELAY_ADJ} - I/O Delay Adjust Register
Setup time adjust for certain signals (e.g. TDC_START).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{5...0}
@tab R/W @tab
@code{N_TAPS}
@tab @code{X} @tab
Number of delay line taps.
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
......
hdl/include/jittery_delay.svh
View file @ ecd0bb00
`timescale 10fs/10fs
module jittery_delay
(
......
hdl/include/regs/fd_main_regs.vh
View file @ ecd0bb00
......@@ -53,6 +53,8 @@
`define FD_TDCSR_STOP_DIS 32'h00000040
`define FD_TDCSR_ALUTRIG_OFFSET 7
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......@@ -155,28 +157,34 @@
`define ADDR_FD_TSBR_ADVANCE 8'h78
`define FD_TSBR_ADVANCE_ADV_OFFSET 0
`define FD_TSBR_ADVANCE_ADV 32'h00000001
`define ADDR_FD_EIC_IDR 8'h80
`define ADDR_FD_FMC_SLOT_ID 8'h7c
`define FD_FMC_SLOT_ID_SLOT_ID_OFFSET 0
`define FD_FMC_SLOT_ID_SLOT_ID 32'h0000000f
`define ADDR_FD_IODELAY_ADJ 8'h80
`define FD_IODELAY_ADJ_N_TAPS_OFFSET 0
`define FD_IODELAY_ADJ_N_TAPS 32'h0000003f
`define ADDR_FD_EIC_IDR 8'ha0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IDR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IDR_DMTD_SPLL 32'h00000002
`define FD_EIC_IDR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IDR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IER 8'h84
`define ADDR_FD_EIC_IER 8'ha4
`define FD_EIC_IER_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IER_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IER_DMTD_SPLL_OFFSET 1
`define FD_EIC_IER_DMTD_SPLL 32'h00000002
`define FD_EIC_IER_SYNC_STATUS_OFFSET 2
`define FD_EIC_IER_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IMR 8'h88
`define ADDR_FD_EIC_IMR 8'ha8
`define FD_EIC_IMR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IMR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IMR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IMR_DMTD_SPLL 32'h00000002
`define FD_EIC_IMR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IMR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_ISR 8'h8c
`define ADDR_FD_EIC_ISR 8'hac
`define FD_EIC_ISR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_ISR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_ISR_DMTD_SPLL_OFFSET 1
......
hdl/include/tunable_clock_gen.svh
View file @ ecd0bb00
......@@ -10,8 +10,8 @@ module tunable_clock_gen
parameter g_tunable = 0;
parameter g_tuning_range = 20e-6; // 20 ppm
parameter g_tuning_voltage = 1.0;
parameter real g_period = 8ns;
parameter real g_jitter = 10ps;
parameter time g_period = 8ns;
parameter time g_jitter = 10ps;
reg clk = 1'b1;
......
hdl/include/vme64x_bfm/svec_vme_buffers.svh
View file @ ecd0bb00
......@@ -162,6 +162,16 @@ function automatic bit[5:0] _gen_ga(int slot);
return {^slot_id, ~slot_id};
endfunction // _gen_ga
function automatic bit[4:0] _gen_ga_convention(int slot);
bit[4:0] slot_id = slot;
return {~slot_id};
endfunction // _gen_ga
function automatic bit _gen_gap_convention(int slot);
bit[4:0] slot_id = slot;
return ^slot_id;
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
......@@ -190,4 +200,30 @@ endfunction // _gen_ga
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
`define WIRE_VME_PINS_CONVENTION(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_SYSRESET_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga_convention(slot_id)),\
.VME_GAP_i(_gen_gap_convention(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_IRQ_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
ddr3-sp6-core @ 1a129390
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores @ 4f414ece
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
Subproject commit 4f414ececa8286f49bc6324425a00b9561884375
gn4124-core @ 91d5efac
Subproject commit 5ffe9f5344e22262d1badeef21b8426d20948368
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ 7911a138
Subproject commit 7911a1387bd47bc74e52957509ba7f303b5880b8
svec @ 41415b81
Subproject commit 41415b8141e5466248e55eadd30ba4a68e4b3e21
vme64x-core @ 366ca4db
Subproject commit 633d31749b104d4ca04c569cf3e30c5a6c9902b5
Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
wr-cores @ ad01cd09
Subproject commit c466a66b4d17173d3ee5e18af26a2d263a760aa0
Subproject commit ad01cd0965381808974decabd924c02ce902a3cc
hdl/rtl/fd_acam_timestamper.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-07-02
-- Last update: 2019-03-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -423,21 +423,10 @@ begin -- behave
-- Input: tdc_start_i
-- Output: tdc_start_d
--
-- A synchronizer chain for detecting the relation between clk_tdc_i
-- and clk_ref_i. Since both clocks are almost in phase, the first stage
-- reacts to the falling edge of the reference clock to satisfy setup/hold
-- requirements.
--
p_sync_tdclk_fedge : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
end if;
end process;
p_sync_tdclk_redge : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
tdc_start_d(1) <= tdc_start_d(0);
tdc_start_d(2) <= tdc_start_d(1);
end if;
......
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ ecd0bb00
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -78,37 +78,63 @@ package fd_channel_wbgen2_pkg is
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end component;
end package;
package body fd_channel_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
variable tmp: t_fd_channel_in_registers;
variable tmp: t_fd_channel_in_registers;
begin
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ ecd0bb00
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -18,7 +18,7 @@ use work.fd_channel_wbgen2_pkg.all;
entity fd_channel_wb_slave is
port (
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
......@@ -29,11 +29,13 @@ entity fd_channel_wb_slave is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
);
end fd_channel_wb_slave;
architecture syn of fd_channel_wb_slave is
......@@ -94,17 +96,12 @@ signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
......@@ -490,15 +487,15 @@ begin
end if;
end if;
end if;
end process;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_enable_o <= '0';
fd_channel_dcr_enable_sync0 <= '0';
......@@ -508,14 +505,14 @@ begin
fd_channel_dcr_enable_sync1 <= fd_channel_dcr_enable_sync0;
regs_o.dcr_enable_o <= fd_channel_dcr_enable_sync1;
end if;
end process;
end process;
-- Delay mode select
regs_o.dcr_mode_o <= fd_channel_dcr_mode_int;
regs_o.dcr_mode_o <= fd_channel_dcr_mode_int;
-- Pulse generator arm
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_pg_arm_o <= '0';
fd_channel_dcr_pg_arm_sync0 <= '0';
......@@ -527,13 +524,13 @@ begin
fd_channel_dcr_pg_arm_sync2 <= fd_channel_dcr_pg_arm_sync1;
regs_o.dcr_pg_arm_o <= fd_channel_dcr_pg_arm_sync2 and (not fd_channel_dcr_pg_arm_sync1);
end if;
end process;
end process;
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_pg_trig_sync0 <= '0';
fd_channel_dcr_pg_trig_sync1 <= '0';
......@@ -541,12 +538,12 @@ begin
fd_channel_dcr_pg_trig_sync0 <= regs_i.dcr_pg_trig_i;
fd_channel_dcr_pg_trig_sync1 <= fd_channel_dcr_pg_trig_sync0;
end if;
end process;
end process;
-- Update delay/absolute trigger time
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_update_o <= '0';
fd_channel_dcr_update_sync0 <= '0';
......@@ -558,13 +555,13 @@ begin
fd_channel_dcr_update_sync2 <= fd_channel_dcr_update_sync1;
regs_o.dcr_update_o <= fd_channel_dcr_update_sync2 and (not fd_channel_dcr_update_sync1);
end if;
end process;
end process;
-- Delay update done flag
-- synchronizer chain for field : Delay update done flag (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_upd_done_sync0 <= '0';
fd_channel_dcr_upd_done_sync1 <= '0';
......@@ -572,12 +569,12 @@ begin
fd_channel_dcr_upd_done_sync0 <= regs_i.dcr_upd_done_i;
fd_channel_dcr_upd_done_sync1 <= fd_channel_dcr_upd_done_sync0;
end if;
end process;
end process;
-- Force calibration delay
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_force_dly_o <= '0';
fd_channel_dcr_force_dly_sync0 <= '0';
......@@ -589,17 +586,17 @@ begin
fd_channel_dcr_force_dly_sync2 <= fd_channel_dcr_force_dly_sync1;
regs_o.dcr_force_dly_o <= fd_channel_dcr_force_dly_sync2 and (not fd_channel_dcr_force_dly_sync1);
end if;
end process;
end process;
-- Disable fine part update
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
-- Force output high
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
-- Fine range in SY89825 taps.
-- asynchronous std_logic_vector register : Fine range in SY89825 taps. (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_frr_swb_s0 <= '0';
fd_channel_frr_swb_s1 <= '0';
......@@ -613,37 +610,39 @@ begin
regs_o.frr_o <= fd_channel_frr_int;
end if;
end if;
end process;
end process;
-- TAI seconds (MSB)
regs_o.u_starth_o <= fd_channel_u_starth_int;
regs_o.u_starth_o <= fd_channel_u_starth_int;
-- TAI seconds (LSB)
regs_o.u_startl_o <= fd_channel_u_startl_int;
regs_o.u_startl_o <= fd_channel_u_startl_int;
-- Reference clock cycles
regs_o.c_start_o <= fd_channel_c_start_int;
regs_o.c_start_o <= fd_channel_c_start_int;
-- Fractional part
regs_o.f_start_o <= fd_channel_f_start_int;
regs_o.f_start_o <= fd_channel_f_start_int;
-- TAI seconds (MSB)
regs_o.u_endh_o <= fd_channel_u_endh_int;
regs_o.u_endh_o <= fd_channel_u_endh_int;
-- TAI seconds (LSB)
regs_o.u_endl_o <= fd_channel_u_endl_int;
regs_o.u_endl_o <= fd_channel_u_endl_int;
-- Reference clock cycles
regs_o.c_end_o <= fd_channel_c_end_int;
regs_o.c_end_o <= fd_channel_c_end_int;
-- Fractional part
regs_o.f_end_o <= fd_channel_f_end_int;
regs_o.f_end_o <= fd_channel_f_end_int;
-- TAI seconds
regs_o.u_delta_o <= fd_channel_u_delta_int;
regs_o.u_delta_o <= fd_channel_u_delta_int;
-- Reference clock cycles
regs_o.c_delta_o <= fd_channel_c_delta_int;
regs_o.c_delta_o <= fd_channel_c_delta_int;
-- Fractional part
regs_o.f_delta_o <= fd_channel_f_delta_int;
regs_o.f_delta_o <= fd_channel_f_delta_int;
-- Repeat Count
regs_o.rcr_rep_cnt_o <= fd_channel_rcr_rep_cnt_int;
regs_o.rcr_rep_cnt_o <= fd_channel_rcr_rep_cnt_int;
-- Continuous Waveform Mode
regs_o.rcr_cont_o <= fd_channel_rcr_cont_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
regs_o.rcr_cont_o <= fd_channel_rcr_cont_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/fd_delay_channel_driver.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-07-18
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ ecd0bb00
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:16 2013
-- Created : Tue Oct 22 18:06:55 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -56,6 +56,8 @@ package fd_main_wbgen2_pkg is
i2cr_sda_in_i : std_logic;
tder1_vcxo_freq_i : std_logic_vector(31 downto 0);
tsbr_debug_i : std_logic_vector(31 downto 0);
fmc_slot_id_slot_id_i : std_logic_vector(3 downto 0);
iodelay_adj_n_taps_i : std_logic_vector(5 downto 0);
end record;
constant c_fd_main_in_registers_init_value: t_fd_main_in_registers := (
......@@ -93,7 +95,9 @@ package fd_main_wbgen2_pkg is
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0',
tder1_vcxo_freq_i => (others => '0'),
tsbr_debug_i => (others => '0')
tsbr_debug_i => (others => '0'),
fmc_slot_id_slot_id_i => (others => '0'),
iodelay_adj_n_taps_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -125,6 +129,7 @@ package fd_main_wbgen2_pkg is
tdcsr_start_en_o : std_logic;
tdcsr_stop_dis_o : std_logic;
tdcsr_alutrig_o : std_logic;
tdcsr_idelay_ce_o : std_logic;
calr_cal_pulse_o : std_logic;
calr_cal_pps_o : std_logic;
calr_cal_dmtd_o : std_logic;
......@@ -152,6 +157,8 @@ package fd_main_wbgen2_pkg is
i2cr_sda_out_o : std_logic;
tder2_pelt_drive_o : std_logic_vector(31 downto 0);
tsbr_advance_adv_o : std_logic;
iodelay_adj_n_taps_o : std_logic_vector(5 downto 0);
iodelay_adj_n_taps_load_o : std_logic;
end record;
constant c_fd_main_out_registers_init_value: t_fd_main_out_registers := (
......@@ -181,6 +188,7 @@ package fd_main_wbgen2_pkg is
tdcsr_start_en_o => '0',
tdcsr_stop_dis_o => '0',
tdcsr_alutrig_o => '0',
tdcsr_idelay_ce_o => '0',
calr_cal_pulse_o => '0',
calr_cal_pps_o => '0',
calr_cal_dmtd_o => '0',
......@@ -207,72 +215,111 @@ package fd_main_wbgen2_pkg is
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
tder2_pelt_drive_o => (others => '0'),
tsbr_advance_adv_o => '0'
tsbr_advance_adv_o => '0',
iodelay_adj_n_taps_o => (others => '0'),
iodelay_adj_n_taps_load_o => '0'
);
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_main_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
regs_i : in t_fd_main_in_registers;
regs_o : out t_fd_main_out_registers
);
end component;
end package;
package body fd_main_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers is
variable tmp: t_fd_main_in_registers;
variable tmp: t_fd_main_in_registers;
begin
tmp.gcr_ddr_locked_i := f_x_to_zero(left.gcr_ddr_locked_i) or f_x_to_zero(right.gcr_ddr_locked_i);
tmp.gcr_fmc_present_i := f_x_to_zero(left.gcr_fmc_present_i) or f_x_to_zero(right.gcr_fmc_present_i);
tmp.tcr_dmtd_stat_i := f_x_to_zero(left.tcr_dmtd_stat_i) or f_x_to_zero(right.tcr_dmtd_stat_i);
tmp.tcr_wr_locked_i := f_x_to_zero(left.tcr_wr_locked_i) or f_x_to_zero(right.tcr_wr_locked_i);
tmp.tcr_wr_present_i := f_x_to_zero(left.tcr_wr_present_i) or f_x_to_zero(right.tcr_wr_present_i);
tmp.tcr_wr_ready_i := f_x_to_zero(left.tcr_wr_ready_i) or f_x_to_zero(right.tcr_wr_ready_i);
tmp.tcr_wr_link_i := f_x_to_zero(left.tcr_wr_link_i) or f_x_to_zero(right.tcr_wr_link_i);
tmp.tm_sech_i := f_x_to_zero(left.tm_sech_i) or f_x_to_zero(right.tm_sech_i);
tmp.tm_secl_i := f_x_to_zero(left.tm_secl_i) or f_x_to_zero(right.tm_secl_i);
tmp.tm_cycles_i := f_x_to_zero(left.tm_cycles_i) or f_x_to_zero(right.tm_cycles_i);
tmp.tdr_i := f_x_to_zero(left.tdr_i) or f_x_to_zero(right.tdr_i);
tmp.tdcsr_empty_i := f_x_to_zero(left.tdcsr_empty_i) or f_x_to_zero(right.tdcsr_empty_i);
tmp.dmtr_in_tag_i := f_x_to_zero(left.dmtr_in_tag_i) or f_x_to_zero(right.dmtr_in_tag_i);
tmp.dmtr_in_rdy_i := f_x_to_zero(left.dmtr_in_rdy_i) or f_x_to_zero(right.dmtr_in_rdy_i);
tmp.dmtr_out_tag_i := f_x_to_zero(left.dmtr_out_tag_i) or f_x_to_zero(right.dmtr_out_tag_i);
tmp.dmtr_out_rdy_i := f_x_to_zero(left.dmtr_out_rdy_i) or f_x_to_zero(right.dmtr_out_rdy_i);
tmp.iecraw_i := f_x_to_zero(left.iecraw_i) or f_x_to_zero(right.iecraw_i);
tmp.iectag_i := f_x_to_zero(left.iectag_i) or f_x_to_zero(right.iectag_i);
tmp.iepd_pdelay_i := f_x_to_zero(left.iepd_pdelay_i) or f_x_to_zero(right.iepd_pdelay_i);
tmp.scr_data_i := f_x_to_zero(left.scr_data_i) or f_x_to_zero(right.scr_data_i);
tmp.scr_ready_i := f_x_to_zero(left.scr_ready_i) or f_x_to_zero(right.scr_ready_i);
tmp.rcrr_i := f_x_to_zero(left.rcrr_i) or f_x_to_zero(right.rcrr_i);
tmp.tsbcr_full_i := f_x_to_zero(left.tsbcr_full_i) or f_x_to_zero(right.tsbcr_full_i);
tmp.tsbcr_empty_i := f_x_to_zero(left.tsbcr_empty_i) or f_x_to_zero(right.tsbcr_empty_i);
tmp.tsbcr_count_i := f_x_to_zero(left.tsbcr_count_i) or f_x_to_zero(right.tsbcr_count_i);
tmp.tsbr_sech_i := f_x_to_zero(left.tsbr_sech_i) or f_x_to_zero(right.tsbr_sech_i);
tmp.tsbr_secl_i := f_x_to_zero(left.tsbr_secl_i) or f_x_to_zero(right.tsbr_secl_i);
tmp.tsbr_cycles_i := f_x_to_zero(left.tsbr_cycles_i) or f_x_to_zero(right.tsbr_cycles_i);
tmp.tsbr_fid_channel_i := f_x_to_zero(left.tsbr_fid_channel_i) or f_x_to_zero(right.tsbr_fid_channel_i);
tmp.tsbr_fid_fine_i := f_x_to_zero(left.tsbr_fid_fine_i) or f_x_to_zero(right.tsbr_fid_fine_i);
tmp.tsbr_fid_seqid_i := f_x_to_zero(left.tsbr_fid_seqid_i) or f_x_to_zero(right.tsbr_fid_seqid_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
tmp.tsbr_debug_i := f_x_to_zero(left.tsbr_debug_i) or f_x_to_zero(right.tsbr_debug_i);
return tmp;
tmp.gcr_ddr_locked_i := f_x_to_zero(left.gcr_ddr_locked_i) or f_x_to_zero(right.gcr_ddr_locked_i);
tmp.gcr_fmc_present_i := f_x_to_zero(left.gcr_fmc_present_i) or f_x_to_zero(right.gcr_fmc_present_i);
tmp.tcr_dmtd_stat_i := f_x_to_zero(left.tcr_dmtd_stat_i) or f_x_to_zero(right.tcr_dmtd_stat_i);
tmp.tcr_wr_locked_i := f_x_to_zero(left.tcr_wr_locked_i) or f_x_to_zero(right.tcr_wr_locked_i);
tmp.tcr_wr_present_i := f_x_to_zero(left.tcr_wr_present_i) or f_x_to_zero(right.tcr_wr_present_i);
tmp.tcr_wr_ready_i := f_x_to_zero(left.tcr_wr_ready_i) or f_x_to_zero(right.tcr_wr_ready_i);
tmp.tcr_wr_link_i := f_x_to_zero(left.tcr_wr_link_i) or f_x_to_zero(right.tcr_wr_link_i);
tmp.tm_sech_i := f_x_to_zero(left.tm_sech_i) or f_x_to_zero(right.tm_sech_i);
tmp.tm_secl_i := f_x_to_zero(left.tm_secl_i) or f_x_to_zero(right.tm_secl_i);
tmp.tm_cycles_i := f_x_to_zero(left.tm_cycles_i) or f_x_to_zero(right.tm_cycles_i);
tmp.tdr_i := f_x_to_zero(left.tdr_i) or f_x_to_zero(right.tdr_i);
tmp.tdcsr_empty_i := f_x_to_zero(left.tdcsr_empty_i) or f_x_to_zero(right.tdcsr_empty_i);
tmp.dmtr_in_tag_i := f_x_to_zero(left.dmtr_in_tag_i) or f_x_to_zero(right.dmtr_in_tag_i);
tmp.dmtr_in_rdy_i := f_x_to_zero(left.dmtr_in_rdy_i) or f_x_to_zero(right.dmtr_in_rdy_i);
tmp.dmtr_out_tag_i := f_x_to_zero(left.dmtr_out_tag_i) or f_x_to_zero(right.dmtr_out_tag_i);
tmp.dmtr_out_rdy_i := f_x_to_zero(left.dmtr_out_rdy_i) or f_x_to_zero(right.dmtr_out_rdy_i);
tmp.iecraw_i := f_x_to_zero(left.iecraw_i) or f_x_to_zero(right.iecraw_i);
tmp.iectag_i := f_x_to_zero(left.iectag_i) or f_x_to_zero(right.iectag_i);
tmp.iepd_pdelay_i := f_x_to_zero(left.iepd_pdelay_i) or f_x_to_zero(right.iepd_pdelay_i);
tmp.scr_data_i := f_x_to_zero(left.scr_data_i) or f_x_to_zero(right.scr_data_i);
tmp.scr_ready_i := f_x_to_zero(left.scr_ready_i) or f_x_to_zero(right.scr_ready_i);
tmp.rcrr_i := f_x_to_zero(left.rcrr_i) or f_x_to_zero(right.rcrr_i);
tmp.tsbcr_full_i := f_x_to_zero(left.tsbcr_full_i) or f_x_to_zero(right.tsbcr_full_i);
tmp.tsbcr_empty_i := f_x_to_zero(left.tsbcr_empty_i) or f_x_to_zero(right.tsbcr_empty_i);
tmp.tsbcr_count_i := f_x_to_zero(left.tsbcr_count_i) or f_x_to_zero(right.tsbcr_count_i);
tmp.tsbr_sech_i := f_x_to_zero(left.tsbr_sech_i) or f_x_to_zero(right.tsbr_sech_i);
tmp.tsbr_secl_i := f_x_to_zero(left.tsbr_secl_i) or f_x_to_zero(right.tsbr_secl_i);
tmp.tsbr_cycles_i := f_x_to_zero(left.tsbr_cycles_i) or f_x_to_zero(right.tsbr_cycles_i);
tmp.tsbr_fid_channel_i := f_x_to_zero(left.tsbr_fid_channel_i) or f_x_to_zero(right.tsbr_fid_channel_i);
tmp.tsbr_fid_fine_i := f_x_to_zero(left.tsbr_fid_fine_i) or f_x_to_zero(right.tsbr_fid_fine_i);
tmp.tsbr_fid_seqid_i := f_x_to_zero(left.tsbr_fid_seqid_i) or f_x_to_zero(right.tsbr_fid_seqid_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
tmp.tsbr_debug_i := f_x_to_zero(left.tsbr_debug_i) or f_x_to_zero(right.tsbr_debug_i);
tmp.fmc_slot_id_slot_id_i := f_x_to_zero(left.fmc_slot_id_slot_id_i) or f_x_to_zero(right.fmc_slot_id_slot_id_i);
tmp.iodelay_adj_n_taps_i := f_x_to_zero(left.iodelay_adj_n_taps_i) or f_x_to_zero(right.iodelay_adj_n_taps_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ ecd0bb00
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:16 2013
-- Created : Tue Oct 22 18:06:55 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -19,7 +19,7 @@ use work.fd_main_wbgen2_pkg.all;
entity fd_main_wb_slave is
port (
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
......@@ -30,6 +30,8 @@ entity fd_main_wb_slave is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
......@@ -43,7 +45,7 @@ entity fd_main_wb_slave is
irq_sync_status_i : in std_logic;
regs_i : in t_fd_main_in_registers;
regs_o : out t_fd_main_out_registers
);
);
end fd_main_wb_slave;
architecture syn of fd_main_wb_slave is
......@@ -138,6 +140,11 @@ signal fd_main_tdcsr_alutrig_int_delay : std_logic ;
signal fd_main_tdcsr_alutrig_sync0 : std_logic ;
signal fd_main_tdcsr_alutrig_sync1 : std_logic ;
signal fd_main_tdcsr_alutrig_sync2 : std_logic ;
signal fd_main_tdcsr_idelay_ce_int : std_logic ;
signal fd_main_tdcsr_idelay_ce_int_delay : std_logic ;
signal fd_main_tdcsr_idelay_ce_sync0 : std_logic ;
signal fd_main_tdcsr_idelay_ce_sync1 : std_logic ;
signal fd_main_tdcsr_idelay_ce_sync2 : std_logic ;
signal fd_main_calr_cal_pulse_int : std_logic ;
signal fd_main_calr_cal_pulse_int_delay : std_logic ;
signal fd_main_calr_cal_pulse_sync0 : std_logic ;
......@@ -260,17 +267,12 @@ signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
......@@ -320,6 +322,8 @@ begin
fd_main_tdcsr_stop_dis_int_delay <= '0';
fd_main_tdcsr_alutrig_int <= '0';
fd_main_tdcsr_alutrig_int_delay <= '0';
fd_main_tdcsr_idelay_ce_int <= '0';
fd_main_tdcsr_idelay_ce_int_delay <= '0';
fd_main_calr_cal_pulse_int <= '0';
fd_main_calr_cal_pulse_int_delay <= '0';
fd_main_calr_cal_pps_int <= '0';
......@@ -377,6 +381,7 @@ begin
fd_main_i2cr_sda_out_int <= '1';
fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
fd_main_tsbr_advance_adv_int <= '0';
regs_o.iodelay_adj_n_taps_load_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -398,6 +403,7 @@ begin
tsbcr_read_ack_o <= '0';
fid_read_ack_o <= '0';
fd_main_tsbr_advance_adv_int <= '0';
regs_o.iodelay_adj_n_taps_load_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -448,6 +454,8 @@ begin
fd_main_tdcsr_stop_dis_int_delay <= '0';
fd_main_tdcsr_alutrig_int <= fd_main_tdcsr_alutrig_int_delay;
fd_main_tdcsr_alutrig_int_delay <= '0';
fd_main_tdcsr_idelay_ce_int <= fd_main_tdcsr_idelay_ce_int_delay;
fd_main_tdcsr_idelay_ce_int_delay <= '0';
fd_main_calr_cal_pulse_int <= fd_main_calr_cal_pulse_int_delay;
fd_main_calr_cal_pulse_int_delay <= '0';
fd_main_calr_psel_swb <= fd_main_calr_psel_swb_delay;
......@@ -491,6 +499,7 @@ begin
fd_main_tsbcr_chan_mask_swb_delay <= '0';
fd_main_tsbcr_rst_seq_int <= fd_main_tsbcr_rst_seq_int_delay;
fd_main_tsbcr_rst_seq_int_delay <= '0';
regs_o.iodelay_adj_n_taps_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -735,6 +744,8 @@ begin
fd_main_tdcsr_stop_dis_int_delay <= wrdata_reg(6);
fd_main_tdcsr_alutrig_int <= wrdata_reg(7);
fd_main_tdcsr_alutrig_int_delay <= wrdata_reg(7);
fd_main_tdcsr_idelay_ce_int <= wrdata_reg(8);
fd_main_tdcsr_idelay_ce_int_delay <= wrdata_reg(8);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -744,7 +755,7 @@ begin
rddata_reg(5) <= '0';
rddata_reg(6) <= '0';
rddata_reg(7) <= '0';
rddata_reg(8) <= 'X';
rddata_reg(8) <= '0';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -1170,7 +1181,74 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.fmc_slot_id_slot_id_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
regs_o.iodelay_adj_n_taps_load_o <= '1';
end if;
rddata_reg(5 downto 0) <= regs_i.iodelay_adj_n_taps_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
......@@ -1208,7 +1286,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
when "101001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
......@@ -1246,7 +1324,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
when "101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(2 downto 0) <= eic_imr_int(2 downto 0);
......@@ -1281,7 +1359,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
when "101011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
......@@ -1325,24 +1403,24 @@ begin
end if;
end if;
end if;
end process;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- State of the reset Line of the Mezzanine (EXT_RST_N pin)
-- pass-through field: State of the reset Line of the Mezzanine (EXT_RST_N pin) in register: Reset Register
regs_o.rstr_rst_fmc_o <= wrdata_reg(0);
regs_o.rstr_rst_fmc_o <= wrdata_reg(0);
-- State of the reset of the Fine Delay Core
-- pass-through field: State of the reset of the Fine Delay Core in register: Reset Register
regs_o.rstr_rst_core_o <= wrdata_reg(1);
regs_o.rstr_rst_core_o <= wrdata_reg(1);
-- Reset magic value
-- pass-through field: Reset magic value in register: Reset Register
regs_o.rstr_lock_o <= wrdata_reg(31 downto 16);
regs_o.rstr_lock_o <= wrdata_reg(31 downto 16);
-- Bypass hardware TDC controller
-- synchronizer chain for field : Bypass hardware TDC controller (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.gcr_bypass_o <= '0';
fd_main_gcr_bypass_sync0 <= '0';
......@@ -1352,13 +1430,13 @@ begin
fd_main_gcr_bypass_sync1 <= fd_main_gcr_bypass_sync0;
regs_o.gcr_bypass_o <= fd_main_gcr_bypass_sync1;
end if;
end process;
end process;
-- Enable trigger input
-- synchronizer chain for field : Enable trigger input (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.gcr_input_en_o <= '0';
fd_main_gcr_input_en_sync0 <= '0';
......@@ -1368,21 +1446,21 @@ begin
fd_main_gcr_input_en_sync1 <= fd_main_gcr_input_en_sync0;
regs_o.gcr_input_en_o <= fd_main_gcr_input_en_sync1;
end if;
end process;
end process;
-- PLL lock status
-- Mezzanine present
-- DMTD Clock Status
-- WR Timing Enable
regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
-- WR Timing Locked
-- WR Core Present
-- WR Core Time Ready
-- WR Core Link Up
-- Capture Current Time
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tcr_cap_time_o <= '0';
fd_main_tcr_cap_time_sync0 <= '0';
......@@ -1394,12 +1472,12 @@ begin
fd_main_tcr_cap_time_sync2 <= fd_main_tcr_cap_time_sync1;
regs_o.tcr_cap_time_o <= fd_main_tcr_cap_time_sync2 and (not fd_main_tcr_cap_time_sync1);
end if;
end process;
end process;
-- Set Current Time
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tcr_set_time_o <= '0';
fd_main_tcr_set_time_sync0 <= '0';
......@@ -1411,13 +1489,13 @@ begin
fd_main_tcr_set_time_sync2 <= fd_main_tcr_set_time_sync1;
regs_o.tcr_set_time_o <= fd_main_tcr_set_time_sync2 and (not fd_main_tcr_set_time_sync1);
end if;
end process;
end process;
-- TAI seconds (MSB)
-- asynchronous std_logic_vector register : TAI seconds (MSB) (type RW/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tm_sech_lw_s0 <= '0';
fd_main_tm_sech_lw_s1 <= '0';
......@@ -1441,13 +1519,13 @@ begin
regs_o.tm_sech_load_o <= '0';
end if;
end if;
end process;
end process;
-- TAI seconds (LSB)
-- asynchronous std_logic_vector register : TAI seconds (LSB) (type RW/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tm_secl_lw_s0 <= '0';
fd_main_tm_secl_lw_s1 <= '0';
......@@ -1471,13 +1549,13 @@ begin
regs_o.tm_secl_load_o <= '0';
end if;
end if;
end process;
end process;
-- Reference clock cycles (0...124999999)
-- asynchronous std_logic_vector register : Reference clock cycles (0...124999999) (type RW/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tm_cycles_lw_s0 <= '0';
fd_main_tm_cycles_lw_s1 <= '0';
......@@ -1501,13 +1579,13 @@ begin
regs_o.tm_cycles_load_o <= '0';
end if;
end if;
end process;
end process;
-- TDC Data
-- asynchronous std_logic_vector register : TDC Data (type RW/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tdr_lw_s0 <= '0';
fd_main_tdr_lw_s1 <= '0';
......@@ -1531,12 +1609,12 @@ begin
regs_o.tdr_load_o <= '0';
end if;
end if;
end process;
end process;
-- Write to TDC
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_write_o <= '0';
fd_main_tdcsr_write_sync0 <= '0';
......@@ -1548,12 +1626,12 @@ begin
fd_main_tdcsr_write_sync2 <= fd_main_tdcsr_write_sync1;
regs_o.tdcsr_write_o <= fd_main_tdcsr_write_sync2 and (not fd_main_tdcsr_write_sync1);
end if;
end process;
end process;
-- Read from TDC
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_read_o <= '0';
fd_main_tdcsr_read_sync0 <= '0';
......@@ -1565,13 +1643,13 @@ begin
fd_main_tdcsr_read_sync2 <= fd_main_tdcsr_read_sync1;
regs_o.tdcsr_read_o <= fd_main_tdcsr_read_sync2 and (not fd_main_tdcsr_read_sync1);
end if;
end process;
end process;
-- Empty flag
-- synchronizer chain for field : Empty flag (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tdcsr_empty_sync0 <= '0';
fd_main_tdcsr_empty_sync1 <= '0';
......@@ -1579,12 +1657,12 @@ begin
fd_main_tdcsr_empty_sync0 <= regs_i.tdcsr_empty_i;
fd_main_tdcsr_empty_sync1 <= fd_main_tdcsr_empty_sync0;
end if;
end process;
end process;
-- Stop enable
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_stop_en_o <= '0';
fd_main_tdcsr_stop_en_sync0 <= '0';
......@@ -1596,12 +1674,12 @@ begin
fd_main_tdcsr_stop_en_sync2 <= fd_main_tdcsr_stop_en_sync1;
regs_o.tdcsr_stop_en_o <= fd_main_tdcsr_stop_en_sync2 and (not fd_main_tdcsr_stop_en_sync1);
end if;
end process;
end process;
-- Start disable
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_start_dis_o <= '0';
fd_main_tdcsr_start_dis_sync0 <= '0';
......@@ -1613,12 +1691,12 @@ begin
fd_main_tdcsr_start_dis_sync2 <= fd_main_tdcsr_start_dis_sync1;
regs_o.tdcsr_start_dis_o <= fd_main_tdcsr_start_dis_sync2 and (not fd_main_tdcsr_start_dis_sync1);
end if;
end process;
end process;
-- Start enable
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_start_en_o <= '0';
fd_main_tdcsr_start_en_sync0 <= '0';
......@@ -1630,12 +1708,12 @@ begin
fd_main_tdcsr_start_en_sync2 <= fd_main_tdcsr_start_en_sync1;
regs_o.tdcsr_start_en_o <= fd_main_tdcsr_start_en_sync2 and (not fd_main_tdcsr_start_en_sync1);
end if;
end process;
end process;
-- Stop disable
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_stop_dis_o <= '0';
fd_main_tdcsr_stop_dis_sync0 <= '0';
......@@ -1647,12 +1725,12 @@ begin
fd_main_tdcsr_stop_dis_sync2 <= fd_main_tdcsr_stop_dis_sync1;
regs_o.tdcsr_stop_dis_o <= fd_main_tdcsr_stop_dis_sync2 and (not fd_main_tdcsr_stop_dis_sync1);
end if;
end process;
end process;
-- Pulse <code>Alutrigger</code> line
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_alutrig_o <= '0';
fd_main_tdcsr_alutrig_sync0 <= '0';
......@@ -1664,12 +1742,29 @@ begin
fd_main_tdcsr_alutrig_sync2 <= fd_main_tdcsr_alutrig_sync1;
regs_o.tdcsr_alutrig_o <= fd_main_tdcsr_alutrig_sync2 and (not fd_main_tdcsr_alutrig_sync1);
end if;
end process;
end process;
-- IDELAY CE (pulse)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tdcsr_idelay_ce_o <= '0';
fd_main_tdcsr_idelay_ce_sync0 <= '0';
fd_main_tdcsr_idelay_ce_sync1 <= '0';
fd_main_tdcsr_idelay_ce_sync2 <= '0';
elsif rising_edge(clk_ref_i) then
fd_main_tdcsr_idelay_ce_sync0 <= fd_main_tdcsr_idelay_ce_int;
fd_main_tdcsr_idelay_ce_sync1 <= fd_main_tdcsr_idelay_ce_sync0;
fd_main_tdcsr_idelay_ce_sync2 <= fd_main_tdcsr_idelay_ce_sync1;
regs_o.tdcsr_idelay_ce_o <= fd_main_tdcsr_idelay_ce_sync2 and (not fd_main_tdcsr_idelay_ce_sync1);
end if;
end process;
-- Generate calibration pulses (type 1 calibration)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.calr_cal_pulse_o <= '0';
fd_main_calr_cal_pulse_sync0 <= '0';
......@@ -1681,13 +1776,13 @@ begin
fd_main_calr_cal_pulse_sync2 <= fd_main_calr_cal_pulse_sync1;
regs_o.calr_cal_pulse_o <= fd_main_calr_cal_pulse_sync2 and (not fd_main_calr_cal_pulse_sync1);
end if;
end process;
end process;
-- PPS calibration output enable.
-- synchronizer chain for field : PPS calibration output enable. (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.calr_cal_pps_o <= '0';
fd_main_calr_cal_pps_sync0 <= '0';
......@@ -1697,15 +1792,15 @@ begin
fd_main_calr_cal_pps_sync1 <= fd_main_calr_cal_pps_sync0;
regs_o.calr_cal_pps_o <= fd_main_calr_cal_pps_sync1;
end if;
end process;
end process;
-- Produce DDMTD calibration pattern (type 2 calibration)
regs_o.calr_cal_dmtd_o <= fd_main_calr_cal_dmtd_int;
regs_o.calr_cal_dmtd_o <= fd_main_calr_cal_dmtd_int;
-- Calibration pulse output select/mask
-- asynchronous std_logic_vector register : Calibration pulse output select/mask (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_calr_psel_swb_s0 <= '0';
fd_main_calr_psel_swb_s1 <= '0';
......@@ -1719,7 +1814,7 @@ begin
regs_o.calr_psel_o <= fd_main_calr_psel_int;
end if;
end if;
end process;
end process;
-- DMTD Tag
......@@ -1728,8 +1823,8 @@ begin
-- DMTD Tag Ready
-- ADSFR Value
-- asynchronous std_logic_vector register : ADSFR Value (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_adsfr_swb_s0 <= '0';
fd_main_adsfr_swb_s1 <= '0';
......@@ -1743,13 +1838,13 @@ begin
regs_o.adsfr_o <= fd_main_adsfr_int;
end if;
end if;
end process;
end process;
-- Coarse threshold
-- asynchronous std_logic_vector register : Coarse threshold (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_atmcr_c_thr_swb_s0 <= '0';
fd_main_atmcr_c_thr_swb_s1 <= '0';
......@@ -1763,13 +1858,13 @@ begin
regs_o.atmcr_c_thr_o <= fd_main_atmcr_c_thr_int;
end if;
end if;
end process;
end process;
-- Fine threshold
-- asynchronous std_logic_vector register : Fine threshold (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_atmcr_f_thr_swb_s0 <= '0';
fd_main_atmcr_f_thr_swb_s1 <= '0';
......@@ -1783,13 +1878,13 @@ begin
regs_o.atmcr_f_thr_o <= fd_main_atmcr_f_thr_int;
end if;
end if;
end process;
end process;
-- Start Offset
-- asynchronous std_logic_vector register : Start Offset (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_asor_offset_swb_s0 <= '0';
fd_main_asor_offset_swb_s1 <= '0';
......@@ -1803,13 +1898,13 @@ begin
regs_o.asor_offset_o <= fd_main_asor_offset_int;
end if;
end if;
end process;
end process;
-- Number of raw events.
-- asynchronous std_logic_vector register : Number of raw events. (type RO/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_iecraw_lwb_s0 <= '0';
fd_main_iecraw_lwb_s1 <= '0';
......@@ -1823,13 +1918,13 @@ begin
fd_main_iecraw_int <= regs_i.iecraw_i;
end if;
end if;
end process;
end process;
-- Number of tagged events
-- asynchronous std_logic_vector register : Number of tagged events (type RO/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_iectag_lwb_s0 <= '0';
fd_main_iectag_lwb_s1 <= '0';
......@@ -1843,12 +1938,12 @@ begin
fd_main_iectag_int <= regs_i.iectag_i;
end if;
end if;
end process;
end process;
-- Reset stats
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.iepd_rst_stat_o <= '0';
fd_main_iepd_rst_stat_sync0 <= '0';
......@@ -1860,13 +1955,13 @@ begin
fd_main_iepd_rst_stat_sync2 <= fd_main_iepd_rst_stat_sync1;
regs_o.iepd_rst_stat_o <= fd_main_iepd_rst_stat_sync2 and (not fd_main_iepd_rst_stat_sync1);
end if;
end process;
end process;
-- Processing delay
-- asynchronous std_logic_vector register : Processing delay (type RO/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_iepd_pdelay_lwb_s0 <= '0';
fd_main_iepd_pdelay_lwb_s1 <= '0';
......@@ -1880,23 +1975,23 @@ begin
fd_main_iepd_pdelay_int <= regs_i.iepd_pdelay_i;
end if;
end if;
end process;
end process;
-- Data
regs_o.scr_data_o <= wrdata_reg(23 downto 0);
regs_o.scr_data_o <= wrdata_reg(23 downto 0);
-- Select DAC
regs_o.scr_sel_dac_o <= fd_main_scr_sel_dac_int;
regs_o.scr_sel_dac_o <= fd_main_scr_sel_dac_int;
-- Select PLL
regs_o.scr_sel_pll_o <= fd_main_scr_sel_pll_int;
regs_o.scr_sel_pll_o <= fd_main_scr_sel_pll_int;
-- Select GPIO
regs_o.scr_sel_gpio_o <= fd_main_scr_sel_gpio_int;
regs_o.scr_sel_gpio_o <= fd_main_scr_sel_gpio_int;
-- Ready flag
-- Clock Polarity
regs_o.scr_cpol_o <= fd_main_scr_cpol_int;
regs_o.scr_cpol_o <= fd_main_scr_cpol_int;
-- Transfer Start
process (clk_sys_i, rst_n_i)
begin
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_scr_start_dly0 <= '0';
regs_o.scr_start_o <= '0';
......@@ -1904,13 +1999,13 @@ begin
fd_main_scr_start_dly0 <= fd_main_scr_start_int;
regs_o.scr_start_o <= fd_main_scr_start_int and (not fd_main_scr_start_dly0);
end if;
end process;
end process;
-- Frequency
-- asynchronous std_logic_vector register : Frequency (type RO/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_rcrr_lwb_s0 <= '0';
fd_main_rcrr_lwb_s1 <= '0';
......@@ -1924,13 +2019,13 @@ begin
fd_main_rcrr_int <= regs_i.rcrr_i;
end if;
end if;
end process;
end process;
-- Channel mask
-- asynchronous std_logic_vector register : Channel mask (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tsbcr_chan_mask_swb_s0 <= '0';
fd_main_tsbcr_chan_mask_swb_s1 <= '0';
......@@ -1944,14 +2039,14 @@ begin
regs_o.tsbcr_chan_mask_o <= fd_main_tsbcr_chan_mask_int;
end if;
end if;
end process;
end process;
-- Buffer enable
regs_o.tsbcr_enable_o <= fd_main_tsbcr_enable_int;
regs_o.tsbcr_enable_o <= fd_main_tsbcr_enable_int;
-- Buffer purge
process (clk_sys_i, rst_n_i)
begin
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tsbcr_purge_dly0 <= '0';
regs_o.tsbcr_purge_o <= '0';
......@@ -1959,12 +2054,12 @@ begin
fd_main_tsbcr_purge_dly0 <= fd_main_tsbcr_purge_int;
regs_o.tsbcr_purge_o <= fd_main_tsbcr_purge_int and (not fd_main_tsbcr_purge_dly0);
end if;
end process;
end process;
-- Reset timestamp sequence number
process (clk_ref_i, rst_n_i)
begin
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tsbcr_rst_seq_o <= '0';
fd_main_tsbcr_rst_seq_sync0 <= '0';
......@@ -1976,18 +2071,18 @@ begin
fd_main_tsbcr_rst_seq_sync2 <= fd_main_tsbcr_rst_seq_sync1;
regs_o.tsbcr_rst_seq_o <= fd_main_tsbcr_rst_seq_sync2 and (not fd_main_tsbcr_rst_seq_sync1);
end if;
end process;
end process;
-- Buffer full
-- Buffer empty
-- Buffer entries count
-- RAW readout mode enable
regs_o.tsbcr_raw_o <= fd_main_tsbcr_raw_int;
regs_o.tsbcr_raw_o <= fd_main_tsbcr_raw_int;
-- IRQ timeout [milliseconds]
regs_o.tsbir_timeout_o <= fd_main_tsbir_timeout_int;
regs_o.tsbir_timeout_o <= fd_main_tsbir_timeout_int;
-- Interrupt threshold
regs_o.tsbir_threshold_o <= fd_main_tsbir_threshold_int;
regs_o.tsbir_threshold_o <= fd_main_tsbir_threshold_int;
-- Timestamps TAI Seconds (bits 39-32)
-- Timestamps TAI Seconds (bits 31-0)
-- Timestamps cycles count (in 8 ns ticks)
......@@ -1995,18 +2090,18 @@ begin
-- Fine Value (in phase units)
-- Timestamp Sequence ID
-- SCL Line out
regs_o.i2cr_scl_out_o <= fd_main_i2cr_scl_out_int;
regs_o.i2cr_scl_out_o <= fd_main_i2cr_scl_out_int;
-- SDA Line out
regs_o.i2cr_sda_out_o <= fd_main_i2cr_sda_out_int;
regs_o.i2cr_sda_out_o <= fd_main_i2cr_sda_out_int;
-- SCL Line in
-- SDA Line in
-- VCXO Frequency
-- Peltier PWM drive
regs_o.tder2_pelt_drive_o <= fd_main_tder2_pelt_drive_int;
regs_o.tder2_pelt_drive_o <= fd_main_tder2_pelt_drive_int;
-- Debug value
-- Advance buffer readout
process (clk_sys_i, rst_n_i)
begin
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tsbr_advance_adv_dly0 <= '0';
regs_o.tsbr_advance_adv_o <= '0';
......@@ -2014,17 +2109,20 @@ begin
fd_main_tsbr_advance_adv_dly0 <= fd_main_tsbr_advance_adv_int;
regs_o.tsbr_advance_adv_o <= fd_main_tsbr_advance_adv_int and (not fd_main_tsbr_advance_adv_dly0);
end if;
end process;
end process;
-- Slot ID
-- Number of delay line taps.
regs_o.iodelay_adj_n_taps_o <= wrdata_reg(5 downto 0);
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(2 downto 0) <= wrdata_reg(2 downto 0);
eic_ier_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(2 downto 0) <= wrdata_reg(2 downto 0);
eic_isr_clear_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 3,
g_irq00_mode => 3,
......@@ -2076,11 +2174,13 @@ begin
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_ts_buf_notempty_i;
irq_inputs_vector_int(1) <= irq_dmtd_spll_i;
irq_inputs_vector_int(2) <= irq_sync_status_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
irq_inputs_vector_int(0) <= irq_ts_buf_notempty_i;
irq_inputs_vector_int(1) <= irq_dmtd_spll_i;
irq_inputs_vector_int(2) <= irq_sync_status_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/fd_main_wishbone_slave.wb
View file @ ecd0bb00
......@@ -404,6 +404,16 @@ peripheral {
prefix = "ALUTRIG";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "IDELAY CE (pulse)";
description = "Write 1 to pulse the IDELAY CE line for 1 clock tick.";
prefix = "IDELAY_CE";
type = MONOSTABLE;
};
};
reg {
......@@ -1031,6 +1041,36 @@ peripheral {
};
};
reg {
name = "FMC Slot ID Register";
description = "Index of the hardware FMC slot the card is in.";
prefix = "FMC_SLOT_ID";
field {
name = "Slot ID";
prefix = "SLOT_ID";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I/O Delay Adjust Register";
description = "Setup time adjust for certain signals (e.g. TDC_START).";
prefix = "IODELAY_ADJ";
field {
name = "Number of delay line taps.";
prefix = "N_TAPS";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
irq {
name = "Timestamp Buffer interrupt.";
......
hdl/rtl/fine_delay_core.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-08-03
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -65,7 +65,11 @@ entity fine_delay_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_debug_output : boolean := false
g_with_debug_output : boolean := false;
-- index of the slot the core is assigned to, written to
-- FMC_SLOT_ID register
g_fmc_slot_id : integer := 0
);
port (
......@@ -195,7 +199,7 @@ entity fine_delay_core is
owr_i : in std_logic;
---------------------------------------------------------------------------
-- Misc signals: I2C EEPROM, FMC presence
-- Misc signals: I2C EEPROM, FMC presence, I/O calibration
---------------------------------------------------------------------------
i2c_scl_o : out std_logic;
......@@ -207,6 +211,11 @@ entity fine_delay_core is
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
---------------------------------------------------------------------------
-- Wishbone slave (classic/pipelined)
......@@ -358,6 +367,12 @@ architecture rtl of fine_delay_core is
signal dmtd_tag_stb, dbg_tag_in, dbg_tag_out : std_logic;
signal iodelay_ntaps : std_logic_vector(5 downto 0);
signal iodelay_cnt : unsigned(5 downto 0);
signal iodelay_div : unsigned(4 downto 0);
signal iodelay_tick : std_logic;
signal iodelay_cal_done : std_logic;
begin -- rtl
U_WB_Adapter : wb_slave_adapter
......@@ -504,6 +519,8 @@ begin -- rtl
);
U_Acam_TSU : fd_acam_timestamper
generic map (
g_min_pulse_width => 3,
......@@ -780,6 +797,7 @@ begin -- rtl
regs_towb_local.gcr_ddr_locked_i <= pll_status_i;
regs_towb_local.gcr_fmc_present_i <= not fmc_present_n_i;
regs_towb_local.fmc_slot_id_slot_id_i <= std_logic_vector(to_unsigned(g_fmc_slot_id, 4 ));
-- Debug PWM driver for adjusting Peltier temperature. Drivers SPI MOSI line
-- with PWM waveform when none of the SPI peripherals is in use (we have no
......@@ -840,4 +858,61 @@ begin -- rtl
dbg_o <= (others => '0');
end generate gen_without_dbg_out;
p_handle_iodelay: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys = '0' then
idelay_cal_o <= '0';
idelay_inc_o <= '1';
idelay_rst_o <= '0';
idelay_ce_o <= '0';
iodelay_cal_done <= '0';
iodelay_cnt <= (others => '0');
iodelay_div <= (others => '0');
iodelay_tick <= '0';
else
if iodelay_cal_done = '0' then
idelay_cal_o <= '1';
iodelay_cnt <= iodelay_cnt + 1;
if iodelay_cnt = 15 then
iodelay_cnt <= (others => '0');
iodelay_cal_done <= '1';
end if;
else
idelay_cal_o <= '0';
end if;
iodelay_div <= iodelay_div + 1;
if iodelay_div = 0 then
iodelay_tick <= '1';
else
iodelay_tick <= '0';
end if;
if regs_fromwb.iodelay_adj_n_taps_load_o = '1' then
iodelay_cnt <= unsigned(regs_fromwb.iodelay_adj_n_taps_o);
idelay_rst_o <= '1';
iodelay_ntaps <= regs_fromwb.iodelay_adj_n_taps_o;
else
idelay_rst_o <= '0';
end if;
if iodelay_cal_done = '1' and iodelay_tick = '1' and iodelay_cnt /= 0 then
idelay_ce_o <= '1';
iodelay_cnt <= iodelay_cnt - 1;
else
idelay_ce_o <= '0';
end if;
end if;
end if;
end process;
regs_towb_local.iodelay_adj_n_taps_i <= iodelay_ntaps;
end rtl;
hdl/rtl/fine_delay_pkg.vhd
View file @ ecd0bb00
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-24
-- Last update: 2019-10-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -237,32 +237,6 @@ package fine_delay_pkg is
regs_o : out t_fd_channel_out_registers);
end component;
component fd_main_wb_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
regs_i : in t_fd_main_in_registers;
regs_o : out t_fd_main_out_registers);
end component;
component fd_delay_line_arbiter
port (
......@@ -382,7 +356,8 @@ package fine_delay_pkg is
g_simulation : boolean := false;
g_with_direct_timestamp_io : boolean := false;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
g_address_granularity : t_wishbone_address_granularity;
g_fmc_slot_id : integer := 0);
port (
clk_ref_0_i : in std_logic;
clk_ref_180_i : in std_logic;
......@@ -436,6 +411,10 @@ package fine_delay_pkg is
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
......
hdl/syn/spec/Manifest.py
View file @ ecd0bb00
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_fine_delay_top.xise"
syn_tool = "ise"
syn_top = "spec_fine_delay_top"
syn_top = "spec_top"
syn_project = "spec_fine_delay.xise"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
syn_tool = "ise"
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../top/spec" ]
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
modules = { "local" : [ "../../top/spec", "../../platform" ] }
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/spec/spec_fine_delay.xise deleted 100644 → 0
View file @ eca0894f
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
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<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spec_top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
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</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/fd_channel_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings>
<binding xil_pn:location="/spec_top" xil_pn:name="../../top/spec/spec_top.ucf"/>
</bindings>
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
</project>
hdl/syn/svec/Manifest.py
View file @ ecd0bb00
board = "svec"
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
syn_tool = "ise"
files = [ "wrc-release.ram" ]
modules = { "local" : [ "../../top/svec", "../../platform" ] }
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/svec/svec_fine_delay.xise
View file @ ecd0bb00
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/wrc-release.ram deleted 100644 → 0
View file @ eca0894f
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/svec_wr_top/Manifest.py
View file @ ecd0bb00
ctrls = ["bank3_32b_32b"]
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include"
include_dirs = ["../../include/vme64x_bfm",
"../../include/wb", "../../include",
"../../ip_cores/general-cores/modules/wishbone/wb_spi/",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/"]
syn_device = "xc6slx45t"
sim_tool = "modelsim"
sim_top = "main"
top_module = "main"
files = ["main.sv","buildinfo_pkg.vhd"]
files = [ "main.sv" ]
modules = { "local" : [ "../../top/svec" ] }
modules = {"local": ["../../top/svec" ]}
#try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
#except:
# pass
hdl/testbench/svec_wr_top/fdelay_board.svh
View file @ ecd0bb00
......@@ -223,34 +223,34 @@ module fdelay_board (
endmodule // main
`define WIRE_FINE_DELAY_PINS(fmc_index,iface) \
.fd``fmc_index``_tdc_start_p_i (iface.core.tdc_start_p), \
.fd``fmc_index``_tdc_start_n_i (iface.core.tdc_start_n), \
.fd``fmc_index``_clk_ref_p_i (iface.core.clk_ref_p), \
.fd``fmc_index``_clk_ref_n_i (iface.core.clk_ref_n), \
.fd``fmc_index``_trig_a_i (iface.core.trig_a), \
.fd``fmc_index``_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fd``fmc_index``_tdc_d_b (iface.core.tdc_d), \
.fd``fmc_index``_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fd``fmc_index``_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fd``fmc_index``_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fd``fmc_index``_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fd``fmc_index``_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fd``fmc_index``_led_trig_o (iface.core.led_trig), \
.fd``fmc_index``_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fd``fmc_index``_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fd``fmc_index``_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fd``fmc_index``_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fd``fmc_index``_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fd``fmc_index``_spi_sclk_o (iface.core.spi_sclk), \
.fd``fmc_index``_spi_mosi_o (iface.core.spi_mosi), \
.fd``fmc_index``_spi_miso_i (iface.core.spi_miso), \
.fd``fmc_index``_delay_len_o (iface.core.delay_len), \
.fd``fmc_index``_delay_val_o (iface.core.delay_val), \
.fd``fmc_index``_delay_pulse_o (iface.core.delay_pulse), \
.fd``fmc_index``_dmtd_clk_o (iface.core.dmtd_clk), \
.fd``fmc_index``_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fd``fmc_index``_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fd``fmc_index``_pll_status_i (iface.core.pll_status), \
.fd``fmc_index``_ext_rst_n_o (iface.core.ext_rst_n), \
.fd``fmc_index``_onewire_b (iface.core.onewire)
.fmc``fmc_index``_fd_tdc_start_p_i (iface.core.tdc_start_p), \
.fmc``fmc_index``_fd_tdc_start_n_i (iface.core.tdc_start_n), \
.fmc``fmc_index``_fd_clk_ref_p_i (iface.core.clk_ref_p), \
.fmc``fmc_index``_fd_clk_ref_n_i (iface.core.clk_ref_n), \
.fmc``fmc_index``_fd_trig_a_i (iface.core.trig_a), \
.fmc``fmc_index``_fd_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fmc``fmc_index``_fd_tdc_d_b (iface.core.tdc_d), \
.fmc``fmc_index``_fd_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fmc``fmc_index``_fd_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fmc``fmc_index``_fd_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fmc``fmc_index``_fd_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fmc``fmc_index``_fd_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fmc``fmc_index``_fd_led_trig_o (iface.core.led_trig), \
.fmc``fmc_index``_fd_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fmc``fmc_index``_fd_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fmc``fmc_index``_fd_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fmc``fmc_index``_fd_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fmc``fmc_index``_fd_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fmc``fmc_index``_fd_spi_sclk_o (iface.core.spi_sclk), \
.fmc``fmc_index``_fd_spi_mosi_o (iface.core.spi_mosi), \
.fmc``fmc_index``_fd_spi_miso_i (iface.core.spi_miso), \
.fmc``fmc_index``_fd_delay_len_o (iface.core.delay_len), \
.fmc``fmc_index``_fd_delay_val_o (iface.core.delay_val), \
.fmc``fmc_index``_fd_delay_pulse_o (iface.core.delay_pulse), \
.fmc``fmc_index``_fd_dmtd_clk_o (iface.core.dmtd_clk), \
.fmc``fmc_index``_fd_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fmc``fmc_index``_fd_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fmc``fmc_index``_fd_pll_status_i (iface.core.pll_status), \
.fmc``fmc_index``_fd_ext_rst_n_o (iface.core.ext_rst_n), \
.fmc``fmc_index``_fd_onewire_b (iface.core.onewire)
hdl/testbench/svec_wr_top/main.sv
View file @ ecd0bb00
......@@ -105,7 +105,6 @@ module main;
`DECLARE_VME_BUFFERS(VME.slave);
svec_top #(
.g_with_wr_phy(0),
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
......@@ -116,7 +115,7 @@ module main;
.rst_n_i(rst_n),
`WIRE_VME_PINS(8),
`WIRE_VME_PINS_CONVENTION(8),
`WIRE_FINE_DELAY_PINS(0, I_fmc0),
`WIRE_FINE_DELAY_PINS(1, I_fmc1)
);
......@@ -169,6 +168,7 @@ module main;
Timestamp dly, t_start;
CSimDrv_FineDelay drv0;
CSimDrv_FineDelay drv1;
uint64_t d;
#20us;
......@@ -181,15 +181,19 @@ module main;
drv0 = new(acc, 'h80010000);
drv0.init();
drv1 = new(acc, 'h80020000);
drv1.init();
t_start=new;
drv0.set_idelay_taps(5);
/* t_start=new;
drv0.get_time(t_start);
t_start.coarse += 20000;
drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
drv0.config_output(1, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001100, -1);
drv0.config_output(2, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001200, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1); */
$display("Init done");
......
hdl/testbench/svec_wr_top/run.do
View file @ ecd0bb00
vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include
vsim work.main -voptargs=+acc
vsim -t 1ps work.main -novopt -L unisim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
View file @ ecd0bb00
......@@ -40,6 +40,17 @@ class CSimDrv_FineDelay;
endfunction // new
task set_idelay_taps( int taps );
uint64_t tdcsr;
$display("Set Idelay taps : %d\n", taps);
writel(`ADDR_FD_IODELAY_ADJ, taps);
endtask // set_idelay_taps
/* fixme - maybe use real mcp23s17 model instead of this stub? */
task sgpio_write(int value);
uint64_t scr;
......
hdl/testbench/svec_wr_top/wave.do
View file @ ecd0bb00
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_ref_0_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_ref_180_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_sys_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_dmtd_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rst_n_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dcm_reset_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dcm_locked_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/trig_a_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_cal_pulse_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_start_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_fb_in_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_fb_out_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_samp_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/led_trig_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/ext_rst_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/pll_status_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_d_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_d_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_d_oen_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_emptyf_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_alutrigger_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_wr_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_rd_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_start_dis_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_stop_dis_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_dac_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_pll_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_gpio_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_sclk_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_mosi_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_miso_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/delay_len_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/delay_val_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/delay_pulse_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_link_up_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_time_valid_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_cycles_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_utc_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_clk_aux_lock_en_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_clk_aux_locked_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_clk_dmtd_locked_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_dac_value_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_dac_wr_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_en_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_scl_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_scl_oen_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_scl_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_sda_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_sda_oen_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_sda_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/fmc_present_n_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_inc_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_cal_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_ce_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_rst_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_adr_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_dat_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_dat_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_sel_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_cyc_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_stb_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_we_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_ack_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_stall_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_irq_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_seconds_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_cycles_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_frac_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_valid_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_seconds_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_cycles_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_frac_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_valid_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_frac
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_coarse
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_utc
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_dbg
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_valid
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_ts
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_valid
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_valid_masked
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_in_ts
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_source
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_valid
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_d
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_q
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/master_csync_p1
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/master_csync_utc
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/master_csync_coarse
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rst_n_sys
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rst_n_ref
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tsbcr_read_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/fid_read_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/irq_rbuf
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/irq_spll
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/irq_sync
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/channels
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/chx_delay_idle
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cnx_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cnx_in
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/slave_in
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/slave_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_fromwb
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_csync
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_spi
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_tsu
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_rbuf
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_local
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_dmtd
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_en_int
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_int
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_acam
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/gen_cal_pulse
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cal_pulse_mask
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cal_pulse_trigger
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_dac_val_int
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tcr_rd_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_valid_masked
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_pattern
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/csync_pps
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_cal_pulse
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtr_in_rd_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtr_out_rd_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/pwm_count
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/pwm_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_dac_n
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_pll_n
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_gpio_n
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_mosi
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_tag_stb
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_tag_in
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_tag_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_ntaps
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_cnt
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_div
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_tick
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_cal_done
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {53004000000 fs} 0}
configure wave -namecolwidth 183
WaveRestoreCursors {{Cursor 1} {23947022 ps} 0}
configure wave -namecolwidth 486
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -20,4 +156,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {226247193600 fs}
WaveRestoreZoom {23573029 ps} {24321015 ps}
hdl/top/spec/Manifest.py
View file @ ecd0bb00
files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd"]
files = ["spec_fine_delay_top.vhd", "spec_fine_delay_top.ucf"]
fetchto = "../../ip_cores"
......@@ -6,10 +6,11 @@ modules = {
"local" : [
"../../rtl",
"../../platform",
],
"git" : [
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/gn4124-core",
"../../ip_cores/spec",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/spec_fine_delay_top.ucf 0 → 100644
View file @ ecd0bb00
####################################################################################
# FineDelay V3/V4 pins
####################################################################################
NET "fmc0_fd_clk_ref_n_i" LOC = L22 ;
NET "fmc0_fd_clk_ref_n_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_clk_ref_p_i" LOC = L20 ;
NET "fmc0_fd_clk_ref_p_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_delay_len_o[3]" LOC = W14 ;
NET "fmc0_fd_delay_len_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[2]" LOC = Y14 ;
NET "fmc0_fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[1]" LOC = Y18 ;
NET "fmc0_fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[0]" LOC = W17 ;
NET "fmc0_fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_pulse_o[3]" LOC = W13 ;
NET "fmc0_fd_delay_pulse_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[2]" LOC = V13 ;
NET "fmc0_fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[1]" LOC = U15 ;
NET "fmc0_fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[0]" LOC = T15 ;
NET "fmc0_fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[0]" LOC = A20 ;
NET "fmc0_fd_delay_val_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[1]" LOC = B20 ;
NET "fmc0_fd_delay_val_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[2]" LOC = A19 ;
NET "fmc0_fd_delay_val_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[3]" LOC = C19 ;
NET "fmc0_fd_delay_val_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[4]" LOC = W18 ;
NET "fmc0_fd_delay_val_o[4]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[5]" LOC = V17 ;
NET "fmc0_fd_delay_val_o[5]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[6]" LOC = C18 ;
NET "fmc0_fd_delay_val_o[6]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[7]" LOC = D17 ;
NET "fmc0_fd_delay_val_o[7]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[8]" LOC = W15 ;
NET "fmc0_fd_delay_val_o[8]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[9]" LOC = Y16 ;
NET "fmc0_fd_delay_val_o[9]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc0_fd_led_trig_o" LOC = V11 ;
NET "fmc0_fd_led_trig_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_dac_n_o" LOC = AB16 ;
NET "fmc0_fd_spi_cs_dac_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_gpio_n_o" LOC = R11 ;
NET "fmc0_fd_spi_cs_gpio_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_pll_n_o" LOC = AB17 ;
NET "fmc0_fd_spi_cs_pll_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_miso_i" LOC = AB18 ;
NET "fmc0_fd_spi_miso_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_mosi_o" LOC = AA18 ;
NET "fmc0_fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_sclk_o" LOC = Y17 ;
NET "fmc0_fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_clk_o" LOC = T12 ;
NET "fmc0_fd_dmtd_clk_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_fb_out_i" LOC = U12 ;
NET "fmc0_fd_dmtd_fb_out_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_cal_pulse_o" LOC = Y15 ;
NET "fmc0_fd_tdc_cal_pulse_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_pll_status_i" LOC = AB15 ;
NET "fmc0_fd_pll_status_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_alutrigger_o" LOC = W12 ;
NET "fmc0_fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_ext_rst_n_o" LOC = T11 ;
NET "fmc0_fd_ext_rst_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[0]" LOC = AB12 ;
NET "fmc0_fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[1]" LOC = U8 ;
NET "fmc0_fd_tdc_d_b[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[10]" LOC = R9 ;
NET "fmc0_fd_tdc_d_b[10]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[11]" LOC = R8 ;
NET "fmc0_fd_tdc_d_b[11]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[12]" LOC = AA6 ;
NET "fmc0_fd_tdc_d_b[12]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[13]" LOC = AB6 ;
NET "fmc0_fd_tdc_d_b[13]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[14]" LOC = U9 ;
NET "fmc0_fd_tdc_d_b[14]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[15]" LOC = V9 ;
NET "fmc0_fd_tdc_d_b[15]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[16]" LOC = Y7 ;
NET "fmc0_fd_tdc_d_b[16]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[17]" LOC = AB7 ;
NET "fmc0_fd_tdc_d_b[17]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[18]" LOC = AA8 ;
NET "fmc0_fd_tdc_d_b[18]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[19]" LOC = AB8 ;
NET "fmc0_fd_tdc_d_b[19]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[2]" LOC = AA12 ;
NET "fmc0_fd_tdc_d_b[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[20]" LOC = T10 ;
NET "fmc0_fd_tdc_d_b[20]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[21]" LOC = U10 ;
NET "fmc0_fd_tdc_d_b[21]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[22]" LOC = W10 ;
NET "fmc0_fd_tdc_d_b[22]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[23]" LOC = Y10 ;
NET "fmc0_fd_tdc_d_b[23]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[24]" LOC = Y9 ;
NET "fmc0_fd_tdc_d_b[24]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[25]" LOC = AB9 ;
NET "fmc0_fd_tdc_d_b[25]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[26]" LOC = AA4 ;
NET "fmc0_fd_tdc_d_b[26]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[27]" LOC = AB4 ;
NET "fmc0_fd_tdc_d_b[27]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[3]" LOC = T8 ;
NET "fmc0_fd_tdc_d_b[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[4]" LOC = W8 ;
NET "fmc0_fd_tdc_d_b[4]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[5]" LOC = V7 ;
NET "fmc0_fd_tdc_d_b[5]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[6]" LOC = Y6 ;
NET "fmc0_fd_tdc_d_b[6]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[7]" LOC = W6 ;
NET "fmc0_fd_tdc_d_b[7]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[8]" LOC = Y5 ;
NET "fmc0_fd_tdc_d_b[8]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[9]" LOC = AB5 ;
NET "fmc0_fd_tdc_d_b[9]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_emptyf_i" LOC = Y12 ;
NET "fmc0_fd_tdc_emptyf_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_oe_n_o" LOC = AA16 ;
NET "fmc0_fd_tdc_oe_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_rd_n_o" LOC = AB13 ;
NET "fmc0_fd_tdc_rd_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_start_dis_o" LOC = R13 ;
NET "fmc0_fd_tdc_start_dis_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_start_n_i" LOC = F16 ;
NET "fmc0_fd_tdc_start_n_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_tdc_start_p_i" LOC = E16 ;
NET "fmc0_fd_tdc_start_p_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_tdc_stop_dis_o" LOC = T14 ;
NET "fmc0_fd_tdc_stop_dis_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_wr_n_o" LOC = Y13 ;
NET "fmc0_fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_trig_a_i" LOC = Y11 ;
NET "fmc0_fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_fb_in_i" LOC = AB11 ;
NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_onewire_b" LOC = W11 ;
NET "fmc0_fd_onewire_b" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc0_fd_clk_ref_p_i" TNM_NET = fmc0_fd_clk_ref_p_i;
TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fmc0_fd_clk_ref_p_i" 8 ns HIGH 50%;
PIN "cmp0_fd_ddr_pll/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "cmp0_fd_ddr_pll/pll_base_inst/CLKOUT0" TNM_NET="fmc0_dcm_clk_ref_0";
TIMESPEC TS_crossdomain_4 = FROM "clk_sys_62m5" TO "fmc0_dcm_clk_ref_0" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_5 = FROM "fmc0_dcm_clk_ref_0" TO "clk_sys_62m5" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_9 = FROM "clk_ref_125m" TO "fmc0_dcm_clk_ref_0" 4ns DATAPATHONLY;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
hdl/top/spec/spec_fine_delay_top.vhd 0 → 100644
View file @ ecd0bb00
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- Fine Delay Mezzanine (fmc-fine-delay)
-- https://ohwr.org/projects/fmc-delay-1ns-8cha
--------------------------------------------------------------------------------
--
-- unit name: spec_fine_delay_top
--
-- description: Top entity for Fine Delay reference design.
--
-- Top level design of the SPEC-based FMC Fine Delay.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2011-2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity spec_fine_delay_top is
generic (
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
-- to speed up simulations.
g_SIMULATION : integer := 0);
port (
-- Reset button
button1_n_i : in std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_cs_n_o : out std_logic; -- 25MHz VCXO
pll20dac_cs_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier front panel LEDs
led_act_o : out std_logic;
led_link_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
onewire_b : inout std_logic;
-- SFP
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-- SPI
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := 'L';
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
------------------------------------------
-- GN4124 interface
--
-- gn_gpio_b[1] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[0] -> U16 -> GN4124 GPIO8
------------------------------------------
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
gn_p2l_clk_p_i : in std_logic;
gn_p2l_rdy_o : out std_logic;
gn_p2l_dframe_i : in std_logic;
gn_p2l_valid_i : in std_logic;
gn_p2l_data_i : in std_logic_vector(15 downto 0);
gn_p_wr_req_i : in std_logic_vector(1 downto 0);
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0);
gn_rx_error_o : out std_logic;
gn_l2p_clk_n_o : out std_logic;
gn_l2p_clk_p_o : out std_logic;
gn_l2p_dframe_o : out std_logic;
gn_l2p_valid_o : out std_logic;
gn_l2p_edb_o : out std_logic;
gn_l2p_data_o : out std_logic_vector(15 downto 0);
gn_l2p_rdy_i : in std_logic;
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0);
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0);
gn_tx_error_i : in std_logic;
gn_vc_rdy_i : in std_logic_vector(1 downto 0);
gn_gpio_b : inout std_logic_vector(1 downto 0);
------------------------------------------
-- FMC slots
------------------------------------------
fmc0_fd_tdc_start_p_i : in std_logic;
fmc0_fd_tdc_start_n_i : in std_logic;
fmc0_fd_clk_ref_p_i : in std_logic;
fmc0_fd_clk_ref_n_i : in std_logic;
fmc0_fd_trig_a_i : in std_logic;
fmc0_fd_tdc_cal_pulse_o : out std_logic;
fmc0_fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fmc0_fd_tdc_emptyf_i : in std_logic;
fmc0_fd_tdc_alutrigger_o : out std_logic;
fmc0_fd_tdc_wr_n_o : out std_logic;
fmc0_fd_tdc_rd_n_o : out std_logic;
fmc0_fd_tdc_oe_n_o : out std_logic;
fmc0_fd_led_trig_o : out std_logic;
fmc0_fd_tdc_start_dis_o : out std_logic;
fmc0_fd_tdc_stop_dis_o : out std_logic;
fmc0_fd_spi_cs_dac_n_o : out std_logic;
fmc0_fd_spi_cs_pll_n_o : out std_logic;
fmc0_fd_spi_cs_gpio_n_o : out std_logic;
fmc0_fd_spi_sclk_o : out std_logic;
fmc0_fd_spi_mosi_o : out std_logic;
fmc0_fd_spi_miso_i : in std_logic;
fmc0_fd_delay_len_o : out std_logic_vector(3 downto 0);
fmc0_fd_delay_val_o : out std_logic_vector(9 downto 0);
fmc0_fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc0_fd_dmtd_clk_o : out std_logic;
fmc0_fd_dmtd_fb_in_i : in std_logic;
fmc0_fd_dmtd_fb_out_i : in std_logic;
fmc0_fd_pll_status_i : in std_logic;
fmc0_fd_ext_rst_n_o : out std_logic;
fmc0_fd_onewire_b : inout std_logic;
-- FMC slot management
fmc0_prsnt_m2c_n_i : in std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic);
end entity spec_fine_delay_top;
architecture arch of spec_fine_delay_top is
component IBUFDS is
generic (
CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE;
DQS_BIAS : string := "FALSE";
IBUF_DELAY_VALUE : string := "0";
IBUF_LOW_PWR : boolean := TRUE;
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component IBUFDS;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters attached to the primary wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 2;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_GENNUM : integer := 0;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC_DELAY : integer := 1;
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FMC_DELAY => x"0001_0000");
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FMC_DELAY => x"0003_0000"); -- 0x10000 bytes
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Clocks and resets
signal clk_dmtd_125m : std_logic;
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- WRPC TM interface and status
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_time_valid_sync : std_logic;
signal tm_clk_aux_lock_en : std_logic_vector(0 downto 0);
signal tm_clk_aux_locked : std_logic_vector(0 downto 0);
signal tm_dac_value : std_logic_vector( 23 downto 0);
signal tm_dac_wr : std_logic_vector(0 downto 0);
signal wrabbit_en : std_logic;
signal pps_led : std_logic;
-- Wishbone bus from cross-clocking module to FMC0 mezzanine
signal cnx_fmc0_sync_master_out : t_wishbone_master_out;
signal cnx_fmc0_sync_master_in : t_wishbone_master_in;
-- Wishbone buses from FMC ADC cores to DDR controller
signal fmc0_wb_ddr_in : t_wishbone_master_data64_in;
signal fmc0_wb_ddr_out : t_wishbone_master_data64_out;
-- Interrupts and status
signal ddr_wr_fifo_empty : std_logic;
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(4 downto 0);
signal gn4124_access : std_logic;
signal fmc0_fd_tdc_start : std_logic;
signal fmc0_ddr_pll_reset : std_logic;
signal fmc0_ddr_pll_locked: std_logic;
signal fmc0_dcm_clk_ref_0 : std_logic;
signal fmc0_dcm_clk_ref_180 : std_logic;
signal fmc0_fd_pll_status : std_logic;
signal fmc0_tdc_data_out, fmc0_tdc_data_in : std_logic_vector(27 downto 0);
signal fmc0_tdc_data_oe : std_logic;
signal fmc0_fd_owr_en : std_logic;
signal fmc0_fd_owr_in : std_logic;
signal fmc0_fd_tdc_start_predelay : std_logic;
signal fmc0_tdc_start_iodelay_inc : std_logic;
signal fmc0_tdc_start_iodelay_rst : std_logic;
signal fmc0_tdc_start_iodelay_cal : std_logic;
signal fmc0_tdc_start_iodelay_ce : std_logic;
begin -- architecture arch
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0001", -- SPEC + 1xFine Delay
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR => FALSE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 5,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 1,
g_FABRIC_IFACE => plain,
g_SIMULATION => f_int2bool(g_SIMULATION))
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
clk_dmtd_125m_o => clk_dmtd_125m,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
clk_125m_ref_o => clk_ref_125m,
rst_125m_ref_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
pps_p_o => open,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
------------------------------------------------------------------------------
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_crossbar : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
------------------------------------------------------------------------------
-- FMC Fine Delay mezzanine
------------------------------------------------------------------------------
cmp0_tm_time_valid_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
cmp0_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc0_irq,
synced_o => irq_vector(0));
cmp0_fd_tdc_start : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fmc0_fd_tdc_start_predelay, -- Buffer output
I => fmc0_fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fmc0_fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_fd_tdc_start_delay0 : IODELAY2
generic map (
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
DATA_RATE => "SDR"
)
port map (
IDATAIN => fmc0_fd_tdc_start_predelay,
DATAOUT2 => fmc0_fd_tdc_start,
INC => fmc0_tdc_start_iodelay_inc,
CE => fmc0_tdc_start_iodelay_ce,
RST => fmc0_tdc_start_iodelay_rst,
CLK => clk_sys_62m5,
ODATAIN => '0',
CAL => fmc0_tdc_start_iodelay_cal,
T => '1',
IOCLK0 => fmc0_dcm_clk_ref_0,
IOCLK1 => '0'
);
cmp0_fd_ddr_pll : entity work.fd_ddr_pll
port map (
RST => fmc0_ddr_pll_reset,
LOCKED => fmc0_ddr_pll_locked,
CLK_IN1_P => fmc0_fd_clk_ref_p_i,
CLK_IN1_N => fmc0_fd_clk_ref_n_i,
CLK_OUT1 => fmc0_dcm_clk_ref_0,
CLK_OUT2 => fmc0_dcm_clk_ref_180);
fmc0_ddr_pll_reset <= not fmc0_fd_pll_status_i;
fmc0_fd_pll_status <= fmc0_fd_pll_status_i and fmc0_ddr_pll_locked;
cmp0_fmc_fdelay_mezzanine : entity work.fine_delay_core
generic map (
g_with_wr_core => true,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_fmc_slot_id => 0)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
clk_ref_0_i => fmc0_dcm_clk_ref_0,
clk_ref_180_i => fmc0_dcm_clk_ref_180,
clk_dmtd_i => clk_dmtd_125m,
dcm_reset_o => open,
dcm_locked_i => fmc0_ddr_pll_locked,
idelay_cal_o => fmc0_tdc_start_iodelay_cal,
idelay_rst_o => fmc0_tdc_start_iodelay_rst,
idelay_ce_o => fmc0_tdc_start_iodelay_ce,
idelay_inc_o => fmc0_tdc_start_iodelay_inc,
trig_a_i => fmc0_fd_trig_a_i,
tdc_cal_pulse_o => fmc0_fd_tdc_cal_pulse_o,
tdc_start_i => fmc0_fd_tdc_start,
dmtd_fb_in_i => fmc0_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fmc0_fd_dmtd_fb_out_i,
dmtd_samp_o => fmc0_fd_dmtd_clk_o,
led_trig_o => fmc0_fd_led_trig_o,
ext_rst_n_o => fmc0_fd_ext_rst_n_o,
pll_status_i => fmc0_fd_pll_status,
acam_d_o => fmc0_tdc_data_out,
acam_d_i => fmc0_tdc_data_in,
acam_d_oen_o => fmc0_tdc_data_oe,
acam_emptyf_i => fmc0_fd_tdc_emptyf_i,
acam_alutrigger_o => fmc0_fd_tdc_alutrigger_o,
acam_wr_n_o => fmc0_fd_tdc_wr_n_o,
acam_rd_n_o => fmc0_fd_tdc_rd_n_o,
acam_start_dis_o => fmc0_fd_tdc_start_dis_o,
acam_stop_dis_o => fmc0_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fmc0_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fmc0_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fmc0_fd_spi_cs_gpio_n_o,
spi_sclk_o => fmc0_fd_spi_sclk_o,
spi_mosi_o => fmc0_fd_spi_mosi_o,
spi_miso_i => fmc0_fd_spi_miso_i,
delay_len_o => fmc0_fd_delay_len_o,
delay_val_o => fmc0_fd_delay_val_o,
delay_pulse_o => fmc0_fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_tai, -- fixme - it's really TAI, not utc. Fix
-- in the FD core
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
-- WRCore
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr(0),
owr_en_o => fmc0_fd_owr_en,
owr_i => fmc0_fd_owr_in,
-- i2c now from spec template
i2c_scl_oen_o => open,
i2c_scl_i => '1',
i2c_sda_oen_o => open,
i2c_sda_i => '1',
fmc_present_n_i => fmc0_prsnt_m2c_n_i,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).adr,
wb_dat_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_FMC_DELAY).dat,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).sel,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).cyc,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_FMC_DELAY).ack,
wb_stall_o => cnx_slave_out(c_WB_SLAVE_FMC_DELAY).stall,
wb_irq_o => fmc0_irq
);
cnx_slave_out(c_WB_SLAVE_FMC_DELAY).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC_DELAY).err <= '0';
fmc0_fd_tdc_d_b <= fmc0_tdc_data_out when fmc0_tdc_data_oe = '1' else (others => 'Z');
fmc0_fd_tdc_oe_n_o <= '1';
fmc0_tdc_data_in <= fmc0_fd_tdc_d_b;
fmc0_fd_onewire_b <= '0' when fmc0_fd_owr_en = '1' else 'Z';
fmc0_fd_owr_in <= fmc0_fd_onewire_b;
------------------------------------------------------------------------------
-- Carrier LEDs
------------------------------------------------------------------------------
cmp_pci_access_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_GENNUM).cyc,
extended_o => gn4124_access);
aux_leds_o(0) <= not gn4124_access;
aux_leds_o(1) <= '1';
aux_leds_o(2) <= not tm_time_valid;
aux_leds_o(3) <= not pps_led;
end architecture arch;
hdl/top/spec/spec_reset_gen.vhd deleted 100644 → 0
View file @ eca0894f
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/spec_top.ucf deleted 100644 → 0
View file @ eca0894f
#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
#####################################################################
### Gennum ports
#####################################################################
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#####################################################################
### SPEC Generic Stuff
#####################################################################
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#net "led_n_o[0]" loc=c20;
#net "led_n_o[0]" IOSTANDARD=LVCMOS18;
#net "led_n_o[1]" loc=F18;
#net "led_n_o[1]" IOSTANDARD=LVCMOS18;
#net "led_n_o[2]" loc=f20;
#net "led_n_o[2]" IOSTANDARD=LVCMOS18;
#net "led_n_o[3]" loc=G19;
#net "led_n_o[3]" IOSTANDARD=LVCMOS18;
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_PRSNT_M2C_L_i" LOC="AB14";
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = F17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
###########################################################################
## Flash memory SPI interface
###########################################################################
NET "flash_ncs_o" LOC = AA3;
NET "flash_ncs_o" IOSTANDARD = "LVCMOS25";
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
####################################################################################
# FineDelay V3/V4 pins
####################################################################################
NET "fd_clk_ref_n_i" LOC = L22 ;
NET "fd_clk_ref_n_i" IOSTANDARD =LVDS_25;
NET "fd_clk_ref_p_i" LOC = L20 ;
NET "fd_clk_ref_p_i" IOSTANDARD =LVDS_25;
NET "fd_delay_len_o[3]" LOC = W14 ;
NET "fd_delay_len_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[3]" SLEW = SLOW;
NET "fd_delay_len_o[3]" DRIVE = 4;
NET "fd_delay_len_o[2]" LOC = Y14 ;
NET "fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[2]" SLEW = SLOW;
NET "fd_delay_len_o[2]" DRIVE = 4;
NET "fd_delay_len_o[1]" LOC = Y18 ;
NET "fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[1]" SLEW = SLOW;
NET "fd_delay_len_o[1]" DRIVE = 4;
NET "fd_delay_len_o[0]" LOC = W17 ;
NET "fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[0]" SLEW = SLOW;
NET "fd_delay_len_o[0]" DRIVE = 4;
NET "fd_delay_pulse_o[3]" LOC = W13 ;
NET "fd_delay_pulse_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[2]" LOC = V13 ;
NET "fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[1]" LOC = U15 ;
NET "fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[0]" LOC = T15 ;
NET "fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[0]" LOC = A20 ;
NET "fd_delay_val_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[0]" SLEW = SLOW;
NET "fd_delay_val_o[0]" DRIVE = 4;
NET "fd_delay_val_o[1]" LOC = B20 ;
NET "fd_delay_val_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[1]" SLEW = SLOW;
NET "fd_delay_val_o[1]" DRIVE = 4;
NET "fd_delay_val_o[2]" LOC = A19 ;
NET "fd_delay_val_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[2]" SLEW = SLOW;
NET "fd_delay_val_o[2]" DRIVE = 4;
NET "fd_delay_val_o[3]" LOC = C19 ;
NET "fd_delay_val_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[3]" SLEW = SLOW;
NET "fd_delay_val_o[3]" DRIVE = 4;
NET "fd_delay_val_o[4]" LOC = W18 ;
NET "fd_delay_val_o[4]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[4]" SLEW = SLOW;
NET "fd_delay_val_o[4]" DRIVE = 4;
NET "fd_delay_val_o[5]" LOC = V17 ;
NET "fd_delay_val_o[5]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[5]" SLEW = SLOW;
NET "fd_delay_val_o[5]" DRIVE = 4;
NET "fd_delay_val_o[6]" LOC = C18 ;
NET "fd_delay_val_o[6]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[6]" SLEW = SLOW;
NET "fd_delay_val_o[6]" DRIVE = 4;
NET "fd_delay_val_o[7]" LOC = D17 ;
NET "fd_delay_val_o[7]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[7]" SLEW = SLOW;
NET "fd_delay_val_o[7]" DRIVE = 4;
NET "fd_delay_val_o[8]" LOC = W15 ;
NET "fd_delay_val_o[8]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[8]" SLEW = SLOW;
NET "fd_delay_val_o[8]" DRIVE = 4;
NET "fd_delay_val_o[9]" LOC = Y16 ;
NET "fd_delay_val_o[9]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[9]" SLEW = SLOW;
NET "fd_delay_val_o[9]" DRIVE = 4;
NET "fd_led_trig_o" LOC = V11 ;
NET "fd_led_trig_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_dac_n_o" LOC = AB16 ;
NET "fd_spi_cs_dac_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_gpio_n_o" LOC = R11 ;
NET "fd_spi_cs_gpio_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_pll_n_o" LOC = AB17 ;
NET "fd_spi_cs_pll_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_miso_i" LOC = AB18 ;
NET "fd_spi_miso_i" IOSTANDARD =LVCMOS25;
NET "fd_spi_mosi_o" LOC = AA18 ;
NET "fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_sclk_o" LOC = Y17 ;
NET "fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_clk_o" LOC = T12 ;
NET "fd_dmtd_clk_o" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_fb_out_i" LOC = U12 ;
NET "fd_dmtd_fb_out_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_cal_pulse_o" LOC = Y15 ;
NET "fd_tdc_cal_pulse_o" IOSTANDARD =LVCMOS25;
NET "fd_pll_status_i" LOC = AB15 ;
NET "fd_pll_status_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_alutrigger_o" LOC = W12 ;
NET "fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fd_ext_rst_n_o" LOC = T11 ;
NET "fd_ext_rst_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[0]" LOC = AB12 ;
NET "fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[1]" LOC = U8 ;
NET "fd_tdc_d_b[1]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[10]" LOC = R9 ;
NET "fd_tdc_d_b[10]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[11]" LOC = R8 ;
NET "fd_tdc_d_b[11]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[12]" LOC = AA6 ;
NET "fd_tdc_d_b[12]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[13]" LOC = AB6 ;
NET "fd_tdc_d_b[13]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[14]" LOC = U9 ;
NET "fd_tdc_d_b[14]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[15]" LOC = V9 ;
NET "fd_tdc_d_b[15]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[16]" LOC = Y7 ;
NET "fd_tdc_d_b[16]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[17]" LOC = AB7 ;
NET "fd_tdc_d_b[17]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[18]" LOC = AA8 ;
NET "fd_tdc_d_b[18]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[19]" LOC = AB8 ;
NET "fd_tdc_d_b[19]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[2]" LOC = AA12 ;
NET "fd_tdc_d_b[2]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[20]" LOC = T10 ;
NET "fd_tdc_d_b[20]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[21]" LOC = U10 ;
NET "fd_tdc_d_b[21]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[22]" LOC = W10 ;
NET "fd_tdc_d_b[22]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[23]" LOC = Y10 ;
NET "fd_tdc_d_b[23]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[24]" LOC = Y9 ;
NET "fd_tdc_d_b[24]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[25]" LOC = AB9 ;
NET "fd_tdc_d_b[25]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[26]" LOC = AA4 ;
NET "fd_tdc_d_b[26]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[27]" LOC = AB4 ;
NET "fd_tdc_d_b[27]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[3]" LOC = T8 ;
NET "fd_tdc_d_b[3]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[4]" LOC = W8 ;
NET "fd_tdc_d_b[4]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[5]" LOC = V7 ;
NET "fd_tdc_d_b[5]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[6]" LOC = Y6 ;
NET "fd_tdc_d_b[6]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[7]" LOC = W6 ;
NET "fd_tdc_d_b[7]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[8]" LOC = Y5 ;
NET "fd_tdc_d_b[8]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[9]" LOC = AB5 ;
NET "fd_tdc_d_b[9]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_emptyf_i" LOC = Y12 ;
NET "fd_tdc_emptyf_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_oe_n_o" LOC = AA16 ;
NET "fd_tdc_oe_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_rd_n_o" LOC = AB13 ;
NET "fd_tdc_rd_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_start_dis_o" LOC = R13 ;
NET "fd_tdc_start_dis_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_start_n_i" LOC = F16 ;
NET "fd_tdc_start_n_i" IOSTANDARD =LVDS_25;
NET "fd_tdc_start_p_i" LOC = E16 ;
NET "fd_tdc_start_p_i" IOSTANDARD =LVDS_25;
NET "fd_tdc_stop_dis_o" LOC = T14 ;
NET "fd_tdc_stop_dis_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_wr_n_o" LOC = Y13 ;
NET "fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fd_trig_a_i" LOC = Y11 ;
NET "fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_fb_in_i" LOC = AB11 ;
NET "fd_dmtd_fb_in_i" IOSTANDARD =LVCMOS25;
NET "fd_onewire_b" LOC = W11 ;
NET "fd_onewire_b" IOSTANDARD =LVCMOS25;
####################################################################################
# Misc
####################################################################################
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fd_clk_ref_n_i" TNM_NET = fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fd_clk_ref_p_i" TNM_NET = fd_clk_ref_p_i;
TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fd_clk_ref_p_i" 8 ns HIGH 50%;
NET "clk_sys" TNM_NET = clk_sys;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
PIN "U_DDR_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2014/08/01
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
# TIMESPEC TS_crossdomain_1 = FROM "clk_sys" TO "clk_125m_pllref_BUFG" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_4 = FROM "clk_sys" TO "dcm_clk_ref_0" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_5 = FROM "dcm_clk_ref_0" TO "clk_sys" 4ns DATAPATHONLY;
# TIMESPEC TS_crossdomain_7 = FROM "clk_125m_pllref_BUFG" TO "clk_sys" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_9 = FROM "clk_125m_pllref_BUFG" TO "dcm_clk_ref_0" 4ns DATAPATHONLY;
NET "*/gc_sync_register_in[*]" MAXDELAY=4ns;
hdl/top/spec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ eca0894f
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-fine-delay ",
syn_commit_id => "7dd0a8c348dee0a3a660143c80487a8a",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20141209",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
hdl/top/svec/Manifest.py
View file @ ecd0bb00
files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf", "bicolor_led_ctrl.vhd", "bicolor_led_ctrl_pkg.vhd" ]
files = ["svec_fine_delay_top.vhd", "svec_fine_delay_top.ucf"]
fetchto = "../../ip_cores"
......@@ -6,10 +6,11 @@ modules = {
"local" : [
"../../rtl",
"../../platform",
],
"git" : [
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/svec",
"../../ip_cores/vme64x-core",
"../../ip_cores/svec",
"../../ip_cores/ddr3-sp6-core",
]
}
hdl/top/svec/svec_fine_delay_top.ucf 0 → 100644
View file @ ecd0bb00
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 0
NET "fmc0_fd_clk_ref_p_i" LOC = "E16";
NET "fmc0_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_clk_ref_n_i" LOC = "D16";
NET "fmc0_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_p_i" LOC = "H15";
NET "fmc0_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_n_i" LOC = "G15";
NET "fmc0_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_delay_len_o[3]" LOC = "G10";
NET "fmc0_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[2]" LOC = "F10";
NET "fmc0_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[1]" LOC = "E9";
NET "fmc0_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[0]" LOC = "F9";
NET "fmc0_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_pulse_o[3]" LOC = "F12";
NET "fmc0_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[1]" LOC = "E11";
NET "fmc0_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[2]" LOC = "G12";
NET "fmc0_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[0]" LOC = "F11";
NET "fmc0_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" LOC = "J12";
NET "fmc0_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[1]" LOC = "H11";
NET "fmc0_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[7]" LOC = "L11";
NET "fmc0_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[5]" LOC = "J13";
NET "fmc0_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[9]" LOC = "L12";
NET "fmc0_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc0_fd_spi_mosi_o" LOC = "M13";
NET "fmc0_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_sclk_o" LOC = "L14";
NET "fmc0_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_oe_n_o" LOC = "M15";
NET "fmc0_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_start_dis_o" LOC = "F13";
NET "fmc0_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_gpio_n_o" LOC = "F15";
NET "fmc0_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_cal_pulse_o" LOC = "G14";
NET "fmc0_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_clk_o" LOC = "J14";
NET "fmc0_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_wr_n_o" LOC = "B15";
NET "fmc0_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_alutrigger_o" LOC = "F19";
NET "fmc0_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_led_trig_o" LOC = "H16";
NET "fmc0_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[26]" LOC = "F17";
NET "fmc0_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[24]" LOC = "G18";
NET "fmc0_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[20]" LOC = "F21";
NET "fmc0_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[22]" LOC = "G20";
NET "fmc0_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[18]" LOC = "L21";
NET "fmc0_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[16]" LOC = "M20";
NET "fmc0_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[10]" LOC = "F23";
NET "fmc0_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[14]" LOC = "G22";
NET "fmc0_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[8]" LOC = "B25";
NET "fmc0_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[12]" LOC = "M19";
NET "fmc0_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[3]" LOC = "D24";
NET "fmc0_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[5]" LOC = "E25";
NET "fmc0_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[7]" LOC = "J22";
NET "fmc0_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[2]" LOC = "H21";
NET "fmc0_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_trig_a_i" LOC = "C16";
NET "fmc0_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" LOC = "H12";
NET "fmc0_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[0]" LOC = "G11";
NET "fmc0_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[6]" LOC = "K11";
NET "fmc0_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[4]" LOC = "H13";
NET "fmc0_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[8]" LOC = "K12";
NET "fmc0_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc0_fd_spi_miso_i" LOC = "L13";
NET "fmc0_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_pll_n_o" LOC = "K14";
NET "fmc0_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_dac_n_o" LOC = "K15";
NET "fmc0_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_stop_dis_o" LOC = "E13";
NET "fmc0_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_ext_rst_n_o" LOC = "E15";
NET "fmc0_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_pll_status_i" LOC = "F14";
NET "fmc0_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_out_i" LOC = "H14";
NET "fmc0_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_rd_n_o" LOC = "A15";
NET "fmc0_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_emptyf_i" LOC = "E19";
NET "fmc0_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_onewire_b" LOC = "G16";
NET "fmc0_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[27]" LOC = "E17";
NET "fmc0_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[25]" LOC = "F18";
NET "fmc0_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[21]" LOC = "E21";
NET "fmc0_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[23]" LOC = "F20";
NET "fmc0_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[19]" LOC = "K21";
NET "fmc0_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[17]" LOC = "L20";
NET "fmc0_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[11]" LOC = "E23";
NET "fmc0_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[15]" LOC = "F22";
NET "fmc0_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[9]" LOC = "A25";
NET "fmc0_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[13]" LOC = "L19";
NET "fmc0_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[1]" LOC = "C24";
NET "fmc0_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[4]" LOC = "D25";
NET "fmc0_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[6]" LOC = "H22";
NET "fmc0_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[0]" LOC = "G21";
NET "fmc0_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_in_i" LOC = "A16";
NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fmc1_fd_clk_ref_p_i" LOC = "AH16";
NET "fmc1_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_clk_ref_n_i" LOC = "AK16";
NET "fmc1_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_p_i" LOC = "AF16";
NET "fmc1_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_n_i" LOC = "AG16";
NET "fmc1_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_delay_len_o[3]" LOC = "AB21";
NET "fmc1_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[2]" LOC = "AC21";
NET "fmc1_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[1]" LOC = "AD24";
NET "fmc1_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[0]" LOC = "AC24";
NET "fmc1_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_pulse_o[3]" LOC = "AE22";
NET "fmc1_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[1]" LOC = "AD17";
NET "fmc1_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[2]" LOC = "AD22";
NET "fmc1_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[0]" LOC = "AB17";
NET "fmc1_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" LOC = "AA19";
NET "fmc1_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[1]" LOC = "W19";
NET "fmc1_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[7]" LOC = "Y21";
NET "fmc1_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[5]" LOC = "W20";
NET "fmc1_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[9]" LOC = "AA22";
NET "fmc1_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc1_fd_spi_mosi_o" LOC = "AB20";
NET "fmc1_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_sclk_o" LOC = "AC19";
NET "fmc1_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_oe_n_o" LOC = "AF25";
NET "fmc1_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_start_dis_o" LOC = "AE24";
NET "fmc1_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_gpio_n_o" LOC = "AE19";
NET "fmc1_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_cal_pulse_o" LOC = "AE23";
NET "fmc1_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_clk_o" LOC = "AE21";
NET "fmc1_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_wr_n_o" LOC = "AC16";
NET "fmc1_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_alutrigger_o" LOC = "AB14";
NET "fmc1_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_led_trig_o" LOC = "Y17";
NET "fmc1_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[26]" LOC = "Y15";
NET "fmc1_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[24]" LOC = "AC15";
NET "fmc1_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[20]" LOC = "AE15";
NET "fmc1_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[22]" LOC = "Y16";
NET "fmc1_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[18]" LOC = "Y14";
NET "fmc1_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[16]" LOC = "W14";
NET "fmc1_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[10]" LOC = "AB12";
NET "fmc1_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[14]" LOC = "AD12";
NET "fmc1_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[8]" LOC = "AD10";
NET "fmc1_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[12]" LOC = "AE11";
NET "fmc1_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[3]" LOC = "AJ15";
NET "fmc1_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[5]" LOC = "AE13";
NET "fmc1_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[7]" LOC = "AC11";
NET "fmc1_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[2]" LOC = "AG8";
NET "fmc1_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_trig_a_i" LOC = "AJ17";
NET "fmc1_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" LOC = "AB19";
NET "fmc1_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[0]" LOC = "Y19";
NET "fmc1_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[6]" LOC = "AA21";
NET "fmc1_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[4]" LOC = "Y20";
NET "fmc1_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[8]" LOC = "AC22";
NET "fmc1_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc1_fd_spi_miso_i" LOC = "AC20";
NET "fmc1_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_pll_n_o" LOC = "AD19";
NET "fmc1_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_dac_n_o" LOC = "AG25";
NET "fmc1_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_stop_dis_o" LOC = "AF24";
NET "fmc1_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_ext_rst_n_o" LOC = "AF19";
NET "fmc1_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_pll_status_i" LOC = "AF23";
NET "fmc1_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_out_i" LOC = "AF21";
NET "fmc1_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_rd_n_o" LOC = "AD16";
NET "fmc1_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_emptyf_i" LOC = "AC14";
NET "fmc1_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_onewire_b" LOC = "AA17";
NET "fmc1_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[27]" LOC = "AA15";
NET "fmc1_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[25]" LOC = "AD15";
NET "fmc1_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[21]" LOC = "AF15";
NET "fmc1_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[23]" LOC = "AB16";
NET "fmc1_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[19]" LOC = "AA14";
NET "fmc1_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[17]" LOC = "Y13";
NET "fmc1_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[11]" LOC = "AC12";
NET "fmc1_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[15]" LOC = "AE12";
NET "fmc1_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[9]" LOC = "AE10";
NET "fmc1_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[13]" LOC = "AF11";
NET "fmc1_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[1]" LOC = "AK15";
NET "fmc1_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[4]" LOC = "AF13";
NET "fmc1_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[6]" LOC = "AD11";
NET "fmc1_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[0]" LOC = "AH8";
NET "fmc1_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_in_i" LOC = "AK17";
NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC template UCF files
# Declaration of domains
NET "dcm0_clk_ref_0" TNM_NET = fd0_clk;
NET "dcm1_clk_ref_0" TNM_NET = fd1_clk;
# Exceptions for crossings via gc_sync_ffs
TIMEGRP "fd0_sync_ffs" = "sync_ffs" EXCEPT "fd0_clk";
TIMEGRP "fd1_sync_ffs" = "sync_ffs" EXCEPT "fd1_clk";
TIMESPEC TS_fd0_sync_ffs = FROM fd0_clk TO "fd0_sync_ffs" TIG;
TIMESPEC TS_fd1_sync_ffs = FROM fd1_clk TO "fd1_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
hdl/top/svec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ eca0894f
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2014-03-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "svec-fine-delay ",
syn_commit_id => "a3f676c402a931c43ed2654bddd7dbaf",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20141209",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
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