hdl/ffpg/rtl · a4f3e56ca20fc95bdb34c2b9af57c543d0f30305 · Projects / FMC DEL 1ns 2cha · Open Hardware Repository

History Find file

added trigger latency specification (not implemented yet); renamed some WB… · a4f3e56c
Jan Pospisil authored Jul 04, 2016
```
added trigger latency specification (not implemented yet); renamed some WB registers to better reflect it purpose
```
a4f3e56c

Name	Last commit	Last update
..
Counter.vhd		Loading commit data...
CounterO.vhd		Loading commit data...
DacsController.vhd		Loading commit data...
DelayController.vhd		Loading commit data...
DelayedPulseGenerator.vhd		Loading commit data...
FfpgCore.vhd		Loading commit data...
FfpgPkg.vhd		Loading commit data...
Manifest.py		Loading commit data...
ShiftRegister.vhd		Loading commit data...
WbSlaveWrapper.vhd		Loading commit data...
pulseGenerator.vhd		Loading commit data...
pulseGeneratorTime.vhd		Loading commit data...