Commit 3a392fca authored by Jan Pospisil's avatar Jan Pospisil

updated block diagram and timing example

added timing closure analysis diagram
parent d0df5c6a
No preview for this file type
// http://wavedrom.com/editor.html
{
signal: [
{name: 'clk', wave: 'PPPP', node: '....', period: 4.99, phase: 0},
{name: 'FPGA-clk-min', wave: 'PPPP', node: 'a...', period: 4.99, phase: -1.478},
{name: 'FPGA-clk-max', wave: 'PPPP', node: 'c...', period: 4.99, phase: -2.514},
{name: 'D-clk-min', wave: 'PPPP', node: '....', period: 4.99, phase: -0.474},
{name: 'D-clk-max', wave: 'PPPP', node: '....', period: 4.99, phase: -0.919},
{name: 'D-data-min', wave: '====', node: '....', period: 4.99, phase: -0.474+0.1},
{name: 'D-data-max', wave: '====', node: '....', period: 4.99, phase: -0.919-0.05},
{name: 'FPGA-data-min', wave: '====', node: '.d..', period: 4.99, phase: -0.474+0.1+0.634},
{name: 'FPGA-data-max', wave: '====', node: '.b..', period: 4.99, phase: -0.919-0.05-0.374},
],
edge: [
'a-~>b ' + Math.round(100*(4.99-1.478+0.919+0.050-0.374), 0.1)/100 + ' ns',
'c~->d ' + Math.round(100*(4.99-2.514+0.474-0.1-0.634), 0.1)/100 + ' ns'
]
}
\ No newline at end of file
// http://wavedrom.com/editor.html
{ {
signal: [ signal: [
{name: 'CLK IN (400 MHz)', wave: 'PPPPPPPPPPPPPPPPPPPPPPPPPPPPPP', node: '.ab', period: 1, phase: 0}, {name: 'CLK IN (400 MHz)', wave: 'PPPPPPPPPPPPPPPPPPPPPPPPPPPPPP', node: '.AB', period: 1, phase: 0},
{node: '.ef.g.h...i'}, {node: '.EF.G.H...I'},
{name: 'CLK (200 MHz)', wave: 'PPPPPPPPPPPPPPP', node: '..cd', period: 2, phase: 0}, {name: 'CLK (200 MHz)', wave: 'PPPPPPPPPPPPPPP', node: '..CD', period: 2, phase: 0},
{name: 'TRIG IN', wave: '0.......1...0..................', node: '...j....k', period: 1, phase: 1}, {name: 'TRIG IN', wave: '0.......1...0..................', node: '...J....K', period: 1, phase: 1},
{name: 'Memory counter', wave: '333333333333333', node: '.l', period: 2, phase: 0, data: ['OVRFLW-1', 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]}, {name: 'Memory counter', wave: '333333333333333', node: '.l', period: 2, phase: 0, data: ['OVRFLW-1', 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]},
{name: 'SET Memory', wave: '222222242224222', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0]}, //{name: 'SET Memory', wave: '222222422242222', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0]},
{name: 'RESET Memory', wave: '222222242222422', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0]}, //{name: 'RESET Memory', wave: '222222422224222', node: '', period: 2, phase: 0, data: [0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0]},
{name: 'SET pulse', wave: '0......10..10..', node: '...........m', period: 2, phase: 0}, {name: 'SET pulse', wave: '0......10..10..', node: '...........M', period: 2, phase: 0},
{name: 'RESET pulse', wave: '0......10...10.', node: '............q', period: 2, phase: 0}, {name: 'RESET pulse', wave: '0......10...10.', node: '............Q', period: 2, phase: 0},
{name: 'SET pulse (delayed)', wave: '0.......10..10..', node: '............n', period: 2, phase: 2-0.5}, {name: 'SET pulse (delayed)', wave: '0.......10..10..', node: '........X...N', period: 2, phase: 2-0.5},
{name: 'RESET pulse (delayed)', wave: '0.......10...10.', node: '.............r', period: 2, phase: 2-1}, {name: 'RESET pulse (delayed)', wave: '0.......10...10.', node: '........Y....R', period: 2, phase: 2-1},
{node: '.......................................s....opt.v.w....u', period: 0.5}, {node: '.......................................S....OPT.V.W...U', period: 0.5},
{name: 'OUT (pulse)', wave: '0............................10..............1....0.........', node: '....', period: 0.5, phase: 0}, {name: 'OUT (pulse)', wave: '0............................10..............1....0.........', node: '.............................ZL', period: 0.5, phase: 0},
], ],
// free nodes: xyz
edge: [ edge: [
'a-e', 'b-f', 'e<->f T', 'A-E', 'B-F', 'E<->F T',
'g-c', 'h-d', 'g<->h', 'h-i T*(CLOCK_RATIO_M1+1)', 'G-C', 'H-D', 'G<->H', 'H~I T × (CLOCK_RATIO_M1 + 1)',
'j-l', 'j<->k TRIGGER_LATENCY', 'J-l', 'J<->K TRIGGER_LATENCY',
'm-o', 'n-p', 's->o DELAY_SET', 'o-p', 't->p', 'M-O', 'N-P', 'S->O DELAY_SET', 'O-P', 'T->P',
'q-v', 'r-w', 'v<->w', 'u-w DELAY_RESET' 'Q-V', 'R-W', 'V<->W', 'U-W DELAY_RESET',
'X->Z', 'Y->L'
] ]
} }
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