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.ohwr.yaml
View file @ cf959c95
......@@ -13,4 +13,4 @@ images:
- 'https://ohwr.org/project/fmc-del-1ns-2cha/uploads/eb40d6640ea19e1be05553e3ea29ce0c/EDA-03339-diagram_thumb.png'
documentation: 'https://ohwr.org/project/fmc-del-1ns-2cha/wikis'
issues: 'https://ohwr.org/project/fmc-del-1ns-2cha/issues'
forum: 'https://forums.ohwr.org/c/fmc-del-1ns-2cha'
doc/manual/ffpg_core.htm
View file @ cf959c95
This diff is collapsed.
hdl/ffpg/cheby/Makefile
View file @ cf959c95
......@@ -6,14 +6,21 @@ CHEBY=cheby
RTL=../rtl
DOC=../../../doc/manual
SIM=../sim/testbench
DRV=../../../sw/driver
.PHONY: all
all: $(RTL)/ffpg_core_regs.vhd \
$(DOC)/ffpg_core.htm \
$(SIM)/ffpg_csr.svh
$(SIM)/ffpg_csr.svh \
$(DRV)/fmc_fpg_vme_hw_desc.csv \
$(DRV)/fmc_fpg_pci_hw_desc.csv
$(RTL)/ffpg_core_regs.vhd: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
$(DOC)/ffpg_core.htm: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
DEPS=ffpg_csr.cheby ffpg_ch.cheby onewire_master.cheby spi_master.cheby
$(RTL)/ffpg_core_regs.vhd: $(DEPS)
$(DOC)/ffpg_core.htm: $(DEPS)
$(DRV)/fmc_fpg_vme_hw_desc.csv: $(DEPS)
$(DRV)/fmc_fpg_pci_hw_desc.csv: $(DEPS)
$(RTL)/%_regs.vhd: %.cheby
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $<
......@@ -23,3 +30,6 @@ $(DOC)/%.htm: %.cheby
$(SIM)/%.svh: %.cheby
$(CHEBY) --consts-style=verilog --gen-consts $@ --header=commit --input $<
$(DRV)/%_hw_desc.csv: %.cheby
$(CHEBY) --gen-edge3 $@ --input $<
\ No newline at end of file
hdl/ffpg/cheby/ffpg_ch.cheby 0 → 100644
View file @ cf959c95
memory-map:
name: ffpg_ch
description: FFPG channel
bus: wb-32-be
children:
- reg:
name: status
description: Status register
width: 32
access: ro
children:
- field:
name: oe
description: Pulse generator channel output enabled
comment: |-
Pulse generator channel output enabled
0: output disabled
1: output enabled
range: 0
x-driver-edge:
generate: false
- field:
name: running
description: Pulse generator channel running
comment: |-
Pulse generator channel running
0: channel is not running
1: channel is running, pulses are generated
range: 1
x-driver-edge:
generate: false
- field:
name: stream_state
description: Current stream state
range: 2
x-driver-edge:
generate: false
- reg:
name: control
description: Control register
width: 32
access: rw
children:
- field:
name: oe
description: Output enable
range: 0
x-driver-edge:
generate: false
- field:
name: stop_immediate
description: Make stop triggers immediate, not turn synchronized.
range: 1
x-driver-edge:
generate: false
- reg:
name: sw_trigger
description: Software triggers
comment: |-
Various SW triggers, write 1 to bit position to trigger.
width: 32
access: rw
x-hdl:
type: autoclear
children:
- field:
name: start
description: Start channel at next turn.
range: 0
x-driver-edge:
generate: false
- field:
name: stop
description: Stop channel at next turn or immediate.
range: 1
x-driver-edge:
generate: false
- reg:
name: delay_set
description: Set delay
comment: |-
10 bit fine delay for pulse generation - delay of the SET pulse, i.e. pulse delay
width: 32
access: rw
address: 0x10
x-hdl:
write-strobe: true
children:
- field:
name: value
description: Set delay
range: 9-0
x-driver-edge:
generate: false
- reg:
name: delay_res
description: Reset delay
comment: |-
10 bit fine delays for pulse generation - delay of the RES pulse, i.e. pulse width
width: 32
access: rw
address: 0x14
x-hdl:
write-strobe: true
children:
- field:
name: value
description: Reset delay
range: 9-0
x-driver-edge:
generate: false
- reg:
name: iterations
description: Number of stream iterations. 0 means infinite or until stop trigger.
width: 32
access: rw
- reg:
name: turns
description: Number of stream turns per each stream iteration. 0 is aliased to 1.
width: 32
access: rw
- reg:
name: pause
description: Transmit idle value for N turns between two stream iterations.
width: 32
access: rw
- reg:
name: force
description: Force set/reset and current state values. Intended for initialization.
width: 32
access: rw
x-hdl:
write-strobe: true
children:
- field:
name: set_val
description: Sequence of 5 bits to transmit on Set control
range: 4-0
x-driver-edge:
generate: false
- field:
name: res_val
description: Sequence of 5 bits to transmit on Reset control
range: 9-5
x-driver-edge:
generate: false
- field:
name: state
description: Pulse generator state after Set/Rst sequence
range: 10
x-driver-edge:
generate: false
hdl/ffpg/cheby/ffpg_csr.cheby
View file @ cf959c95
This diff is collapsed.
hdl/ffpg/cheby/fmc_fpg_pci.cheby 0 → 100644
View file @ cf959c95
memory-map:
name: FMC-FPG
description: "FMC Fast Pulse Generator"
bus: wb-32-be
x-driver-edge:
board-type: fmc_fpg
driver-version: 3.0.0-pci
schema-version: 3.1
bus-type: PCI
endianness: little
device-info:
vendor-id: 0x10DC
device-id: 0x01A3
subvendor-id: 0x1A39
subdevice-id: 0x0004
children:
- address-space:
name: registers
size: 0x20000
children:
- submap:
name: onewire_master
description: OneWire master
address: 0x1000
filename: onewire_master.cheby
- submap:
name: spi_master
description: WB SPI master
address: 0x2000
filename: spi_master.cheby
- submap:
name: csr
description: Control/status registers
address: 0x10000
filename: ffpg_csr.cheby
hdl/ffpg/cheby/fmc_fpg_vme.cheby 0 → 100644
View file @ cf959c95
memory-map:
name: FMC-FPG
description: "FMC Fast Pulse Generator"
bus: wb-32-be
x-driver-edge:
board-type: fmc_fpg
driver-version: 3.0.0-vme
schema-version: 3.1
bus-type: VME
endianness: big
children:
- address-space:
name: registers
size: 0x20000
x-driver-edge:
number: 0
addr-mode: A24
data-width: 32
dma-mode: BLT|MBLT
children:
- submap:
name: onewire_master
description: OneWire master
address: 0x1000
filename: onewire_master.cheby
- submap:
name: spi_master
description: WB SPI master
address: 0x2000
filename: spi_master.cheby
- submap:
name: csr
description: Control/status registers
address: 0x10000
filename: ffpg_csr.cheby
hdl/ffpg/rtl/FfpgCore.vhd
View file @ cf959c95
......@@ -53,7 +53,8 @@ use work.wishbone_pkg.all;
entity FfpgCore is
generic (
g_ClkFrequency: positive; -- input clock frequency in Hz
g_Version: std_logic_vector(31 downto 0)
g_Version: std_logic_vector(31 downto 0);
g_Ident: std_logic_vector(63 downto 0)
);
port (
-- Wishbone connection
......@@ -214,7 +215,7 @@ begin
Reset_nr <= not Reset_r;
-- registers reset synchronously, so combining with main async reset
ResetToRf_r <= WbRegsOutput.csr_control_RfLogicRst or Reset_r;
ResetToRf_r <= WbRegsOutput.csr_control_rf_logic_rst or Reset_r;
cResetSyncerRf: entity work.ResetSyncer(syn)
generic map (
......@@ -240,11 +241,11 @@ begin
);
ResetToRfIf_ra <= Reset_r or WbRegsOutput.csr_control_SerdesIfRst;
ResetToRfIf_ra <= Reset_r or WbRegsOutput.csr_control_serdes_if_rst;
ResetRfIf_ora <= ResetToRfIf_ra;
WbRegsInput.csr_status_SerdesIfRdy <= RfIfRdySys;
WbRegsInput.csr_status_SerdesIfRdyStable <= RfIfRdySysStable;
WbRegsInput.csr_status_serdes_if_rdy <= RfIfRdySys;
WbRegsInput.csr_status_serdes_if_rdy_stable <= RfIfRdySysStable;
-- keep zero value until next read
pRfIfRdyStable: process(Clk_ik) is begin
......@@ -287,8 +288,8 @@ begin
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_r,
TriggerValue_ib16 => WbRegsOutput.csr_trigger_threshold_value,
TriggerLoad_i => WbRegsOutput.csr_trigger_threshold_wr,
TriggerValue_ib16 => WbRegsOutput.csr_trig_threshold_value,
TriggerLoad_i => WbRegsOutput.csr_trig_threshold_wr,
VcxoValue_ib16 => WbRegsOutput.csr_vcxo_voltage_value,
VcxoLoad_i => WbRegsOutput.csr_vcxo_voltage_wr,
TriggerDac_o => TriggerDac_o,
......@@ -309,12 +310,12 @@ begin
Reset_ir => Reset_r,
Ch1SetValue_ib => WbRegsOutput.csr_ch1_delay_set_value,
Ch1SetValueLoad_i => WbRegsOutput.csr_ch1_delay_set_wr,
Ch1ResValue_ib => WbRegsOutput.csr_ch1_delay_reset_value,
Ch1ResValueLoad_i => WbRegsOutput.csr_ch1_delay_reset_wr,
Ch1ResValue_ib => WbRegsOutput.csr_ch1_delay_res_value,
Ch1ResValueLoad_i => WbRegsOutput.csr_ch1_delay_res_wr,
Ch2SetValue_ib => WbRegsOutput.csr_ch2_delay_set_value,
Ch2SetValueLoad_i => WbRegsOutput.csr_ch2_delay_set_wr,
Ch2ResValue_ib => WbRegsOutput.csr_ch2_delay_reset_value,
Ch2ResValueLoad_i => WbRegsOutput.csr_ch2_delay_reset_wr,
Ch2ResValue_ib => WbRegsOutput.csr_ch2_delay_res_value,
Ch2ResValueLoad_i => WbRegsOutput.csr_ch2_delay_res_wr,
DelayValue_ob => DelayValue_ob,
Ch1SetLe_on => Ch1SetLe_on,
Ch1ResLe_on => Ch1ResLe_on,
......@@ -326,10 +327,10 @@ begin
----------------------------------
-- output enable controls
----------------------------------
Ch1OutputEnable_o <= WbRegsOutput.csr_control_ch1_oe;
Ch2OutputEnable_o <= WbRegsOutput.csr_control_ch2_oe;
WbRegsInput.csr_status_channel_1_oe <= WbRegsOutput.csr_control_ch1_oe;
WbRegsInput.csr_status_channel_2_oe <= WbRegsOutput.csr_control_ch2_oe;
Ch1OutputEnable_o <= WbRegsOutput.csr_ch1_control_oe;
Ch2OutputEnable_o <= WbRegsOutput.csr_ch2_control_oe;
WbRegsInput.csr_ch1_status_oe <= WbRegsOutput.csr_ch1_control_oe;
WbRegsInput.csr_ch2_status_oe <= WbRegsOutput.csr_ch2_control_oe;
----------------------------------
-- serial stream generators in CDC entity
......@@ -352,48 +353,48 @@ begin
Ch2MemData_ib => WbRegsOutput.csr_ch2_mem_data_dat_o(9 downto 0),
Resync_i => WbRegsOutput.csr_sw_trigger_resync,
MaxBunchNum_i => WbRegsOutput.csr_MaxBunch_Num,
TrigLatInt_i => WbRegsOutput.csr_trigger_latency_Int,
TrigLatFrac_i => WbRegsOutput.csr_trigger_latency_Frac,
StreamOffVal_i => WbRegsOutput.csr_control_StopState,
Ch1NTurns_i => WbRegsOutput.csr_TurnsCh1,
Ch1NRepeats_i => WbRegsOutput.csr_IterationsCh1,
Ch1RepeatPause_i => WbRegsOutput.csr_PauseCh1,
Ch2NTurns_i => WbRegsOutput.csr_TurnsCh2,
Ch2NRepeats_i => WbRegsOutput.csr_IterationsCh2,
Ch2RepeatPause_i => WbRegsOutput.csr_PauseCh2,
Ch1Start_i => WbRegsOutput.csr_sw_trigger_ch1_start,
Ch1Stop_i => WbRegsOutput.csr_sw_trigger_ch1_stop,
Ch1StopImmediate_i => WbRegsOutput.csr_control_StopImmediateCh1,
Ch2Start_i => WbRegsOutput.csr_sw_trigger_ch2_start,
Ch2Stop_i => WbRegsOutput.csr_sw_trigger_ch2_stop,
Ch2StopImmediate_i => WbRegsOutput.csr_control_StopImmediateCh2,
Ch1Force_i => WbRegsOutput.csr_ForceCh1_wr,
Ch1SetForceVal_i => WbRegsOutput.csr_ForceCh1_SetVal,
Ch1RstForceVal_i => WbRegsOutput.csr_ForceCh1_ResetVal,
Ch1StateForceVal_i => WbRegsOutput.csr_ForceCh1_State,
Ch2Force_i => WbRegsOutput.csr_ForceCh2_wr,
Ch2SetForceVal_i => WbRegsOutput.csr_ForceCh2_SetVal,
Ch2RstForceVal_i => WbRegsOutput.csr_ForceCh2_ResetVal,
Ch2StateForceVal_i => WbRegsOutput.csr_ForceCh2_State,
Ch1Running_o => WbRegsInput.csr_status_channel_1_running,
Ch2Running_o => WbRegsInput.csr_status_channel_2_running,
MaxBunchNum_i => WbRegsOutput.csr_max_bunch_num,
TrigLatInt_i => WbRegsOutput.csr_trigger_latency_int,
TrigLatFrac_i => WbRegsOutput.csr_trigger_latency_frac,
StreamOffVal_i => WbRegsOutput.csr_control_stop_state,
Ch1NTurns_i => WbRegsOutput.csr_ch1_turns,
Ch1NRepeats_i => WbRegsOutput.csr_ch1_iterations,
Ch1RepeatPause_i => WbRegsOutput.csr_ch1_pause,
Ch2NTurns_i => WbRegsOutput.csr_ch2_turns,
Ch2NRepeats_i => WbRegsOutput.csr_ch2_iterations,
Ch2RepeatPause_i => WbRegsOutput.csr_ch2_pause,
Ch1Start_i => WbRegsOutput.csr_ch1_sw_trigger_start,
Ch1Stop_i => WbRegsOutput.csr_ch1_sw_trigger_stop,
Ch1StopImmediate_i => WbRegsOutput.csr_ch1_control_stop_immediate,
Ch2Start_i => WbRegsOutput.csr_ch2_sw_trigger_start,
Ch2Stop_i => WbRegsOutput.csr_ch2_sw_trigger_stop,
Ch2StopImmediate_i => WbRegsOutput.csr_ch2_control_stop_immediate,
Ch1Force_i => WbRegsOutput.csr_ch1_force_wr,
Ch1SetForceVal_i => WbRegsOutput.csr_ch1_force_set_val,
Ch1RstForceVal_i => WbRegsOutput.csr_ch1_force_res_val,
Ch1StateForceVal_i => WbRegsOutput.csr_ch1_force_state,
Ch2Force_i => WbRegsOutput.csr_ch2_force_wr,
Ch2SetForceVal_i => WbRegsOutput.csr_ch2_force_set_val,
Ch2RstForceVal_i => WbRegsOutput.csr_ch2_force_res_val,
Ch2StateForceVal_i => WbRegsOutput.csr_ch2_force_state,
Ch1Running_o => WbRegsInput.csr_ch1_status_running,
Ch2Running_o => WbRegsInput.csr_ch2_status_running,
ClkRf_ik => ClkRf_k,
ResetRf_ir => ResetRf_r,
Ch1SetStream_o => Ch1Set_o,
Ch1ResetStream_o => Ch1Res_o,
Ch2SetStream_o => Ch2Set_o,
Ch2ResetStream_o => Ch2Res_o,
Ch1GateState_o => WbRegsInput.csr_status_StreamStateCh1,
Ch2GateState_o => WbRegsInput.csr_status_StreamStateCh2,
Ch1GateState_o => WbRegsInput.csr_ch1_status_stream_state,
Ch2GateState_o => WbRegsInput.csr_ch2_status_stream_state,
Ch1FsmState_o => WbRegsInput.csr_debug(2 downto 0),
Ch2FsmState_o => WbRegsInput.csr_debug(5 downto 3)
);
......@@ -416,10 +417,10 @@ begin
);
-- OUT1 - enabled and running
LedSignal_b(1) <= WbRegsInput.csr_status_channel_1_running and WbRegsOutput.csr_control_ch1_oe;
LedSignal_b(1) <= WbRegsInput.csr_ch1_status_running and WbRegsOutput.csr_ch1_control_oe;
-- OUT2 - enabled and running
LedSignal_b(2) <= WbRegsInput.csr_status_channel_2_running and WbRegsOutput.csr_control_ch2_oe;
LedSignal_b(2) <= WbRegsInput.csr_ch2_status_running and WbRegsOutput.csr_ch2_control_oe;
-- TRIG IN
LedSignal_b(3) <= TriggerRf;
......@@ -592,11 +593,17 @@ begin
WbRegsInput.csr_status_input_clock_stable <= ClkRfStable;
----------------------------------
-- debug
-- Debug
----------------------------------
WbRegsInput.csr_debug(31 downto 6) <= (others => '0');
----------------------------------
-- Ident
----------------------------------
WbRegsInput.csr_ident <= g_Ident;
----------------------------------
-- Version information
----------------------------------
......
hdl/ffpg/rtl/FfpgCoreWrapper.vhd
View file @ cf959c95
......@@ -46,6 +46,7 @@ entity FfpgCoreWrapper is
generic (
g_ClkFrequency: positive; -- input clock frequency in Hz
g_Version: std_logic_vector(31 downto 0);
g_Ident: std_logic_vector(63 downto 0);
g_usePLL: boolean := True
);
port (
......@@ -115,7 +116,8 @@ architecture sp6 of FfpgCoreWrapper is
cFfpgCore: entity work.FfpgCore(syn)
generic map (
g_ClkFrequency => g_ClkFrequency, -- input clock frequency in Hz
g_Version => g_Version
g_Version => g_Version,
g_Ident => g_Ident
)
port map (
-- Wishbone connection
......
hdl/ffpg/rtl/ffpg_core_regs.vhd
View file @ cf959c95
This diff is collapsed.
hdl/ffpg/sim/testbench/ffpg_csr.svh
View file @ cf959c95
......@@ -2,252 +2,151 @@
// --consts-style=verilog --gen-consts ../sim/testbench/ffpg_csr.svh --header=commit --input ffpg_csr.cheby
`define FFPG_CSR_SIZE 49152
`define ADDR_FFPG_CSR_STATUS 'h0
`define ADDR_FFPG_CSR_STATUS_CLOCK_INFRASTRUCTURE_BUSY 'h0
`define ADDR_FFPG_CSR_IDENT 'h0
`define ADDR_FFPG_CSR_VERSION 'h8
`define ADDR_FFPG_CSR_VERSION_REVISION 'h8
`define FFPG_CSR_VERSION_REVISION_WIDTH 12
`define FFPG_CSR_VERSION_REVISION_OFFSET 0
`define FFPG_CSR_VERSION_REVISION 'hfff
`define ADDR_FFPG_CSR_VERSION_MINOR 'h8
`define FFPG_CSR_VERSION_MINOR_WIDTH 10
`define FFPG_CSR_VERSION_MINOR_OFFSET 12
`define FFPG_CSR_VERSION_MINOR 'h3ff000
`define ADDR_FFPG_CSR_VERSION_MAJOR 'h8
`define FFPG_CSR_VERSION_MAJOR_WIDTH 10
`define FFPG_CSR_VERSION_MAJOR_OFFSET 22
`define FFPG_CSR_VERSION_MAJOR 'hffc00000
`define ADDR_FFPG_CSR_STATUS 'hc
`define ADDR_FFPG_CSR_STATUS_CLOCK_INFRASTRUCTURE_BUSY 'hc
`define FFPG_CSR_STATUS_CLOCK_INFRASTRUCTURE_BUSY_WIDTH 1
`define FFPG_CSR_STATUS_CLOCK_INFRASTRUCTURE_BUSY_OFFSET 0
`define FFPG_CSR_STATUS_CLOCK_INFRASTRUCTURE_BUSY 'h1
`define ADDR_FFPG_CSR_STATUS_DAC_VCXO_BUSY 'h0
`define ADDR_FFPG_CSR_STATUS_DAC_VCXO_BUSY 'hc
`define FFPG_CSR_STATUS_DAC_VCXO_BUSY_WIDTH 1
`define FFPG_CSR_STATUS_DAC_VCXO_BUSY_OFFSET 1
`define FFPG_CSR_STATUS_DAC_VCXO_BUSY 'h2
`define ADDR_FFPG_CSR_STATUS_DAC_TRIGGER_BUSY 'h0
`define ADDR_FFPG_CSR_STATUS_DAC_TRIGGER_BUSY 'hc
`define FFPG_CSR_STATUS_DAC_TRIGGER_BUSY_WIDTH 1
`define FFPG_CSR_STATUS_DAC_TRIGGER_BUSY_OFFSET 2
`define FFPG_CSR_STATUS_DAC_TRIGGER_BUSY 'h4
`define ADDR_FFPG_CSR_STATUS_DELAY_CONFIGURATION_BUSY 'h0
`define ADDR_FFPG_CSR_STATUS_DELAY_CONFIGURATION_BUSY 'hc
`define FFPG_CSR_STATUS_DELAY_CONFIGURATION_BUSY_WIDTH 1
`define FFPG_CSR_STATUS_DELAY_CONFIGURATION_BUSY_OFFSET 3
`define FFPG_CSR_STATUS_DELAY_CONFIGURATION_BUSY 'h8
`define ADDR_FFPG_CSR_STATUS_CHANNEL_1_OE 'h0
`define FFPG_CSR_STATUS_CHANNEL_1_OE_WIDTH 1
`define FFPG_CSR_STATUS_CHANNEL_1_OE_OFFSET 4
`define FFPG_CSR_STATUS_CHANNEL_1_OE 'h10
`define ADDR_FFPG_CSR_STATUS_CHANNEL_2_OE 'h0
`define FFPG_CSR_STATUS_CHANNEL_2_OE_WIDTH 1
`define FFPG_CSR_STATUS_CHANNEL_2_OE_OFFSET 5
`define FFPG_CSR_STATUS_CHANNEL_2_OE 'h20
`define ADDR_FFPG_CSR_STATUS_CHANNEL_1_RUNNING 'h0
`define FFPG_CSR_STATUS_CHANNEL_1_RUNNING_WIDTH 1
`define FFPG_CSR_STATUS_CHANNEL_1_RUNNING_OFFSET 6
`define FFPG_CSR_STATUS_CHANNEL_1_RUNNING 'h40
`define ADDR_FFPG_CSR_STATUS_CHANNEL_2_RUNNING 'h0
`define FFPG_CSR_STATUS_CHANNEL_2_RUNNING_WIDTH 1
`define FFPG_CSR_STATUS_CHANNEL_2_RUNNING_OFFSET 7
`define FFPG_CSR_STATUS_CHANNEL_2_RUNNING 'h80
`define ADDR_FFPG_CSR_STATUS_INPUT_CLOCK_STABLE 'h0
`define ADDR_FFPG_CSR_STATUS_INPUT_CLOCK_STABLE 'hc
`define FFPG_CSR_STATUS_INPUT_CLOCK_STABLE_WIDTH 1
`define FFPG_CSR_STATUS_INPUT_CLOCK_STABLE_OFFSET 8
`define FFPG_CSR_STATUS_INPUT_CLOCK_STABLE 'h100
`define ADDR_FFPG_CSR_STATUS_STREAMSTATECH1 'h0
`define FFPG_CSR_STATUS_STREAMSTATECH1_WIDTH 1
`define FFPG_CSR_STATUS_STREAMSTATECH1_OFFSET 9
`define FFPG_CSR_STATUS_STREAMSTATECH1 'h200
`define ADDR_FFPG_CSR_STATUS_STREAMSTATECH2 'h0
`define FFPG_CSR_STATUS_STREAMSTATECH2_WIDTH 1
`define FFPG_CSR_STATUS_STREAMSTATECH2_OFFSET 10
`define FFPG_CSR_STATUS_STREAMSTATECH2 'h400
`define ADDR_FFPG_CSR_STATUS_SERDESIFRDY 'h0
`define FFPG_CSR_STATUS_SERDESIFRDY_WIDTH 1
`define FFPG_CSR_STATUS_SERDESIFRDY_OFFSET 11
`define FFPG_CSR_STATUS_SERDESIFRDY 'h800
`define ADDR_FFPG_CSR_STATUS_SERDESIFRDYSTABLE 'h0
`define FFPG_CSR_STATUS_SERDESIFRDYSTABLE_WIDTH 1
`define FFPG_CSR_STATUS_SERDESIFRDYSTABLE_OFFSET 12
`define FFPG_CSR_STATUS_SERDESIFRDYSTABLE 'h1000
`define ADDR_FFPG_CSR_CONTROL 'h4
`define ADDR_FFPG_CSR_CONTROL_CLOCK_SELECTION 'h4
`define ADDR_FFPG_CSR_STATUS_SERDES_IF_RDY 'hc
`define FFPG_CSR_STATUS_SERDES_IF_RDY_WIDTH 1
`define FFPG_CSR_STATUS_SERDES_IF_RDY_OFFSET 11
`define FFPG_CSR_STATUS_SERDES_IF_RDY 'h800
`define ADDR_FFPG_CSR_STATUS_SERDES_IF_RDY_STABLE 'hc
`define FFPG_CSR_STATUS_SERDES_IF_RDY_STABLE_WIDTH 1
`define FFPG_CSR_STATUS_SERDES_IF_RDY_STABLE_OFFSET 12
`define FFPG_CSR_STATUS_SERDES_IF_RDY_STABLE 'h1000
`define ADDR_FFPG_CSR_CONTROL 'h10
`define ADDR_FFPG_CSR_CONTROL_CLOCK_SELECTION 'h10
`define FFPG_CSR_CONTROL_CLOCK_SELECTION_WIDTH 2
`define FFPG_CSR_CONTROL_CLOCK_SELECTION_OFFSET 0
`define FFPG_CSR_CONTROL_CLOCK_SELECTION 'h3
`define ADDR_FFPG_CSR_CONTROL_CH1_OE 'h4
`define FFPG_CSR_CONTROL_CH1_OE_WIDTH 1
`define FFPG_CSR_CONTROL_CH1_OE_OFFSET 2
`define FFPG_CSR_CONTROL_CH1_OE 'h4
`define ADDR_FFPG_CSR_CONTROL_CH2_OE 'h4
`define FFPG_CSR_CONTROL_CH2_OE_WIDTH 1
`define FFPG_CSR_CONTROL_CH2_OE_OFFSET 3
`define FFPG_CSR_CONTROL_CH2_OE 'h8
`define ADDR_FFPG_CSR_CONTROL_LED_TEST 'h4
`define ADDR_FFPG_CSR_CONTROL_LED_TEST 'h10
`define FFPG_CSR_CONTROL_LED_TEST_WIDTH 1
`define FFPG_CSR_CONTROL_LED_TEST_OFFSET 8
`define FFPG_CSR_CONTROL_LED_TEST 'h100
`define ADDR_FFPG_CSR_CONTROL_AD9512_SYNC 'h4
`define ADDR_FFPG_CSR_CONTROL_AD9512_SYNC 'h10
`define FFPG_CSR_CONTROL_AD9512_SYNC_WIDTH 1
`define FFPG_CSR_CONTROL_AD9512_SYNC_OFFSET 9
`define FFPG_CSR_CONTROL_AD9512_SYNC 'h200
`define ADDR_FFPG_CSR_CONTROL_FINE_DELAY_ENABLE 'h4
`define ADDR_FFPG_CSR_CONTROL_FINE_DELAY_ENABLE 'h10
`define FFPG_CSR_CONTROL_FINE_DELAY_ENABLE_WIDTH 1
`define FFPG_CSR_CONTROL_FINE_DELAY_ENABLE_OFFSET 10
`define FFPG_CSR_CONTROL_FINE_DELAY_ENABLE 'h400
`define ADDR_FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE 'h4
`define ADDR_FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE 'h10
`define FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE_WIDTH 1
`define FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE_OFFSET 11
`define FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE 'h800
`define ADDR_FFPG_CSR_CONTROL_AD9512_START_CONFIG 'h4
`define ADDR_FFPG_CSR_CONTROL_AD9512_START_CONFIG 'h10
`define FFPG_CSR_CONTROL_AD9512_START_CONFIG_WIDTH 1
`define FFPG_CSR_CONTROL_AD9512_START_CONFIG_OFFSET 12
`define FFPG_CSR_CONTROL_AD9512_START_CONFIG 'h1000
`define ADDR_FFPG_CSR_CONTROL_SERDESIFRST 'h4
`define FFPG_CSR_CONTROL_SERDESIFRST_WIDTH 1
`define FFPG_CSR_CONTROL_SERDESIFRST_OFFSET 13
`define FFPG_CSR_CONTROL_SERDESIFRST 'h2000
`define FFPG_CSR_CONTROL_SERDESIFRST_PRESET 'h1
`define ADDR_FFPG_CSR_CONTROL_RFLOGICRST 'h4
`define FFPG_CSR_CONTROL_RFLOGICRST_WIDTH 1
`define FFPG_CSR_CONTROL_RFLOGICRST_OFFSET 14
`define FFPG_CSR_CONTROL_RFLOGICRST 'h4000
`define FFPG_CSR_CONTROL_RFLOGICRST_PRESET 'h1
`define ADDR_FFPG_CSR_CONTROL_STOPIMMEDIATECH1 'h4
`define FFPG_CSR_CONTROL_STOPIMMEDIATECH1_WIDTH 1
`define FFPG_CSR_CONTROL_STOPIMMEDIATECH1_OFFSET 16
`define FFPG_CSR_CONTROL_STOPIMMEDIATECH1 'h10000
`define ADDR_FFPG_CSR_CONTROL_STOPIMMEDIATECH2 'h4
`define FFPG_CSR_CONTROL_STOPIMMEDIATECH2_WIDTH 1
`define FFPG_CSR_CONTROL_STOPIMMEDIATECH2_OFFSET 17
`define FFPG_CSR_CONTROL_STOPIMMEDIATECH2 'h20000
`define ADDR_FFPG_CSR_CONTROL_STOPSTATE 'h4
`define FFPG_CSR_CONTROL_STOPSTATE_WIDTH 1
`define FFPG_CSR_CONTROL_STOPSTATE_OFFSET 18
`define FFPG_CSR_CONTROL_STOPSTATE 'h40000
`define ADDR_FFPG_CSR_VCXO_VOLTAGE 'h8
`define ADDR_FFPG_CSR_VCXO_VOLTAGE_VALUE 'h8
`define ADDR_FFPG_CSR_CONTROL_SERDES_IF_RST 'h10
`define FFPG_CSR_CONTROL_SERDES_IF_RST_WIDTH 1
`define FFPG_CSR_CONTROL_SERDES_IF_RST_OFFSET 13
`define FFPG_CSR_CONTROL_SERDES_IF_RST 'h2000
`define FFPG_CSR_CONTROL_SERDES_IF_RST_PRESET 'h1
`define ADDR_FFPG_CSR_CONTROL_RF_LOGIC_RST 'h10
`define FFPG_CSR_CONTROL_RF_LOGIC_RST_WIDTH 1
`define FFPG_CSR_CONTROL_RF_LOGIC_RST_OFFSET 14
`define FFPG_CSR_CONTROL_RF_LOGIC_RST 'h4000
`define FFPG_CSR_CONTROL_RF_LOGIC_RST_PRESET 'h1
`define ADDR_FFPG_CSR_CONTROL_STOP_STATE 'h10
`define FFPG_CSR_CONTROL_STOP_STATE_WIDTH 1
`define FFPG_CSR_CONTROL_STOP_STATE_OFFSET 15
`define FFPG_CSR_CONTROL_STOP_STATE 'h8000
`define ADDR_FFPG_CSR_VCXO_VOLTAGE 'h14
`define ADDR_FFPG_CSR_VCXO_VOLTAGE_VALUE 'h14
`define FFPG_CSR_VCXO_VOLTAGE_VALUE_WIDTH 16
`define FFPG_CSR_VCXO_VOLTAGE_VALUE_OFFSET 0
`define FFPG_CSR_VCXO_VOLTAGE_VALUE 'hffff
`define ADDR_FFPG_CSR_CLOCK_RATIO_M1 'hc
`define ADDR_FFPG_CSR_CLOCK_RATIO_M1_VALUE 'hc
`define ADDR_FFPG_CSR_CLOCK_RATIO_M1 'h18
`define ADDR_FFPG_CSR_CLOCK_RATIO_M1_VALUE 'h18
`define FFPG_CSR_CLOCK_RATIO_M1_VALUE_WIDTH 5
`define FFPG_CSR_CLOCK_RATIO_M1_VALUE_OFFSET 0
`define FFPG_CSR_CLOCK_RATIO_M1_VALUE 'h1f
`define ADDR_FFPG_CSR_CLOCK_RATIO_M1_EXT 'hc
`define ADDR_FFPG_CSR_CLOCK_RATIO_M1_EXT 'h18
`define FFPG_CSR_CLOCK_RATIO_M1_EXT_WIDTH 5
`define FFPG_CSR_CLOCK_RATIO_M1_EXT_OFFSET 16
`define FFPG_CSR_CLOCK_RATIO_M1_EXT 'h1f0000
`define ADDR_FFPG_CSR_CH1_DELAY_SET 'h10
`define ADDR_FFPG_CSR_CH1_DELAY_SET_VALUE 'h10
`define FFPG_CSR_CH1_DELAY_SET_VALUE_WIDTH 10
`define FFPG_CSR_CH1_DELAY_SET_VALUE_OFFSET 0
`define FFPG_CSR_CH1_DELAY_SET_VALUE 'h3ff
`define ADDR_FFPG_CSR_CH1_DELAY_RESET 'h14
`define ADDR_FFPG_CSR_CH1_DELAY_RESET_VALUE 'h14
`define FFPG_CSR_CH1_DELAY_RESET_VALUE_WIDTH 10
`define FFPG_CSR_CH1_DELAY_RESET_VALUE_OFFSET 0
`define FFPG_CSR_CH1_DELAY_RESET_VALUE 'h3ff
`define ADDR_FFPG_CSR_CH2_DELAY_SET 'h18
`define ADDR_FFPG_CSR_CH2_DELAY_SET_VALUE 'h18
`define FFPG_CSR_CH2_DELAY_SET_VALUE_WIDTH 10
`define FFPG_CSR_CH2_DELAY_SET_VALUE_OFFSET 0
`define FFPG_CSR_CH2_DELAY_SET_VALUE 'h3ff
`define ADDR_FFPG_CSR_CH2_DELAY_RESET 'h1c
`define ADDR_FFPG_CSR_CH2_DELAY_RESET_VALUE 'h1c
`define FFPG_CSR_CH2_DELAY_RESET_VALUE_WIDTH 10
`define FFPG_CSR_CH2_DELAY_RESET_VALUE_OFFSET 0
`define FFPG_CSR_CH2_DELAY_RESET_VALUE 'h3ff
`define ADDR_FFPG_CSR_TRIGGER_THRESHOLD 'h20
`define ADDR_FFPG_CSR_TRIGGER_THRESHOLD_VALUE 'h20
`define FFPG_CSR_TRIGGER_THRESHOLD_VALUE_WIDTH 16
`define FFPG_CSR_TRIGGER_THRESHOLD_VALUE_OFFSET 0
`define FFPG_CSR_TRIGGER_THRESHOLD_VALUE 'hffff
`define ADDR_FFPG_CSR_MAXBUNCH 'h24
`define ADDR_FFPG_CSR_MAXBUNCH_NUM 'h24
`define FFPG_CSR_MAXBUNCH_NUM_WIDTH 12
`define FFPG_CSR_MAXBUNCH_NUM_OFFSET 0
`define FFPG_CSR_MAXBUNCH_NUM 'hfff
`define ADDR_FFPG_CSR_TRIGGER_LATENCY 'h28
`define ADDR_FFPG_CSR_TRIGGER_LATENCY_INT 'h28
`define ADDR_FFPG_CSR_TRIG_THRESHOLD 'h1c
`define ADDR_FFPG_CSR_TRIG_THRESHOLD_VALUE 'h1c
`define FFPG_CSR_TRIG_THRESHOLD_VALUE_WIDTH 16
`define FFPG_CSR_TRIG_THRESHOLD_VALUE_OFFSET 0
`define FFPG_CSR_TRIG_THRESHOLD_VALUE 'hffff
`define ADDR_FFPG_CSR_MAX_BUNCH 'h20
`define ADDR_FFPG_CSR_MAX_BUNCH_NUM 'h20
`define FFPG_CSR_MAX_BUNCH_NUM_WIDTH 12
`define FFPG_CSR_MAX_BUNCH_NUM_OFFSET 0
`define FFPG_CSR_MAX_BUNCH_NUM 'hfff
`define ADDR_FFPG_CSR_TRIGGER_LATENCY 'h24
`define ADDR_FFPG_CSR_TRIGGER_LATENCY_INT 'h24
`define FFPG_CSR_TRIGGER_LATENCY_INT_WIDTH 12
`define FFPG_CSR_TRIGGER_LATENCY_INT_OFFSET 8
`define FFPG_CSR_TRIGGER_LATENCY_INT 'hfff00
`define ADDR_FFPG_CSR_TRIGGER_LATENCY_FRAC 'h28
`define ADDR_FFPG_CSR_TRIGGER_LATENCY_FRAC 'h24
`define FFPG_CSR_TRIGGER_LATENCY_FRAC_WIDTH 4
`define FFPG_CSR_TRIGGER_LATENCY_FRAC_OFFSET 0
`define FFPG_CSR_TRIGGER_LATENCY_FRAC 'hf
`define ADDR_FFPG_CSR_FREQUENCY 'h2c
`define ADDR_FFPG_CSR_DEBUG 'h30
`define ADDR_FFPG_CSR_VERSION 'h34
`define ADDR_FFPG_CSR_VERSION_REVISION 'h34
`define FFPG_CSR_VERSION_REVISION_WIDTH 12
`define FFPG_CSR_VERSION_REVISION_OFFSET 0
`define FFPG_CSR_VERSION_REVISION 'hfff
`define ADDR_FFPG_CSR_VERSION_MINOR 'h34
`define FFPG_CSR_VERSION_MINOR_WIDTH 10
`define FFPG_CSR_VERSION_MINOR_OFFSET 12
`define FFPG_CSR_VERSION_MINOR 'h3ff000
`define ADDR_FFPG_CSR_VERSION_MAJOR 'h34
`define FFPG_CSR_VERSION_MAJOR_WIDTH 10
`define FFPG_CSR_VERSION_MAJOR_OFFSET 22
`define FFPG_CSR_VERSION_MAJOR 'hffc00000
`define ADDR_FFPG_CSR_SW_TRIGGER 'h38
`define ADDR_FFPG_CSR_SW_TRIGGER_CH1_START 'h38
`define FFPG_CSR_SW_TRIGGER_CH1_START_WIDTH 1
`define FFPG_CSR_SW_TRIGGER_CH1_START_OFFSET 0
`define FFPG_CSR_SW_TRIGGER_CH1_START 'h1
`define ADDR_FFPG_CSR_SW_TRIGGER_CH2_START 'h38
`define FFPG_CSR_SW_TRIGGER_CH2_START_WIDTH 1
`define FFPG_CSR_SW_TRIGGER_CH2_START_OFFSET 1
`define FFPG_CSR_SW_TRIGGER_CH2_START 'h2
`define ADDR_FFPG_CSR_SW_TRIGGER_CH1_STOP 'h38
`define FFPG_CSR_SW_TRIGGER_CH1_STOP_WIDTH 1
`define FFPG_CSR_SW_TRIGGER_CH1_STOP_OFFSET 2
`define FFPG_CSR_SW_TRIGGER_CH1_STOP 'h4
`define ADDR_FFPG_CSR_SW_TRIGGER_CH2_STOP 'h38
`define FFPG_CSR_SW_TRIGGER_CH2_STOP_WIDTH 1
`define FFPG_CSR_SW_TRIGGER_CH2_STOP_OFFSET 3
`define FFPG_CSR_SW_TRIGGER_CH2_STOP 'h8
`define ADDR_FFPG_CSR_SW_TRIGGER_RESYNC 'h38
`define ADDR_FFPG_CSR_FREQUENCY 'h28
`define ADDR_FFPG_CSR_DEBUG 'h2c
`define ADDR_FFPG_CSR_SW_TRIGGER 'h30
`define ADDR_FFPG_CSR_SW_TRIGGER_RESYNC 'h30
`define FFPG_CSR_SW_TRIGGER_RESYNC_WIDTH 1
`define FFPG_CSR_SW_TRIGGER_RESYNC_OFFSET 8
`define FFPG_CSR_SW_TRIGGER_RESYNC 'h100
`define ADDR_FFPG_CSR_SW_TRIGGER_TRIGGER 'h38
`define FFPG_CSR_SW_TRIGGER_RESYNC_OFFSET 0
`define FFPG_CSR_SW_TRIGGER_RESYNC 'h1
`define ADDR_FFPG_CSR_SW_TRIGGER_TRIGGER 'h30
`define FFPG_CSR_SW_TRIGGER_TRIGGER_WIDTH 5
`define FFPG_CSR_SW_TRIGGER_TRIGGER_OFFSET 9
`define FFPG_CSR_SW_TRIGGER_TRIGGER 'h3e00
`define ADDR_FFPG_CSR_FINE_DELAY 'h3c
`define ADDR_FFPG_CSR_FINE_DELAY_VALUE 'h3c
`define FFPG_CSR_SW_TRIGGER_TRIGGER_OFFSET 1
`define FFPG_CSR_SW_TRIGGER_TRIGGER 'h3e
`define ADDR_FFPG_CSR_FINE_DELAY 'h34
`define ADDR_FFPG_CSR_FINE_DELAY_VALUE 'h34
`define FFPG_CSR_FINE_DELAY_VALUE_WIDTH 5
`define FFPG_CSR_FINE_DELAY_VALUE_OFFSET 0
`define FFPG_CSR_FINE_DELAY_VALUE 'h1f
`define ADDR_FFPG_CSR_FINE_DELAY_CURRENT 'h3c
`define ADDR_FFPG_CSR_FINE_DELAY_CURRENT 'h34
`define FFPG_CSR_FINE_DELAY_CURRENT_WIDTH 3
`define FFPG_CSR_FINE_DELAY_CURRENT_OFFSET 5
`define FFPG_CSR_FINE_DELAY_CURRENT 'he0
`define ADDR_FFPG_CSR_FINE_DELAY_CAPACITORS 'h3c
`define ADDR_FFPG_CSR_FINE_DELAY_CAPACITORS 'h34
`define FFPG_CSR_FINE_DELAY_CAPACITORS_WIDTH 3
`define FFPG_CSR_FINE_DELAY_CAPACITORS_OFFSET 8
`define FFPG_CSR_FINE_DELAY_CAPACITORS 'h700
`define ADDR_FFPG_CSR_ITERATIONSCH1 'h40
`define ADDR_FFPG_CSR_TURNSCH1 'h44
`define ADDR_FFPG_CSR_PAUSECH1 'h48
`define ADDR_FFPG_CSR_FORCECH1 'h4c
`define ADDR_FFPG_CSR_FORCECH1_SETVAL 'h4c
`define FFPG_CSR_FORCECH1_SETVAL_WIDTH 5
`define FFPG_CSR_FORCECH1_SETVAL_OFFSET 0
`define FFPG_CSR_FORCECH1_SETVAL 'h1f
`define ADDR_FFPG_CSR_FORCECH1_RESETVAL 'h4c
`define FFPG_CSR_FORCECH1_RESETVAL_WIDTH 5
`define FFPG_CSR_FORCECH1_RESETVAL_OFFSET 5
`define FFPG_CSR_FORCECH1_RESETVAL 'h3e0
`define ADDR_FFPG_CSR_FORCECH1_STATE 'h4c
`define FFPG_CSR_FORCECH1_STATE_WIDTH 1
`define FFPG_CSR_FORCECH1_STATE_OFFSET 10
`define FFPG_CSR_FORCECH1_STATE 'h400
`define ADDR_FFPG_CSR_ITERATIONSCH2 'h50
`define ADDR_FFPG_CSR_TURNSCH2 'h54
`define ADDR_FFPG_CSR_PAUSECH2 'h58
`define ADDR_FFPG_CSR_FORCECH2 'h5c
`define ADDR_FFPG_CSR_FORCECH2_SETVAL 'h5c
`define FFPG_CSR_FORCECH2_SETVAL_WIDTH 5
`define FFPG_CSR_FORCECH2_SETVAL_OFFSET 0
`define FFPG_CSR_FORCECH2_SETVAL 'h1f
`define ADDR_FFPG_CSR_FORCECH2_RESETVAL 'h5c
`define FFPG_CSR_FORCECH2_RESETVAL_WIDTH 5
`define FFPG_CSR_FORCECH2_RESETVAL_OFFSET 5
`define FFPG_CSR_FORCECH2_RESETVAL 'h3e0
`define ADDR_FFPG_CSR_FORCECH2_STATE 'h5c
`define FFPG_CSR_FORCECH2_STATE_WIDTH 1
`define FFPG_CSR_FORCECH2_STATE_OFFSET 10
`define FFPG_CSR_FORCECH2_STATE 'h400
`define ADDR_FFPG_CSR_CH1 'h40
`define ADDR_MASK_FFPG_CSR_CH1 'hffc0
`define FFPG_CSR_CH1_SIZE 64
`define ADDR_FFPG_CSR_CH2 'h80
`define ADDR_MASK_FFPG_CSR_CH2 'hffc0
`define FFPG_CSR_CH2_SIZE 64
`define ADDR_FFPG_CSR_CH1_MEM 'h4000
`define FFPG_CSR_CH1_MEM_SIZE 4
`define ADDR_FFPG_CSR_CH1_MEM_DATA 'h0
......
hdl/top/spec/spec_top_ffpg.vhd
View file @ cf959c95
......@@ -384,7 +384,8 @@ begin
cFmc0FfpgCore: entity work.FfpgCoreWrapper(sp6)
generic map (
g_ClkFrequency => 62500000, -- in Hz
g_Version => sourceid_spec_top_ffpg_pkg.version
g_Version => sourceid_spec_top_ffpg_pkg.version,
g_Ident => X"66667067_30000000"
)
port map (
Clk_ik => clk_sys_62m5,
......
hdl/top/svec/svec_top_ffpg.vhd
View file @ cf959c95
......@@ -558,7 +558,8 @@ begin
cFmc0FfpgCore: entity work.FfpgCoreWrapper(sp6)
generic map (
g_ClkFrequency => 62500000, -- in Hz
g_Version => sourceid_svec_top_ffpg_pkg.version
g_Version => sourceid_svec_top_ffpg_pkg.version,
g_Ident => X"66667067_30000000"
)
port map (
Clk_ik => clk_sys_62m5,
......@@ -605,7 +606,8 @@ begin
cFmc1FfpgCore: entity work.FfpgCoreWrapper(sp6)
generic map (
g_ClkFrequency => 62500000, -- in Hz
g_Version => sourceid_svec_top_ffpg_pkg.version
g_Version => sourceid_svec_top_ffpg_pkg.version,
g_Ident => X"66667067_31000000"
)
port map (
Clk_ik => clk_sys_62m5,
......
sw/driver/fmc_fpg_pci_hw_desc.csv
View file @ cf959c95
#Encore Driver GEnerator version 3.1
# Module description table
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 1.0.0-pci, 3.1, PCI, LE, FMC Fast Pulse Generator
# Device Identification table definition
vendor, device, args
0x10DC, 0x01A3, subvendor=0x1A39 subdevice=0x0004
# BARs definition table
res_def_name, type, res_no, args, description
registers, MEM, 0, ,
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
csr, REG, status, 0x0, r, 32, 0x1, , , Status register
csr, REG, control, 0x4, rw, 32, 0x1, , , Control register
csr, REG, vcxo_voltage, 0x8, rw, 32, 0x1, , , VCXO voltage
csr, REG, clock_ratio_m1, 0xc, rw, 32, 0x1, , , Clock ratio minus 1
csr, REG, ch1_delay_set, 0x10, rw, 32, 0x1, , , CH1 set delay
csr, REG, ch1_delay_res, 0x14, rw, 32, 0x1, , , CH1 reset delay
csr, REG, ch2_delay_set, 0x18, rw, 32, 0x1, , , CH2 set delay
csr, REG, ch2_delay_res, 0x1c, rw, 32, 0x1, , , CH2 reset delay
csr, REG, trig_threshold, 0x20, rw, 32, 0x1, , , Trigger threshold voltage
csr, REG, overflow, 0x24, rw, 32, 0x1, , , Overflow
csr, REG, ch1_trig_latency, 0x28, rw, 32, 0x1, , , CH1 trigger latency
csr, REG, frequency, 0x2c, r, 32, 0x1, , , Clock frequency
csr, REG, debug, 0x30, r, 32, 0x1, , , Debug register
csr, REG, version, 0x34, r, 32, 0x1, , , FFPG version
csr, REG, ch2_trig_latency, 0x38, rw, 32, 0x1, , , CH2 trigger latency
csr, REG, fine_delay, 0x3c, rw, 32, 0x1, , , AD9512 OUT4 fine delay
csr, REG, ch1_set_mem, 0x2000, rw, 32, 0x800, , , CH1 SET serial stream
csr, REG, ch1_res_mem, 0x4000, rw, 32, 0x800, , , CH1 RES serial stream
csr, REG, ch2_set_mem, 0x6000, rw, 32, 0x800, , , CH2 SET serial stream
csr, REG, ch2_res_mem, 0x8000, rw, 32, 0x800, , , CH2 RES serial stream
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, rw, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, rw, 32, 0x1, , , Shift in register
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
# Block instances table
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x21000, OneWire master
spi_master, spi_master, registers, 0x22000, WB SPI master
csr, csr, registers, 0x30000, Control/status registers
# Reg roles table
reg_role, reg_name, block_def_name, args
#Encore Driver GEnerator version: 3.1
#LIF (Logical Interface) table definition
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 3.0.0-pci, 3.1, PCI, LE, FMC Fast Pulse Generator
#Device Identification table definition
vendor, device, args
0x10dc, 0x1a3, subvendor=0x1a39 subdevice=0x4
#Resources (Memory(BARs) - DMA - IRQ) table definition
res_def_name, type, res_no, args, description
registers, MEM, 0, ,
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, r, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, r, 32, 0x1, , , Shift in register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
ffpg_csr, REG, ident, 0x0, r, 64, 0x1, , , FFPG ident
ffpg_csr, REG, version, 0x8, r, 32, 0x1, , , FFPG version
ffpg_csr, REG, status, 0xc, r, 32, 0x1, , , Status register
ffpg_csr, REG, control, 0x10, rw, 32, 0x1, , , Control register
ffpg_csr, REG, vcxo_voltage, 0x14, rw, 32, 0x1, , , VCXO voltage
ffpg_csr, REG, clock_ratio_m1, 0x18, rw, 32, 0x1, , , Clock ratio minus 1
ffpg_csr, REG, trig_threshold, 0x1c, rw, 32, 0x1, , , Trigger threshold voltage
ffpg_csr, REG, max_bunch, 0x20, rw, 32, 0x1, , , Maximum bunch number
ffpg_csr, REG, trigger_latency, 0x24, rw, 32, 0x1, , , Trigger latency
ffpg_csr, REG, frequency, 0x28, r, 32, 0x1, , , Clock frequency
ffpg_csr, REG, debug, 0x2c, r, 32, 0x1, , , Debug register
ffpg_csr, REG, sw_trigger, 0x30, rw, 32, 0x1, , , Software triggers
ffpg_csr, REG, fine_delay, 0x34, rw, 32, 0x1, , , AD9512 OUT4 fine delay
ffpg_csr, ffpg_ch, ch1, 0x40, , , , , , Channel 1 registers
ffpg_csr, ffpg_ch, ch2, 0x80, , , , , , Channel 2 registers
ffpg_csr, REG, ch1_mem, 0x4000, rw, 32, 0x1000, , , CH1 output state serial stream
ffpg_csr, REG, ch2_mem, 0x8000, rw, 32, 0x1000, , , CH2 output state serial stream
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
ffpg_ch, REG, status, 0x0, r, 32, 0x1, , , Status register
ffpg_ch, REG, control, 0x4, rw, 32, 0x1, , , Control register
ffpg_ch, REG, sw_trigger, 0x8, rw, 32, 0x1, , , Software triggers
ffpg_ch, REG, delay_set, 0x10, rw, 32, 0x1, , , Set delay
ffpg_ch, REG, delay_res, 0x14, rw, 32, 0x1, , , Reset delay
ffpg_ch, REG, iterations, 0x18, rw, 32, 0x1, , , Number of stream iterations. 0 means infinite or until stop trigger.
ffpg_ch, REG, turns, 0x1c, rw, 32, 0x1, , , Number of stream turns per each stream iteration. 0 is aliased to 1.
ffpg_ch, REG, pause, 0x20, rw, 32, 0x1, , , Transmit idle value for N turns between two stream iterations.
ffpg_ch, REG, force, 0x24, rw, 32, 0x1, , , Force set/reset and current state values. Intended for initialization.
#Block instances table definition
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x1000, OneWire master
spi_master, spi_master, registers, 0x2000, WB SPI master
csr, ffpg_csr, registers, 0x10000, Control/status registers
#Interrupt Controller (INTC) table definition
intc_name, type, reg_name, block_def_name, chained_intc_name, chained_intc_mask, args, description
#Register Roles table definition
reg_role, reg_name, block_def_name, args
sw/driver/fmc_fpg_vme_hw_desc.csv
View file @ cf959c95
#Encore Driver GEnerator version 3.1
# Module description table
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 1.0.0-vme, 3.1, VME, BE, FMC Fast Pulse Generator
# BARs definition table
res_def_name, type, res_no, args, description
registers, MEM, 0, addrspace=A24 dwidth=32 size=0x20000 dma=BLT|MBLT,
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
csr, REG, status, 0x0, r, 32, 0x1, , , Status register
csr, REG, control, 0x4, rw, 32, 0x1, , , Control register
csr, REG, vcxo_voltage, 0x8, rw, 32, 0x1, , , VCXO voltage
csr, REG, clock_ratio_m1, 0xc, rw, 32, 0x1, , , Clock ratio minus 1
csr, REG, ch1_delay_set, 0x10, rw, 32, 0x1, , , CH1 set delay
csr, REG, ch1_delay_res, 0x14, rw, 32, 0x1, , , CH1 reset delay
csr, REG, ch2_delay_set, 0x18, rw, 32, 0x1, , , CH2 set delay
csr, REG, ch2_delay_res, 0x1c, rw, 32, 0x1, , , CH2 reset delay
csr, REG, trig_threshold, 0x20, rw, 32, 0x1, , , Trigger threshold voltage
csr, REG, overflow, 0x24, rw, 32, 0x1, , , Overflow
csr, REG, ch1_trig_latency, 0x28, rw, 32, 0x1, , , CH1 trigger latency
csr, REG, frequency, 0x2c, r, 32, 0x1, , , Clock frequency
csr, REG, debug, 0x30, r, 32, 0x1, , , Debug register
csr, REG, version, 0x34, r, 32, 0x1, , , FFPG version
csr, REG, ch2_trig_latency, 0x38, rw, 32, 0x1, , , CH2 trigger latency
csr, REG, fine_delay, 0x3c, rw, 32, 0x1, , , AD9512 OUT4 fine delay
csr, REG, ch1_set_mem, 0x2000, rw, 32, 0x800, , , CH1 SET serial stream
csr, REG, ch1_res_mem, 0x4000, rw, 32, 0x800, , , CH1 RES serial stream
csr, REG, ch2_set_mem, 0x6000, rw, 32, 0x800, , , CH2 SET serial stream
csr, REG, ch2_res_mem, 0x8000, rw, 32, 0x800, , , CH2 RES serial stream
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, rw, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, rw, 32, 0x1, , , Shift in register
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
# Block instances table
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x21000, OneWire master
spi_master, spi_master, registers, 0x22000, WB SPI master
csr, csr, registers, 0x30000, Control/status registers
# Reg roles table
reg_role, reg_name, block_def_name, args
#Encore Driver GEnerator version: 3.1
#LIF (Logical Interface) table definition
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 3.0.0-vme, 3.1, VME, BE, FMC Fast Pulse Generator
#Resources (Memory(BARs) - DMA - IRQ) table definition
res_def_name, type, res_no, args, description
registers, MEM, 0, addrspace=A24 dwidth=32 size=0x20000 dma=BLT|MBLT,
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, r, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, r, 32, 0x1, , , Shift in register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
ffpg_csr, REG, ident, 0x0, r, 64, 0x1, , , FFPG ident
ffpg_csr, REG, version, 0x8, r, 32, 0x1, , , FFPG version
ffpg_csr, REG, status, 0xc, r, 32, 0x1, , , Status register
ffpg_csr, REG, control, 0x10, rw, 32, 0x1, , , Control register
ffpg_csr, REG, vcxo_voltage, 0x14, rw, 32, 0x1, , , VCXO voltage
ffpg_csr, REG, clock_ratio_m1, 0x18, rw, 32, 0x1, , , Clock ratio minus 1
ffpg_csr, REG, trig_threshold, 0x1c, rw, 32, 0x1, , , Trigger threshold voltage
ffpg_csr, REG, max_bunch, 0x20, rw, 32, 0x1, , , Maximum bunch number
ffpg_csr, REG, trigger_latency, 0x24, rw, 32, 0x1, , , Trigger latency
ffpg_csr, REG, frequency, 0x28, r, 32, 0x1, , , Clock frequency
ffpg_csr, REG, debug, 0x2c, r, 32, 0x1, , , Debug register
ffpg_csr, REG, sw_trigger, 0x30, rw, 32, 0x1, , , Software triggers
ffpg_csr, REG, fine_delay, 0x34, rw, 32, 0x1, , , AD9512 OUT4 fine delay
ffpg_csr, ffpg_ch, ch1, 0x40, , , , , , Channel 1 registers
ffpg_csr, ffpg_ch, ch2, 0x80, , , , , , Channel 2 registers
ffpg_csr, REG, ch1_mem, 0x4000, rw, 32, 0x1000, , , CH1 output state serial stream
ffpg_csr, REG, ch2_mem, 0x8000, rw, 32, 0x1000, , , CH2 output state serial stream
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
ffpg_ch, REG, status, 0x0, r, 32, 0x1, , , Status register
ffpg_ch, REG, control, 0x4, rw, 32, 0x1, , , Control register
ffpg_ch, REG, sw_trigger, 0x8, rw, 32, 0x1, , , Software triggers
ffpg_ch, REG, delay_set, 0x10, rw, 32, 0x1, , , Set delay
ffpg_ch, REG, delay_res, 0x14, rw, 32, 0x1, , , Reset delay
ffpg_ch, REG, iterations, 0x18, rw, 32, 0x1, , , Number of stream iterations. 0 means infinite or until stop trigger.
ffpg_ch, REG, turns, 0x1c, rw, 32, 0x1, , , Number of stream turns per each stream iteration. 0 is aliased to 1.
ffpg_ch, REG, pause, 0x20, rw, 32, 0x1, , , Transmit idle value for N turns between two stream iterations.
ffpg_ch, REG, force, 0x24, rw, 32, 0x1, , , Force set/reset and current state values. Intended for initialization.
#Block instances table definition
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x1000, OneWire master
spi_master, spi_master, registers, 0x2000, WB SPI master
csr, ffpg_csr, registers, 0x10000, Control/status registers
#Interrupt Controller (INTC) table definition
intc_name, type, reg_name, block_def_name, chained_intc_name, chained_intc_mask, args, description
#Register Roles table definition
reg_role, reg_name, block_def_name, args