ADC FMC board clock synchronization mechanism
The fmc-adc-100m14b4cha board is equipped with an on-board crystal oscillator from Silicon Labs. The Si570 crystal oscillator IC (datasheet) can be programmed via the I2C interface to provide frequencies in the range 10MHz - 1.4GHz. This crystal oscillator drives the clock pins of the ADC chip on-board the mezzanine cards. When using multiple ADC mezzanine cards in a large experimental facility, it may be necessary to make sure the measurements they provide are synchronized. This synchronization can be provided via White Rabbit (WR).
This page contans the specifications and implementation details of the mechanism used to synchronize multiple ADC mezzanine cards with a sub-nanosecond(ns) accuracy.
Functional specification
In order to synchronize two or more ADC mezzanine cards with sub-ns accuracy, the clock synchronization mechanism (CSM) should be perform as follows:
- It is assumed that the ADC FMCs are equipped with an Si570 pre-calibrated from factory to output a 100MHz frequency. Since the WR core offers a clock which is stable to within /-2 ppm, and the output frequency of the Si570 can be changed to within/-3500 ppm simply by changing the values of the RFREQ registers (see datasheet), it is enough to only change one or more of the RFREQ registers whenever the Si570 clock and the White Rabbit clocks are out of sync.
- Upon initialization (FPGA device reset), the CSM will read the RFREQ register of the Si570. This process is performed only once, upon device reset, and considering the previous specification, changes in frequency will be further on made by adjusting the value of RFREQ.
- A dedicated I2C controller will be implemented in hardware to handle reading from and writing to the Si570.
- The CSM will be accessible externally via the Wishbone bus, offering control and status registers (CSRs) accessible to the user. The Wishbone bus in use is the auxiliary WR Wishbone bus, therefore, one will need to read/write through the WR core to access the device.
- In order to comply with the previous specification, the CSM will implement a simple Wishbone slave interface.
- It will not be possible to access the Si570 registers directly through this interface, these are assumed to be controlled exclusively by the CSM.
- Since the WR core is capable of disciplining various external clocks via its internal software PLL, the clock from the Si570 will be input to the WR core and uses timing data from the WR core to adjust the RFREQ registers of the Si570.
- If WR is in sync with an uplink node or is the System Timing Master (thus providing the synchronization based on the high-precision reference clock), the CSM is enabled and tracks the Si570 clock against the WR clock continuously.
- If WR is not in synchronization with the uplink node, the CSM should be disabled and the Si570 frequency left free-running.
Block diagram of the design
Register description
One control and status register (CSMCSR) is envisioned at this moment for the CSM. It will be a byte-sized register; its bits are shown in the table below.
Bit | Name | Description |
7 | CSMEN | Enable/disable CSM operation (1 - enable / 0 - disable) |
6..2 | -- | Not implemented |
1 | WRSYNC | WR clock in sync status bit (1 - WR clock synced to upper node / 0 - WR clock not synced) |
0 | SILOCK | Locked to WR clock status bit (1 - Si570 locked / 0 - not locked) |