ADC FMC board clock synchronization mechanism
The fmc-adc-100m14b4cha board is equipped with an on-board crystal oscillator from Silicon Labs. The Si570 crystal oscillator IC (datasheet) can be programmed via the I2C interface to provide frequencies in the range 10MHz - 1.4GHz. This crystal oscillator drives the clock pins of the ADC chip on-board the mezzanine cards. When using multiple ADC mezzanine cards in a large experimental facility, it may be necessary to make sure the measurements they provide are synchronized. This synchronization can be provided via White Rabbit.
This page contans the specifications and implementation details of the mechanism used to synchronize multiple ADC mezzanine cards with a sub-nanosecond(ns) accuracy.
Functional specification
In order to synchronize two or more ADC mezzanine cards with sub-ns accuracy, the clock synchronization mechanism (CSM) should be perform as follows:
- The CSM will be an autonomous device, there will be no Wishbone-mapped registers available.
- Upon initialization (FPGA device reset), the CSM will read the internal registers of the Si570 and calculate the internal fXTAL frequency of the Si570 (see datasheet). This frequency is stored and used in all further calculations. This process is performed only once, upon device reset.
- Reading and writing to the Si570 is done through the Wishbone-mapped mezzanine I2C interface. The CSM will connect to this interface for accessing the Si570's registers; Wishbone-specific signals will be multiplexed between the Wishbone bus and the CSM. The address decoder already implemented in the design will be used to select between the Wishbone bus and the CSM, with priority given to the Wishbone bus. Thus, when the Wishbone address is that of the I2C mezzanine interface, the Wishbone bus will read/write the Si570's registers; otherwise, the CSM reads/writes the Si570's registers.
- In order to comply with the previous specification, the CSM will implement a simple Wishbone master interface.
- ** If a write is performed to the Si570 via Wishbone, the CSM will re-read the oscillator's configuration and adjust its operation accordingly. That is, in case the oscillator frequency is changed, the CSM will operate according to the new frequency setting.
- If White Rabbit (WR) is present, enabled and synchronized to an uplink node, the CSM is enabled and uses the reference clock the WR core provides to adjust the frequency and phase of the on-board Si570.
- If WR is not present, not enabled or not synchronized, the CSM should be disabled and the Si570 frequency left free-running.
- Given that once the WR core has synchronized to an uplink node, clock synchronization is performed only once every few minutes or more, the CSM will operate in a similar manner. That is, once the Si570 clock signal is synchronized to the WR clock, the CSM will only be enabled once every few minutes.
- A dedicated counter based on the existing PPS signal will be used to count the interval mentioned in the previous requirement. **