Project description
The FmcAdc100M14b4chb is a 4 channel 100MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card) format. The gain can be set by software in three steps: /-50mV,/-0.5V, /-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of/- 5V that is independent on the chosen gain range. To see how this mezzanine can be combined with a carrier and turned into a complete system, see the HDL specifications page.
Top side*
3D
drawing
Bottom
side
Front
panel
Specifications
Parameter | Value |
max. sample rate | 105 MSPS |
bits/sample | 14 bit |
ENOB | 11, 11.5, 11.7 bit (@ /-50mV,/-0.5V, +/-5V range) |
channels | 4 |
connectors | 4 x SMC for signals, 1 x SMC for trigger |
analog bandwidth | 25 MHz. DC-coupled |
input impedance | 1 kOhm / 50 Ohm - software selectable |
gain steps | /-50 mV,/-0.5 V, +/-5 V for full scale |
offset correction range | +/- 5 V for every input voltage range |
max. gain error | +/- 1 % |
SNR | 67.7 dB, 70.8 dB, 72.2 dB (@ /-50mV,/-0.5V, +/-5V range) |
FMC to carrier interface | FMC low pin count connector with internal clock generator / high pin count connector with external clock |
ADC interface | Serial LVDS, 2 pairs for each channel |
Clock [link](https://www.ohwr.org/project/fmc-adc-100m14b4cha/blob/master | )External, from dedicated FMC connector pins, or from programmed on-board generator |
Project documents
Official production documentation: EDMS:
EDA-02063
LHC Equipment name:
CFFIA
Full schematic - PDF
file:
https://www.ohwr.org/307
PCB - PDF file:
https://www.ohwr.org/121
PCB top and bottom side - PDF file:
https://www.ohwr.org/122
ZIP files containing schematic and PCB in Altium Designer format
SCH -
https://www.ohwr.org/127
PCB -
https://www.ohwr.org/126
Informal description of the design - PDF
file:
https://www.ohwr.org/project/fmc-adc-100m14b4cha/uploads/e2a206cec3aae225525e232cf2a41ebb/FmcAdc100M14b4cha_informal_description.pdf
Estimation of the performance of the FmcAdc100M14b4cha with higher input
impedance:
https://www.ohwr.org/project/fmc-adc-100m14b4cha/uploads/ce95c19e5c7183c9e76a6a8229116422/1MOhm.pdf
Simple bill of materials and prices of the truncated versions of the
FmcAdc (reduced capability) - PDF
file:
https://www.ohwr.org/project/fmc-adc-100m14b4cha/uploads/8ea08e17077323b9fef754eca5fcca48/FmcAdc100M14b4cha_simple_BOM_different_variants.pdf
Bill of materials - Excel
file:
https://www.ohwr.org/project/fmc-adc-100m14b4cha/uploads/9c0beb6aa2f8ed64b574f9e4bd160be3/FmcAdc100M14b4cha_bill_of_materials.xls
>Board cost is estimated basing on current relation between
dollar/frank/EURO. The price of the components is dependent on their
quantity requested from the supplier. This estimation is for the amount
of the components sufficient for 10 boards. The higher number of
components, the lower the price.
Current consumption measurements
More about SNR, SINAD and ENOB calculation
Changes for the second version of the PCB
Investigating the distortion source...
Thermal stability measurements
Status
Date | Event |
01-10-2009 | Start working on project |
25-10-2009 | Functional specification written. |
23-11-2009 | Selection of components, waiting for schematic symbols. |
02-12-2009 | Work on the FmcAdc100M14b4ch_a is suppressed, because estimated performance couldn't pass the expectations. |
18-12-2009 | Specification and schematic of new version has been added. |
22-01-2010 | FmcAdc100M14b4cha upgrade. Design revised and modified, better parameters expected. |
10-02-2010 | New design made with 3 input ranges and programmable offset. Need to finalise local clock circuit before PCB layout can start. |
24-02-2010 | Draft PCB layout done. Design document being written. Design review planned for 2 March. |
02-03-2010 | Design review of schematics done. Review02032010 |
04-03-2010 | Improvements made, responding to design review. Review02032010-improvements |
19-03-2010 | PCB review planned for 24 March 2010. |
24-03-2010 | Design review of PCB layout done. Review24032010 |
25-03-2010 | Small changes involved to the schematic (to make routing easier), PCB partially updated. Review24032010-improvements |
29-03-2010 | PCB updated. Waiting for Design Office's review. |
06-04-2010 | 12 PCBs ordered. 3 will be mounted for prototyping. |
12-04-2010 | For availability reasons two resistor values need to be modified (120 |
06-05-2010 | 3 cards assembled, SMC connectors ordered but not yet available. |
28-05-2010 | SMC connectors given to workshop. Boards look really nice. |
09-06-2010 | 3 assembled boards received. |
12-07-2010 | One board plugged in on Xilinx development kit and powered. Debugging start. |
13-07-2010 | Two channels working! Limited by Xilinx development kit clock connections. |
30-07-2010 | Current consumption has been measured, document is now available on the wiki. |
30-07-2010 | Changes for the second version of the PCB documented, mainly to solve thermal problems with regulators. Required change of DC/DC converter and inductor. |
30-07-2010 | ENOB & SNR measured: >11 bits in all ranges. |
03-08-2010 | First harmonic distortion measurements made. Needs further investigation as with -60dB is higher than expected. |
03-09-2010 | The distortion source has been found. For further information go to Investigating the distortion source... |
03-09-2010 | Thermal stability measurements made. |
03-09-2010 | Frequency response of the anti-aliasing filter will be verified and possibly corrected. Needs development of software that shows frequency response. |
07-09-2010 | Both I2C buses are working. Accessing memory, setting the sampling frequency and making temperature measurements are now possible. |
08-09-2010 | Issue with linearity in the 30-90 kHz region caused by offset compensation circuit being investigated. |
20-09-2010 | The schematic has been updated. All the differences for the second version are given here :PDF |
29-09-2010 | Updates to PCB made (EDA-02063-V2). Ten boards ordered. Designer left CERN. |
22-10-2010 | Found inconsistencies in BOM. Requires modifications to schematics and production files. |
Useful references
-
Fundamentals of Sampled Data Systems - Overview, Analog
Devices
- From EETimes Europe
-
ADC
Tutorials,
Analog Devices
- From Data Converter Tutorials, Analog Devices
- Optimizing SAR ADC performance by proper PCB layout (recommendations may be used in a future version of the design).
- Seven Steps to Successful Analog-to-Digital Signal Conversion (Noise calculation for proper signal conditioning) - Understand how to balance gain blocks and noise, 2010, R. Moghimi, Analog Devices.
- Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor, W. Kester, Analog Devices
Maciej Firmiarz, Erik van der Bij - 25 October 2010