hdl: further sanitise resets and switch the core to using synchronous resets (safer, easier to meet timing)

sim: Introduction of new, simpler testbench for FMC-ADC core, without any SPEC or SVEC specific details

hdl: fix bug where newly-arriving triggers could cause trigger delay logic to reset while counting for previous trigger

hdl: add bit to clear last trigger status, and prevent trigger status from updating when not in acquisition

hdl: removed carrier one-wire master (now handled by WR PTP core), introduced SPI Flash interface for WR PTP core, migrated all carrier HDL to 62.5MHz clock (FMC-ADC and DMA datapath still on 125MHz)

hdl: integrated WR PTP core (SPEC only for now), tested, works, need to review calibration procedure

hdl: modify trigger tag data to include metavalue (0xACCE55) and also reorder the trigger tag seconds field to make it more readable

The new trigger logic allows for logical OR'ing of all trigger sources, by means
of the new "trigger enable" register. For each trigger the "mask" of the trigger source(s)
is reflected in the "trigger status" register and it is also stored in the data stream
together with the trigger time tag.

Furthermore, the previously used glitch filter has been removed, in favor of a comparator module
with optional hysteresis. This approach makes the internal trigger logic more responsible,
versatile and intuitive to the user.

The SPEC testbench has been updated to test these new features. It is still far from perfect though,
see also issue #1726.

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>