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FMC ADC 100M 14b 4cha
Commit 290c1c04 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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update WR support to wrpc-v4.2, WIP

parent ffbb4150
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.gitmodules
View file @ 290c1c04
......@@ -12,4 +12,7 @@
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git@ohwr.org:hdl-core-lib/wr-cores.git
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
etherbone-core @ 84894459
Subproject commit 8489445985ff2afe6c72712014a92a271869f20a
wr-cores @ 69cc4cc3
Subproject commit f3437dd82dd2267c63f3df341daac8972184cd9e
Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 290c1c04
This diff is collapsed.
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 290c1c04
......@@ -32,8 +32,8 @@ NET "SFP_TXP_O" LOC = B16;
NET "SFP_TXP_O" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_B" LOC = C17;
NET "SFP_MOD_DEF1_B" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_B" LOC = G15;
NET "SFP_MOD_DEF0_B" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_I" LOC = G15;
NET "SFP_MOD_DEF0_I" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_B" LOC = G16;
NET "SFP_MOD_DEF2_B" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_B" LOC = H14;
......@@ -540,6 +540,8 @@ NET "UART_RXD_I" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
NET "BUTTON1_N_I" LOC = C22;
NET "BUTTON1_N_I" IOSTANDARD = "LVCMOS18";
#NET "AUX_BUTTONS_I[0]" LOC = C22;
#NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
#NET "AUX_BUTTONS_I[1]" LOC = D21;
......@@ -600,10 +602,10 @@ TIMESPEC TS_adc_dco_n_i = PERIOD "adc_dco_n_i" 2.5 ns HIGH 50%;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
#TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
NET "clk_125m_pllref" TNM_NET = clk_125m_pllref;
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
TIMESPEC TS_crossdomain_01 = FROM "clk_125m_pllref" TO "sys_clk_62_5" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_02 = FROM "sys_clk_62_5" TO "clk_125m_pllref" 4ns DATAPATHONLY;
NET "ddr_clk_buf" TNM_NET = ddr_clk;
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
TIMESPEC TS_sys_to_drr_cross = FROM "sys_clk_62_5" TO "ddr_clk" 16ns DATAPATHONLY;
#===============================================================================
# False Path
......@@ -625,4 +627,4 @@ NET "cmp_powerup_reset/master_rstn" TIG;
# Async reset inputs to reset synchroniser
NET "sys_clk_pll_locked" TIG;
NET "button1_n_i" TIG;
hdl/spec/syn/Manifest.py
View file @ 290c1c04
......@@ -8,19 +8,21 @@ syn_top = "spec_top_fmc_adc_100Ms"
syn_project = "spec_fmc_adc_100Ms.xise"
syn_tool = "ise"
files = ["wrc.ram",
"../spec_top_fmc_adc_100Ms.ucf"]
files = [
"../spec_top_fmc_adc_100Ms.ucf",
modules = {
"local" : [
"../rtl",
"../../adc/rtl",
"../../ip_cores/wr-cores/board/common",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
......
hdl/spec/testbench/top/Manifest.py
View file @ 290c1c04
......@@ -13,7 +13,10 @@ files = [
modules = { "local" : [ "gn4124_bfm",
"../../rtl",
"../../../adc/rtl",
"../../../ip_cores/wr-cores/board/common",
"../../../ip_cores/wr-cores",
"../../../ip_cores/general-cores",
"../../../ip_cores/etherbone-core",
"../../../ip_cores/ddr3-sp6-core",
"../../../ip_cores/gn4124-core" ]};
......
hdl/spec/testbench/top/main.sv
View file @ 290c1c04
......@@ -12,6 +12,11 @@ module main;
reg clk_125m_pllref_p = 0;
reg clk_125m_pllref_n = 1;
reg clk_125m_gtp_p = 0;
reg clk_125m_gtp_n = 1;
reg clk_20m_vcxo = 0;
reg rst_n = 0;
reg adc0_dco = 0;
reg adc0_fr = 1'b0;
......@@ -25,6 +30,9 @@ module main;
always #1.25ns adc0_dco <= ~adc0_dco;
always #4ns clk_125m_pllref_p <= ~clk_125m_pllref_p;
always #4ns clk_125m_pllref_n <= ~clk_125m_pllref_n;
always #4ns clk_125m_gtp_p <= ~clk_125m_gtp_p;
always #4ns clk_125m_gtp_n <= ~clk_125m_gtp_n;
always #25ns clk_20m_vcxo <= ~clk_20m_vcxo;
IGN4124PCIMaster I_Gennum ();
......@@ -41,11 +49,16 @@ module main;
spec_top_fmc_adc_100Ms
#(
.g_simulation("TRUE"),
.g_simulation(1),
.g_wrpc_initf("../../../ip_cores/wr-cores/bin/wrpc/wrc_phy8_sim.bram"),
.g_calib_soft_ip("FALSE")
) DUT (
.button1_n_i(1'b1),
.clk_20m_vcxo_i(clk_20m_vcxo),
.clk_125m_pllref_p_i(clk_125m_pllref_p),
.clk_125m_pllref_n_i(clk_125m_pllref_n),
.clk_125m_gtp_p_i(clk_125m_gtp_p),
.clk_125m_gtp_n_i(clk_125m_gtp_n),
.adc0_ext_trigger_p_i(ext_trig),
.adc0_ext_trigger_n_i(~ext_trig),
.adc0_dco_p_i(adc0_dco),
......@@ -166,11 +179,16 @@ module main;
//@(posedge DUT.sys_clk_pll_locked);
#5us;
#15us;
acc.read(0, val);
$display("ID: %x", val);
// FMC software reset
acc.write('h120c, 'h00000001);
#1us;
acc.write('h120c, 'h00000000);
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); // status
$display("STATUS: %x", val);
......@@ -273,7 +291,7 @@ module main;
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY, 3);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000002);
......
hdl/spec/testbench/top/run.do
View file @ 290c1c04
......@@ -3,6 +3,6 @@ set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 50us
run 70us
wave zoomfull
radix -hexadecimal
hdl/spec/testbench/top/wave.do
View file @ 290c1c04
......@@ -63,8 +63,9 @@ add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stb_t
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
#add wave -noupdate -group Top /main/DUT/clk20_vcxo_i
add wave -noupdate -group Top /main/DUT/clk_20m_vcxo_i
add wave -noupdate -group Top /main/DUT/clk_125m_pllref*
add wave -noupdate -group Top /main/DUT/clk_125m_gtp*
add wave -noupdate -group Top /main/DUT/powerup*
add wave -noupdate -group Top /main/DUT/pll25dac_sync_n_o
add wave -noupdate -group Top /main/DUT/pll20dac_sync_n_o
......@@ -148,10 +149,10 @@ add wave -noupdate -group Top /main/DUT/adc0_one_wire_b
add wave -noupdate -group Top /main/DUT/fmc0_prsnt_m2c_n_i
add wave -noupdate -group Top /main/DUT/fmc0_sys_scl_b
add wave -noupdate -group Top /main/DUT/fmc0_sys_sda_b
add wave -noupdate -group Top /main/DUT/sys_clk_in
add wave -noupdate -group Top /main/DUT/sys_clk_125_buf
add wave -noupdate -group Top /main/DUT/sys_clk_62_5
add wave -noupdate -group Top /main/DUT/sys_clk_125
add wave -noupdate -group Top /main/DUT/sys_clk_fb
add wave -noupdate -group Top /main/DUT/clk_dmtd
add wave -noupdate -group Top /main/DUT/clk_dmtd_locked
add wave -noupdate -group Top /main/DUT/sys_clk_pll_locked
add wave -noupdate -group Top /main/DUT/ddr_clk
add wave -noupdate -group Top /main/DUT/ddr_clk_buf
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 290c1c04
......@@ -58,8 +58,7 @@ use work.wr_xilinx_pkg.all;
entity svec_top_fmc_adc_100Ms is
generic(
g_simulation_int : integer := 0; -- used in newer modules such as xwr_core
g_SIMULATION : string := "FALSE"; -- kept for backwards compatibility
g_simulation : integer := 0;
g_multishot_ram_size : natural := 8192;
g_CALIB_SOFT_IP : string := "TRUE");
port
......@@ -345,6 +344,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is
xdone_o : out std_logic);
end component;
-- Conversion of g_simulation to boolean
constant c_SIMULATION_BOOL : boolean := f_int2bool(g_simulation);
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
......@@ -894,7 +896,7 @@ begin
---------------------
U_GTP : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation_int,
g_simulation => g_simulation,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map (
......@@ -975,9 +977,8 @@ begin
U_WR_CORE : xwr_core
generic map (
g_simulation => g_simulation_int,
g_dpram_initf => "")
-- g_dpram_initf => "wrc.ram")
g_simulation => g_simulation,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram")
port map (
clk_sys_i => sys_clk_62_5,
clk_dmtd_i => clk_dmtd,
......@@ -1342,7 +1343,7 @@ begin
generic map(
g_BANK_PORT_SELECT => "SVEC_BANK4_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_SIMULATION => c_SIMULATION_BOOL,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
......@@ -1496,7 +1497,7 @@ begin
generic map(
g_BANK_PORT_SELECT => "SVEC_BANK5_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_SIMULATION => c_SIMULATION_BOOL,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
......
hdl/svec/syn/Manifest.py
View file @ 290c1c04
......@@ -8,7 +8,9 @@ syn_top = "svec_top_fmc_adc_100Ms"
syn_project = "svec_fmc_adc_100Ms.xise"
syn_tool = "ise"
files = ["../svec_top_fmc_adc_100Ms.ucf"]
files = [
"../svec_top_fmc_adc_100Ms.ucf",
]
modules = {
"local" : [
......
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