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FMC ADC 100M 14b 4cha
Commit d805e900 authored by Paul PERONNARD's avatar Paul PERONNARD
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use of DS48E2 for gain/offset

parent 87c3aa7c
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Showing with 4455 additions and 182 deletions
hdl/cheby/fmc_adc_100Ms_channel_regs.vhd
View file @ d805e900
......@@ -157,7 +157,7 @@ begin
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
calib_gain_reg <= "0000000000000000";
calib_gain_reg <= "1000000000000000";
calib_offset_reg <= "0000000000000000";
calib_wack <= '0';
else
......@@ -175,7 +175,7 @@ begin
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sat_val_reg <= "000000000000000";
sat_val_reg <= (others => '1');
sat_wack <= '0';
else
if sat_wreq = '1' then
......
hdl/platform/xilinx/ultrascale/ltc2174.sv
View file @ d805e900
......@@ -72,8 +72,8 @@ module ltc2174_2l16b_us_receiver #(
wire frame_dly;
logic [6:0] serdes_rst_seq = 7'b1111111;
wire serdes_rst;
(* syn_keep = "true", mark_debug = "true" *) wire [7:0] serdes_parallel_outa[0:3];
(* syn_keep = "true", mark_debug = "true" *) wire [7:0] serdes_parallel_outb[0:3];
wire [7:0] serdes_parallel_outa[0:3];
wire [7:0] serdes_parallel_outb[0:3];
wire [7:0] serdes_parallel_frame;
wire mmcm_clkfbout, mmcm_locked, mmcm_clkfbin;
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ d805e900
......@@ -33,7 +33,7 @@ entity fmc_adc_100Ms_core is
generic (
g_MULTISHOT_RAM_SIZE : natural := 2048;
-- FPGA family SPARTAN6, ULTRASCALE
g_FPGA_DEVICE : string := "SPARTAN6";
g_FPGA_DEVICE : string := "ULTRASCALE";
-- DDR Bus type
g_DDR_AXI_STREAM : boolean := false;
-- Only used on Xilinx Spartan6 FPGAs
......@@ -349,6 +349,34 @@ architecture rtl of fmc_adc_100Ms_core is
signal wb_channel_in : t_fmc_adc_channel_wbin_array;
signal wb_channel_out : t_fmc_adc_channel_wbout_array;
component ltc2174_2l16b_us_receiver
generic(
FPGA_TECHNOLOGY: string := "ULTRASCALE_PLUS";
IODELAY_GROUP:string := "adc_delay_group";
USE_PLL: natural := 1;
C_M_AXIS_TDATA_WIDTH: natural := 64
);
port (
adc_dco_p_i: in std_logic;
adc_dco_n_i: in std_logic;
adc_fr_p_i: in std_logic;
adc_fr_n_i: in std_logic;
adc_outa_p_i: in std_logic_vector(3 downto 0);
adc_outa_n_i: in std_logic_vector(3 downto 0);
adc_outb_p_i: in std_logic_vector(3 downto 0);
adc_outb_n_i: in std_logic_vector(3 downto 0);
serdes_calib_i: in std_logic;
serdes_locked_o: out std_logic;
serdes_synced_o: out std_logic;
adc_data_o: out std_logic_vector(63 downto 0);
adc_clk_o: out std_logic;
m_axis_tvalid_o: out std_logic;
m_axis_tdata_o: out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_tstrb_o: out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_tready_i: in std_logic
);
end component;
begin
------------------------------------------------------------------------------
......@@ -448,29 +476,29 @@ begin
d_i => csr_regout.ctl_serdes_calib,
q_o => serdes_calib_sync);
gen_adc_spartan_receiver: if g_FPGA_DEVICE = "SPARTAN6" generate
cmp_adc_serdes : entity work.ltc2174_2l16b_receiver
generic map (
g_USE_PLL => g_SPARTAN6_USE_PLL)
port map (
adc_dco_p_i => adc_dco_p_i,
adc_dco_n_i => adc_dco_n_i,
adc_fr_p_i => adc_fr_p_i,
adc_fr_n_i => adc_fr_n_i,
adc_outa_p_i => adc_outa_p_i,
adc_outa_n_i => adc_outa_n_i,
adc_outb_p_i => adc_outb_p_i,
adc_outb_n_i => adc_outb_n_i,
serdes_arst_i => serdes_arst,
serdes_calib_i => serdes_calib_sync,
serdes_locked_o => serdes_locked,
serdes_synced_o => serdes_synced,
adc_data_o => serdes_out_data,
adc_clk_o => fs_clk);
end generate;
--gen_adc_spartan_receiver: if g_FPGA_DEVICE = "SPARTAN6" generate
--cmp_adc_serdes : entity work.ltc2174_2l16b_receiver
-- generic map (
-- g_USE_PLL => g_SPARTAN6_USE_PLL)
-- port map (
-- adc_dco_p_i => adc_dco_p_i,
-- adc_dco_n_i => adc_dco_n_i,
-- adc_fr_p_i => adc_fr_p_i,
-- adc_fr_n_i => adc_fr_n_i,
-- adc_outa_p_i => adc_outa_p_i,
-- adc_outa_n_i => adc_outa_n_i,
-- adc_outb_p_i => adc_outb_p_i,
-- adc_outb_n_i => adc_outb_n_i,
-- serdes_arst_i => serdes_arst,
-- serdes_calib_i => serdes_calib_sync,
-- serdes_locked_o => serdes_locked,
-- serdes_synced_o => serdes_synced,
-- adc_data_o => serdes_out_data,
-- adc_clk_o => fs_clk);
--end generate;
gen_adc_ultrascale_receiver: if g_FPGA_DEVICE = "ULTRASCALE" generate
cmp_adc_serdes : entity work.ltc2174_2l16b_us_receiver
cmp_adc_serdes : ltc2174_2l16b_us_receiver
port map (
adc_dco_p_i => adc_dco_p_i,
adc_dco_n_i => adc_dco_n_i,
......@@ -484,7 +512,11 @@ begin
serdes_locked_o => serdes_locked,
serdes_synced_o => serdes_synced,
adc_data_o => serdes_out_data,
adc_clk_o => fs_clk);
adc_clk_o => fs_clk,
m_axis_tvalid_o => open,
m_axis_tdata_o => open,
m_axis_tstrb_o => open,
m_axis_tready_i => '0');
end generate;
cmp_serdes_synced_sync : gc_sync
......@@ -1623,30 +1655,30 @@ begin
-- end if;
-- end process;
gen_wb_ctrl_ddr: if not g_DDR_AXI_STREAM generate
p_wb_ddr_fifo_input : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
wb_ddr_fifo_din <= (others => '0');
wb_ddr_fifo_wr_en <= '0';
else
if single_shot = '1' then
if acq_in_trig_tag = '1' then
wb_ddr_fifo_din <= '0' & trig_tag_data;
wb_ddr_fifo_wr_en <= acq_in_trig_tag;
else
wb_ddr_fifo_din <= acq_trig & sync_fifo_dout(63 downto 0); -- trigger + data
wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid;
end if;
p_wb_ddr_fifo_input : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
wb_ddr_fifo_din <= (others => '0');
wb_ddr_fifo_wr_en <= '0';
else
if single_shot = '1' then
if acq_in_trig_tag = '1' then
wb_ddr_fifo_din <= '0' & trig_tag_data;
wb_ddr_fifo_wr_en <= acq_in_trig_tag;
else
wb_ddr_fifo_din <= '0' & dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid;
wb_ddr_fifo_din <= acq_trig & sync_fifo_dout(63 downto 0); -- trigger + data
wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid;
end if;
else
wb_ddr_fifo_din <= '0' & dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid;
end if;
end if;
end process p_wb_ddr_fifo_input;
end if;
end process p_wb_ddr_fifo_input;
gen_wb_ctrl_ddr: if not g_DDR_AXI_STREAM generate
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_skidpad_stall);
end generate;
......@@ -1701,35 +1733,35 @@ begin
-- Convert to 32-bit word addressing for Wishbone
wb_ddr_skidpad_adr_in <= std_logic_vector(ram_addr_cnt);
inst_skidpad: entity work.wb_skidpad2
generic map (
g_adrbits => ram_addr_cnt'length,
g_datbits => 64
)
port map (
clk_i => wb_ddr_clk_i,
rst_n_i => wb_ddr_rst_n_i,
stb_i => wb_ddr_skidpad_stb_in,
adr_i => wb_ddr_skidpad_adr_in,
dat_i => wb_ddr_fifo_dout2,
sel_i => (others => '1'),
we_i => '1',
stall_o => wb_ddr_skidpad_stall,
stb_o => wb_ddr_skidpad_stb_out,
adr_o => wb_ddr_skidpad_adr_out,
dat_o => wb_ddr_master_o.dat,
sel_o => open,
we_o => open,
stall_i => wb_ddr_master_i.stall
);
wb_ddr_master_o.we <= '1';
wb_ddr_master_o.sel <= X"FF";
wb_ddr_master_o.cyc <= dpram_valid or wb_ddr_skidpad_stb_out when acq_fsm_state = "001" else '1';
wb_ddr_master_o.stb <= wb_ddr_skidpad_stb_out;
wb_ddr_master_o.adr <= "00" & wb_ddr_skidpad_adr_out & "0";
inst_skidpad: entity work.wb_skidpad2
generic map (
g_adrbits => ram_addr_cnt'length,
g_datbits => 64
)
port map (
clk_i => wb_ddr_clk_i,
rst_n_i => wb_ddr_rst_n_i,
stb_i => wb_ddr_skidpad_stb_in,
adr_i => wb_ddr_skidpad_adr_in,
dat_i => wb_ddr_fifo_dout2,
sel_i => (others => '1'),
we_i => '1',
stall_o => wb_ddr_skidpad_stall,
stb_o => wb_ddr_skidpad_stb_out,
adr_o => wb_ddr_skidpad_adr_out,
dat_o => wb_ddr_master_o.dat,
sel_o => open,
we_o => open,
stall_i => wb_ddr_master_i.stall
);
wb_ddr_master_o.we <= '1';
wb_ddr_master_o.sel <= X"FF";
wb_ddr_master_o.cyc <= dpram_valid or wb_ddr_skidpad_stb_out when acq_fsm_state = "001" else '1';
wb_ddr_master_o.stb <= wb_ddr_skidpad_stb_out;
wb_ddr_master_o.adr <= "00" & wb_ddr_skidpad_adr_out & "0";
-- Store trigger DDR address (byte address)
p_trig_addr : process (wb_ddr_clk_i)
begin
......
hdl/rtl/offset_gain_s.vhd
View file @ d805e900
This diff is collapsed.
hdl/syn/spexi7u_ref_design/spexi7u_ref_fmc_adc_100Ms.xpr
View file @ d805e900
......@@ -91,6 +91,19 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../top/spexi7u_ref_design/modules_axi_mpsoc_int_gen_mpsoc_int_gen.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../top/spexi7u_ref_design/skidbuffer.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v">
<FileInfo SFType="VHeader">
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -126,6 +139,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../top/spexi7u_ref_design/wbm2axisp.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../platform/xilinx/ultrascale/ltc2174.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -439,12 +459,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../top/spexi7u_ref_design/modules_axi_mpsoc_int_gen_mpsoc_int_gen.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/pxie_bd/pxie_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -574,15 +588,15 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="pxie_bd_axi_fmc_adc_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pxie_bd_axi_fmc_adc_0_0" RelGenDir="$PGENDIR/pxie_bd_axi_fmc_adc_0_0">
<FileSet Name="pxie_bd_mpsoc_int_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pxie_bd_mpsoc_int_gen_0_0" RelGenDir="$PGENDIR/pxie_bd_mpsoc_int_gen_0_0">
<Config>
<Option Name="TopModule" Val="pxie_bd_axi_fmc_adc_0_0"/>
<Option Name="TopModule" Val="pxie_bd_mpsoc_int_gen_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pxie_bd_mpsoc_int_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pxie_bd_mpsoc_int_gen_0_0" RelGenDir="$PGENDIR/pxie_bd_mpsoc_int_gen_0_0">
<FileSet Name="pxie_bd_axi_fmc_adc_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pxie_bd_axi_fmc_adc_0_0" RelGenDir="$PGENDIR/pxie_bd_axi_fmc_adc_0_0">
<Config>
<Option Name="TopModule" Val="pxie_bd_mpsoc_int_gen_0_0"/>
<Option Name="TopModule" Val="pxie_bd_axi_fmc_adc_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
......@@ -616,7 +630,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pxie_bd_axi_fmc_adc_0_0_synth_1" Type="Ft3:Synth" SrcSet="pxie_bd_axi_fmc_adc_0_0" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_axi_fmc_adc_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pxie_bd_axi_fmc_adc_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_synth_1">
<Run Id="pxie_bd_mpsoc_int_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="pxie_bd_mpsoc_int_gen_0_0" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_mpsoc_int_gen_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pxie_bd_mpsoc_int_gen_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
......@@ -626,9 +640,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pxie_bd_mpsoc_int_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="pxie_bd_mpsoc_int_gen_0_0" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_mpsoc_int_gen_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pxie_bd_mpsoc_int_gen_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_synth_1">
<Run Id="pxie_bd_axi_fmc_adc_0_0_synth_1" Type="Ft3:Synth" SrcSet="pxie_bd_axi_fmc_adc_0_0" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_axi_fmc_adc_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pxie_bd_axi_fmc_adc_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
......@@ -654,7 +670,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pxie_bd_axi_fmc_adc_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_axi_fmc_adc_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pxie_bd_axi_fmc_adc_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_impl_1">
<Run Id="pxie_bd_mpsoc_int_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_mpsoc_int_gen_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pxie_bd_mpsoc_int_gen_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
......@@ -671,9 +687,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pxie_bd_mpsoc_int_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_mpsoc_int_gen_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pxie_bd_mpsoc_int_gen_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_mpsoc_int_gen_0_0_impl_1">
<Run Id="pxie_bd_axi_fmc_adc_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7cg-ffvf1517-1-e" ConstrsSet="pxie_bd_axi_fmc_adc_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pxie_bd_axi_fmc_adc_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pxie_bd_axi_fmc_adc_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......
hdl/testbench/spexi7u_ref_design/compile.do
View file @ d805e900
......@@ -5,6 +5,12 @@ vmap secureip c:/Xilinx/simlib/aldec/secureip
vlib work
vlog -work work -dbg ../include/glbl.v
vcom -work work -dbg ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vlog -work work -dbg -l unisims_ver -l secureip ../../platform/xilinx/ultrascale/ltc2174.sv
vlog -work work -dbg tb_iserdes.sv
vcom -work work ../../rtl/offset_gain_s.vhd
vcom -work work ../../rtl/timetag_core.vhd
vcom -work work ../../rtl/fmc_adc_100Ms_core_pkg.vhd
vlog -work work -dbg ../include/glbl.v
hdl/testbench/spexi7u_ref_design/compile_core.do 0 → 100644
View file @ d805e900
vlib work
vcom -work work ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
# -packagevhdlsv for aldec, -mixedsvvh for modelsim
vcom -mixedsvvh -work work ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom -work work ../../rtl/fmc_adc_100Ms_core_pkg.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_sync.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_negedge.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_posedge.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom -work work ../../ip_cores/general-cores/modules/common/gc_comparator.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom -work work ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom -work work ../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd
vcom -work work ../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd
vcom -work work ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom -work work ../../cheby/fmc_adc_100Ms_csr.vhd
#vcom -work work ../../platform/xilinx/spartan6/ltc2174_2l16b_receiver.vhd
vlog -work work -l unisims_ver -l secureip ../../platform/xilinx/ultrascale/ltc2174.sv
vcom -work work ../../cheby/timetag_core_regs.vhd
vcom -work work ../../cheby/fmc_adc_100Ms_channel_regs.vhd
vcom -work work ../../cheby/fmc_adc_aux_trigin.vhd
vcom -work work ../../cheby/fmc_adc_aux_trigout.vhd
vcom -work work ../../rtl/timetag_core.vhd
vcom -work work ../../rtl/offset_gain_s.vhd
vcom -work work ../../rtl/fmc_adc_100Ms_core.vhd
vlog -work work ../include/glbl.v
vlog -work work +incdir+../include+../../ip_cores/general-cores/sim tb_core.sv
hdl/testbench/spexi7u_ref_design/compile_iserdes.do 0 → 100644
View file @ d805e900
vmap unisims_ver c:/Xilinx/simlib/aldec/unisims_ver
vmap unimacro_ver c:/Xilinx/simlib/aldec/unimacro_ver
vmap secureip c:/Xilinx/simlib/aldec/secureip
vlib work
vlog -work work -dbg ../include/glbl.v
vlog -work work -dbg -l unisims_ver -l secureip ../../platform/xilinx/ultrascale/ltc2174.sv
vlog -work work -dbg tb_iserdes.sv
hdl/testbench/spexi7u_ref_design/core.awc 0 → 100644
View file @ d805e900
<?xml version="1.0" encoding="UTF-8"?>
<document type="awc" version="2">
<waveform>
<datasets>
<dataset alias="sim" file="dataset.asdb" id="0" uniqueid="1701875776654"/>
</datasets>
<browser type="events"/>
<view active="true">
<cursors>
<cursor name="Default cursor" id="-1" time="0fs+0" lock="0" tip="1"/>
<active name="Default cursor" time="0fs+0"/>
</cursors>
<signalspart>
<signal name="/tb_core/rst_n" aliasid="0"/>
<signal name="/tb_core/clk_sys" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/offset_i" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/gain_i" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/sat_i" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/data_i" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/data_o" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/rst" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/data_offset" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/gain" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/product_t" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/product48" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/product" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/pos_sat" aliasid="0"/>
<signal name="/tb_core/DUT/l_offset_gain_calibr__0/cmp_offset_gain_calibr/neg_sat" aliasid="0"/>
<signal name="/tb_core/DUT/acq_fsm_state" aliasid="0"/>
<signal name="/tb_core/DUT/wb_csr_in" aliasid="0"/>
<signal name="/tb_core/DUT/wb_csr_out" aliasid="0"/>
<signal name="/tb_core/DUT/channel_regin(1)" aliasid="0"/>
<signal name="/tb_core/DUT/wb_channel_out" aliasid="0"/>
</signalspart>
<firstvisiblesignal number="0"/>
<timesynchronization value="1"/>
<cursorssynchronization value="1"/>
<time beginvisible="0fs" endvisible="0fs"/>
</view>
<bookmarks/>
<time beginvisible="0fs" endvisible="1050ps"/>
<timeunit name="auto"/>
<cursors>
<cursor name="Default cursor" id="-1" time="354ps" lock="0" tip="1"/>
<active name="Default cursor" time="354ps"/>
</cursors>
<hierarchy_depth value="0"/>
</waveform>
</document>
hdl/testbench/spexi7u_ref_design/core.mpf 0 → 100644
View file @ d805e900
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/spexi7u_ref_design/core.rdsn 0 → 100644
View file @ d805e900
<?xml version="1.0" encoding="UTF-8"?>
<riviera-design>
<version value="2023.10.106.9105"/>
<configurations>
<configuration name="optimized"/>
<configuration name="debug"/>
</configurations>
<properties>
<configuration name="debug">
<compilation>
<cpp>
<generate-debug-information value="true"/>
</cpp>
<verilog>
<generate-debug-information value="true"/>
<pli-applications value="C:/Aldec/Riviera-PRO-2023.10-x64/bin/systf.dll;"/>
</verilog>
<vhdl>
<generate-debug-information value="true"/>
</vhdl>
</compilation>
<global>
<intermediate-dir value="./debug"/>
</global>
<library>
<active-library value="work"/>
</library>
<simulation>
<general>
<enable-debug value="true"/>
</general>
<verilog>
<pli-applications value="1|C:/Aldec/Riviera-PRO-2023.10-x64/bin/systf.dll;"/>
</verilog>
</simulation>
</configuration>
<configuration name="optimized">
<compilation>
<cpp>
<generate-debug-information value="false"/>
</cpp>
<verilog>
<generate-debug-information value="false"/>
</verilog>
<vhdl>
<generate-debug-information value="false"/>
</vhdl>
</compilation>
<global>
<intermediate-dir value="./optimized"/>
</global>
</configuration>
</properties>
<structure>
<file path="compile_core.do"/>
<file path="tb_core.sv"/>
<file path="sim_core.do"/>
<file path="core.awc"/>
</structure>
<dependencies/>
</riviera-design>
hdl/testbench/spexi7u_ref_design/tb_iserdes.rwsp → hdl/testbench/spexi7u_ref_design/fmc-adc-100m14b4cha.rwsp
View file @ d805e900
......@@ -2,18 +2,24 @@
<!DOCTYPE riviera-workspace>
<riviera-workspace>
<version value="2023.10.106.9105"/>
<active-design name="tb_iserdes"/>
<active-design name="core"/>
<active-configuration name="debug"/>
<designs>
<design path="tb_iserdes.rdsn"/>
<design path="iserdes.rdsn"/>
<design path="main.rdsn"/>
<design path="core.rdsn"/>
</designs>
<dependencies/>
<configurations>
<configuration name="optimized">
<design name="tb_iserdes" configuration="optimized"/>
<design name="core" configuration="optimized"/>
<design name="iserdes" configuration="optimized"/>
<design name="main" configuration="optimized"/>
</configuration>
<configuration name="debug">
<design name="tb_iserdes" configuration="debug"/>
<design name="core" configuration="debug"/>
<design name="iserdes" configuration="debug"/>
<design name="main" configuration="debug"/>
</configuration>
</configurations>
</riviera-workspace>
hdl/testbench/spexi7u_ref_design/fmc-adc-100m14b4cha.rwsp.user 0 → 100644
View file @ d805e900
<?xml version="1.0" encoding="UTF-8"?>
<riviera-workspace-user>
<plugins>
<plugin name="simulation_controller">
<settings>
<breakpoints/>
</settings>
</plugin>
<plugin name="vsimgui">
<settings>
<run_for_time time="100ns"/>
</settings>
</plugin>
</plugins>
<documents>
<document file="compile_core.do" is_docked="1" type="macro">
<settings>
<cursor column="0" line="60"/>
<code_analysis enabled="1"/>
</settings>
</document>
<document file="tb_core.sv" is_docked="1" type="systemverilog">
<settings>
<cursor column="8" line="152"/>
<code_analysis enabled="1"/>
</settings>
</document>
<document file="sim_core.do" is_docked="1" type="macro">
<settings>
<cursor column="0" line="4"/>
<code_analysis enabled="1"/>
</settings>
</document>
<document file="core.awc" is_docked="1" type="awc"/>
</documents>
</riviera-workspace-user>
hdl/testbench/spexi7u_ref_design/tb_iserdes.rdsn → hdl/testbench/spexi7u_ref_design/iserdes.rdsn
View file @ d805e900
......@@ -61,13 +61,9 @@
<file path="work/work.lib"/>
</directory>
<file path="tb_iserdes.sv"/>
<file path="compile.do"/>
<file path="compile_iserdes.do"/>
<file path="dataset.asdb"/>
<file path="main.sv"/>
<file path="run.do"/>
<file path="run_ci.do"/>
<file path="sim_iserdes.do"/>
<file path="wave.do"/>
<file path="../../platform/xilinx/ultrascale/ltc2174.sv"/>
<file path="iserdes.awc"/>
</structure>
......
hdl/testbench/spexi7u_ref_design/main.rdsn 0 → 100644
View file @ d805e900
<?xml version="1.0" encoding="UTF-8"?>
<riviera-design>
<version value="2023.10.106.9105"/>
<configurations>
<configuration name="optimized"/>
<configuration name="debug"/>
</configurations>
<properties>
<configuration name="debug">
<compilation>
<cpp>
<generate-debug-information value="true"/>
</cpp>
<verilog>
<generate-debug-information value="true"/>
</verilog>
<vhdl>
<generate-debug-information value="true"/>
</vhdl>
</compilation>
<global>
<intermediate-dir value="./debug"/>
</global>
<library>
<active-library value="main"/>
</library>
<simulation>
<general>
<enable-debug value="true"/>
</general>
</simulation>
</configuration>
<configuration name="optimized">
<compilation>
<cpp>
<generate-debug-information value="false"/>
</cpp>
<verilog>
<generate-debug-information value="false"/>
</verilog>
<vhdl>
<generate-debug-information value="false"/>
</vhdl>
</compilation>
<global>
<intermediate-dir value="./optimized"/>
</global>
</configuration>
</properties>
<structure>
<file path="main.sv"/>
<file path="compile.do"/>
</structure>
<dependencies/>
</riviera-design>
hdl/testbench/spexi7u_ref_design/restart_sim_core.do 0 → 100644
View file @ d805e900
vlog -work work +incdir+../include+../../ip_cores/general-cores/sim tb_core.sv
vopt +acc -suppress 10016 -suppress 8885 -L unisims_ver -L unimacro_ver -L secureip work.tb_core work.glbl -o tb_core_opt
restart -f
run 100us
\ No newline at end of file
hdl/testbench/spexi7u_ref_design/secureip 0 → 100644
View file @ d805e900
QuestaSim-64 vlog 2022.3 Compiler 2022.07 Jul 18 2022
Start time: 14:18:12 on Dec 07,2023
vlog -reportprogress 300 -work work -l unisims_ver -l secureip ../../platform/xilinx/ultrascale/ltc2174.sv
-- Compiling module ltc2174_2l16b_us_receiver
Top level modules:
ltc2174_2l16b_us_receiver
End time: 14:18:12 on Dec 07,2023, Elapsed time: 0:00:00
Errors: 0, Warnings: 0
hdl/testbench/spexi7u_ref_design/sim_core.do 0 → 100644
View file @ d805e900
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#vsim +access +r+w +accb -L unisims_ver -L secureip work.tb_core work.glbl
vopt +acc -suppress 10016 -suppress 8885 -L unisims_ver -L unimacro_ver -L secureip work.tb_core work.glbl -o tb_core_opt
vsim tb_core_opt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave_core.do
view wave
view structure
view signals
radix -hexadecimal
run 400ns
hdl/testbench/spexi7u_ref_design/tb_core.sv 0 → 100644
View file @ d805e900
This diff is collapsed.
hdl/testbench/spexi7u_ref_design/tb_iserdes.rwsp.user
View file @ d805e900
......@@ -21,16 +21,16 @@
</plugin>
</plugins>
<documents>
<document is_docked="1" file="compile.do" type="macro">
<document type="macro" file="compile.do" is_docked="1">
<settings>
<cursor line="8" column="0"/>
<cursor column="0" line="8"/>
<code_analysis enabled="1"/>
</settings>
</document>
<document is_docked="1" file="iserdes.awc" type="awc"/>
<document is_docked="1" file="tb_iserdes.sv" type="systemverilog">
<document type="awc" file="iserdes.awc" is_docked="1"/>
<document type="systemverilog" file="tb_iserdes.sv" is_docked="1">
<settings>
<cursor line="95" column="32"/>
<cursor column="32" line="95"/>
<code_analysis enabled="1"/>
</settings>
</document>
......
hdl/testbench/spexi7u_ref_design/tb_iserdes.sv
View file @ d805e900
......@@ -108,7 +108,7 @@ module tb_iserdes;
adc0_data = adc0_data - 1;
end*/
//#1;
adc0_dat_odd = {4{adc0_data[13]}};
adc0_dat_odd = {4{adc0_data[13]}};
adc0_dat_even = {4{adc0_data[12]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[11]}};
......
hdl/testbench/spexi7u_ref_design/vmap.do 0 → 100644
View file @ d805e900
vmap unisim c:/Xilinx/simlib/unisim
vmap unisims_ver c:/Xilinx/simlib/unisims_ver
vmap unimacro_ver c:/Xilinx/simlib/unimacro_ver
vmap unimacro c:/Xilinx/simlib/unimacro
vmap secureip c:/Xilinx/simlib/secureip
#vmap unisim c:/Xilinx/simlib/aldec/unisim
#vmap unisims_ver c:/Xilinx/simlib/aldec/unisims_ver
#vmap unimacro_ver c:/Xilinx/simlib/aldec/unimacro_ver
#vmap unimacro c:/Xilinx/simlib/aldec/unimacro
#vmap secureip c:/Xilinx/simlib/aldec/secureip
\ No newline at end of file
hdl/testbench/spexi7u_ref_design/wave_core.do 0 → 100644
View file @ d805e900
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_core/DUT/sys_clk_i
add wave -noupdate /tb_core/DUT/sys_rst_n_i
add wave -noupdate /tb_core/DUT/wb_csr_slave_i
add wave -noupdate /tb_core/DUT/wb_csr_slave_o
add wave -noupdate /tb_core/DUT/wb_channel_in(1)
add wave -noupdate /tb_core/DUT/wb_channel_out(1)
add wave -noupdate /tb_core/DUT/wb_csr_in
add wave -noupdate /tb_core/DUT/wb_csr_out
add wave -noupdate /tb_core/DUT/channel_regin
add wave -noupdate /tb_core/DUT/channel_regout
add wave -noupdate /tb_core/DUT/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/offset_i
add wave -noupdate /tb_core/DUT/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/gain_i
add wave -noupdate /tb_core/DUT/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/sat_i
add wave -noupdate /tb_core/DUT/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/data_i
add wave -noupdate /tb_core/DUT/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/data_o
add wave -noupdate /tb_core/DUT/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/product48
add wave -noupdate /tb_core/DUT/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/product
add wave -noupdate /tb_core/DUT/cmp_fmc_adc_100Ms_csr/fmc_adc_ch1_i
add wave -noupdate /tb_core/DUT/cmp_fmc_adc_100Ms_csr/fmc_adc_ch1_o
add wave -noupdate /tb_core/DUT/cmp_fmc_adc_100Ms_csr/fmc_adc_100ms_csr_i
add wave -noupdate /tb_core/DUT/cmp_fmc_adc_100Ms_csr/fmc_adc_100ms_csr_o
add wave -noupdate /tb_core/DUT/gen_adc_ultrascale_receiver/cmp_adc_serdes/serdes_calib_i
add wave -noupdate /tb_core/DUT/gen_adc_ultrascale_receiver/cmp_adc_serdes/serdes_locked_o
add wave -noupdate /tb_core/DUT/gen_adc_ultrascale_receiver/cmp_adc_serdes/serdes_synced_o
add wave -noupdate /tb_core/DUT/gen_adc_ultrascale_receiver/cmp_adc_serdes/nb_psinc
add wave -noupdate /tb_core/DUT/gen_adc_ultrascale_receiver/cmp_adc_serdes/psinc
add wave -noupdate /tb_core/DUT/gen_adc_ultrascale_receiver/cmp_adc_serdes/cal_state
add wave -noupdate /tb_core/DUT/sync_calib_apply
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {95413856 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 693
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {94759455 ps} {95665575 ps}
hdl/top/spexi7u_ref_design/axi_fmc_adc.vhd
View file @ d805e900
This diff is collapsed.
hdl/top/spexi7u_ref_design/modules_axi_mpsoc_int_gen_mpsoc_int_gen.vhd
View file @ d805e900
......@@ -84,7 +84,7 @@ begin
-- AW
S_AXI_awaddr (31 downto 0) <= g_addr;
S_AXI_awaddr (48 downto 32) <= (others => '0');
S_AXI_awaddr (S_AXI_awaddr'left downto 32) <= (others => '0');
-- No burst.
S_AXI_awburst <= "01";
......@@ -111,11 +111,9 @@ begin
-- W
S_AXI_wdata (31 downto 0) <= g_data;
S_AXI_wdata (S_AXI_wdata'left downto 32) <= (others => '0');
S_AXI_wdata <= g_data;
S_AXI_wlast <= '1';
S_AXI_wstrb(3 downto 0) <= "1111";
S_AXI_wstrb(s_AXI_wstrb'left downto 4) <= (others => '0');
process (clk_i)
begin
......@@ -130,7 +128,7 @@ begin
else
case state is
when S_IDLE =>
if irq_i /= "0000" then
if irq_i /= "00000" then
-- Send the write.
S_AXI_awvalid <= '1';
S_AXI_wvalid <= '1';
......@@ -148,7 +146,7 @@ begin
state <= S_DONE;
end if;
when S_DONE =>
if irq_i = "000" then
if irq_i = "00000" then
-- Wait for irq release.
state <= S_IDLE;
end if;
......@@ -157,6 +155,3 @@ begin
end if;
end process;
end arch;
hdl/top/spexi7u_ref_design/skidbuffer.v 0 → 100644
View file @ d805e900
////////////////////////////////////////////////////////////////////////////////
//
// Filename: skidbuffer.v
// {{{
// Project: WB2AXIPSP: bus bridges and other odds and ends
//
// Purpose: A basic SKID buffer.
// {{{
// Skid buffers are required for high throughput AXI code, since the AXI
// specification requires that all outputs be registered. This means
// that, if there are any stall conditions calculated, it will take a clock
// cycle before the stall can be propagated up stream. This means that
// the data will need to be buffered for a cycle until the stall signal
// can make it to the output.
//
// Handling that buffer is the purpose of this core.
//
// On one end of this core, you have the i_valid and i_data inputs to
// connect to your bus interface. There's also a registered o_ready
// signal to signal stalls for the bus interface.
//
// The other end of the core has the same basic interface, but it isn't
// registered. This allows you to interact with the bus interfaces
// as though they were combinatorial logic, by interacting with this half
// of the core.
//
// If at any time the incoming !stall signal, i_ready, signals a stall,
// the incoming data is placed into a buffer. Internally, that buffer
// is held in r_data with the r_valid flag used to indicate that valid
// data is within it.
// }}}
// Parameters:
// {{{
// DW or data width
// In order to make this core generic, the width of the data in the
// skid buffer is parameterized
//
// OPT_LOWPOWER
// Forces both o_data and r_data to zero if the respective *VALID
// signal is also low. While this costs extra logic, it can also
// be used to guarantee that any unused values aren't toggling and
// therefore unnecessarily using power.
//
// This excess toggling can be particularly problematic if the
// bus signals have a high fanout rate, or a long signal path
// across an FPGA.
//
// OPT_OUTREG
// Causes the outputs to be registered
//
// OPT_PASSTHROUGH
// Turns the skid buffer into a passthrough. Used for formal
// verification only.
// }}}
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2019-2022, Gisselquist Technology, LLC
// {{{
// This file is part of the WB2AXIP project.
//
// The WB2AXIP project contains free software and gateware, licensed under the
// Apache License, Version 2.0 (the "License"). You may not use this project,
// or this file, except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
// }}}
module skidbuffer #(
// {{{
parameter [0:0] OPT_LOWPOWER = 0,
parameter [0:0] OPT_OUTREG = 1,
//
parameter [0:0] OPT_PASSTHROUGH = 0,
parameter DW = 8,
parameter [0:0] OPT_INITIAL = 1'b1
// }}}
) (
// {{{
input wire i_clk, i_reset,
input wire i_valid,
output wire o_ready,
input wire [DW-1:0] i_data,
output wire o_valid,
input wire i_ready,
output reg [DW-1:0] o_data
// }}}
);
wire [DW-1:0] w_data;
generate if (OPT_PASSTHROUGH)
begin : PASSTHROUGH
// {{{
assign { o_valid, o_ready } = { i_valid, i_ready };
always @(*)
if (!i_valid && OPT_LOWPOWER)
o_data = 0;
else
o_data = i_data;
assign w_data = 0;
// Keep Verilator happy
// Verilator lint_off UNUSED
// {{{
wire unused_passthrough;
assign unused_passthrough = &{ 1'b0, i_clk, i_reset };
// }}}
// Verilator lint_on UNUSED
// }}}
end else begin : LOGIC
// We'll start with skid buffer itself
// {{{
reg r_valid;
reg [DW-1:0] r_data;
// r_valid
// {{{
initial if (OPT_INITIAL) r_valid = 0;
always @(posedge i_clk)
if (i_reset)
r_valid <= 0;
else if ((i_valid && o_ready) && (o_valid && !i_ready))
// We have incoming data, but the output is stalled
r_valid <= 1;
else if (i_ready)
r_valid <= 0;
// }}}
// r_data
// {{{
initial if (OPT_INITIAL) r_data = 0;
always @(posedge i_clk)
if (OPT_LOWPOWER && i_reset)
r_data <= 0;
else if (OPT_LOWPOWER && (!o_valid || i_ready))
r_data <= 0;
else if ((!OPT_LOWPOWER || !OPT_OUTREG || i_valid) && o_ready)
r_data <= i_data;
assign w_data = r_data;
// }}}
// o_ready
// {{{
assign o_ready = !r_valid;
// }}}
//
// And then move on to the output port
//
if (!OPT_OUTREG)
begin : NET_OUTPUT
// Outputs are combinatorially determined from inputs
// {{{
// o_valid
// {{{
assign o_valid = !i_reset && (i_valid || r_valid);
// }}}
// o_data
// {{{
always @(*)
if (r_valid)
o_data = r_data;
else if (!OPT_LOWPOWER || i_valid)
o_data = i_data;
else
o_data = 0;
// }}}
// }}}
end else begin : REG_OUTPUT
// Register our outputs
// {{{
// o_valid
// {{{
reg ro_valid;
initial if (OPT_INITIAL) ro_valid = 0;
always @(posedge i_clk)
if (i_reset)
ro_valid <= 0;
else if (!o_valid || i_ready)
ro_valid <= (i_valid || r_valid);
assign o_valid = ro_valid;
// }}}
// o_data
// {{{
initial if (OPT_INITIAL) o_data = 0;
always @(posedge i_clk)
if (OPT_LOWPOWER && i_reset)
o_data <= 0;
else if (!o_valid || i_ready)
begin
if (r_valid)
o_data <= r_data;
else if (!OPT_LOWPOWER || i_valid)
o_data <= i_data;
else
o_data <= 0;
end
// }}}
// }}}
end
// }}}
end endgenerate
// }}}
endmodule
`default_nettype wire
hdl/top/spexi7u_ref_design/wbm2axisp.v 0 → 100644
View file @ d805e900
This diff is collapsed.
software/vitis/fmc_adc_100M/src/main.c
View file @ d805e900
......@@ -87,15 +87,28 @@ int main(void) {
init_gpiops(&ps_gpio);
i2c_init(fa.fa_i2c_base);
si570_set_frequency(fa.fa_i2c_base, &si570, 100000000LL);
//si570_set_frequency(fa.fa_i2c_base, &si570, 100000000LL);
i2c_write_byte(fa.fa_i2c_base, SI570_I2C_ADDR, SI570_REG_CONTROL,
SI570_CNTRL_RECALL);
XGpioPs_WritePin(&ps_gpio, SPEXI7U_PL_RESET_GPIOPS_PIN, 0);
usleep(10);
XGpioPs_WritePin(&ps_gpio, SPEXI7U_PL_RESET_GPIOPS_PIN, 1);
// enable 50-ohm termination and 10V range
for (int i = 0; i < 4; i++)
fa.fa_adc_csr_base->chan[i].ctrl = 0x45 | 0x08;
fa.fa_adc_csr_base->shots = 1;
fa.fa_adc_csr_base->post_samples = 256;
for (int i = 0; i < 4; i++) {
// enable 50-ohm termination and 10V calibrated range
fa.fa_adc_csr_base->chan[i].ctrl = 0x44 | 0x08;
// gain 1, no offset
fa.fa_adc_csr_base->chan[i].calib = 0x8000;
// no saturation
fa.fa_adc_csr_base->chan[i].sat = -1;
}
// apply channel configuration
fa.fa_adc_csr_base->ctrl |= 0x8000;
fa_spi_init(fa.fa_spi_base);
......@@ -112,9 +125,11 @@ int main(void) {
fa.fa_adc_csr_base->ctrl = 0;
usleep(1000);
for (int16_t i = 0x2000; i > 0; i >>= 1) {
fa_adc_data_pattern_set(&fa, i, 1);
}
/*for (int16_t i = 0x2000; i > 0; i >>= 1) {
fa_adc_data_pattern_set(&fa, i, 1);
}*/
fa_adc_data_pattern_set(&fa, 0x5554, 1);
fa_adc_data_pattern_set(&fa, 0, 0);
......
software/vitis/spexi7u/platform.tcl
View file @ d805e900
......@@ -30,3 +30,4 @@ bsp reload
catch {bsp regenerate}
platform generate -domains standalone_domain
platform generate
platform generate
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