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FMC ADC 100M 14b 4cha
Commit cc9eb1c5 authored by Tristan Gingold's avatar Tristan Gingold Committed by Dimitris Lampridis
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Add alternate trigger in (from a separate WB interface).

parent 552ff72c
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Showing with 469 additions and 60 deletions
doc/manual/fmc_adc_100Ms_csr.tex
View file @ cc9eb1c5
......@@ -329,6 +329,11 @@ Software trigger
@code{TIME}
@tab @code{0} @tab
Timetag trigger
@item @code{5}
@tab R/W @tab
@code{ALT_TIME}
@tab @code{0} @tab
Alternate timetag trigger
@item @code{8}
@tab R/W @tab
@code{CH1}
......@@ -355,6 +360,7 @@ Channel 4 internal threshold trigger
@item @code{ext} @tab 0: disable@*1: enable
@item @code{sw} @tab 0: disable@*1: enable
@item @code{time} @tab 0: disable@*1: enable
@item @code{alt_time} @tab 0: disable@*1: enable
@item @code{ch1} @tab 0: disable@*1: enable
@item @code{ch2} @tab 0: disable@*1: enable
@item @code{ch3} @tab 0: disable@*1: enable
......
hdl/rtl/Manifest.py
View file @ cc9eb1c5
......@@ -5,6 +5,7 @@ files = [
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_100Ms_csr_wbgen2_pkg.vhd",
"fmc_adc_alt_trigin.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd",
]
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ cc9eb1c5
......@@ -69,8 +69,9 @@ entity fmc_adc_100Ms_core is
acq_end_p_o : out std_logic;
-- Trigger time-tag inputs
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
alt_time_trig_i : in std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
......@@ -241,6 +242,9 @@ architecture rtl of fmc_adc_100Ms_core is
signal time_trig : std_logic;
signal time_trig_en : std_logic;
signal time_trig_fixed_delay : std_logic_vector(4 downto 0);
signal alt_time_trig : std_logic;
signal alt_time_trig_en : std_logic;
signal alt_time_trig_fixed_delay : std_logic_vector(4 downto 0);
signal trig : std_logic;
signal trig_align : std_logic;
signal trig_fifo_din : std_logic_vector(32 downto 0);
......@@ -716,6 +720,7 @@ begin
sw_trig <= csr_regout.sw_trig_wr_o;
sw_trig_en <= csr_regout.trig_en_sw_o;
time_trig_en <= csr_regout.trig_en_time_o;
alt_time_trig_en <= csr_regout.trig_en_alt_time_o;
shots_value <= csr_regout.shots_nb_o;
undersample_factor <= csr_regout.sr_undersample_o;
pre_trig_value <= csr_regout.pre_samples_o;
......@@ -836,6 +841,15 @@ begin
npulse_o => open,
ppulse_o => time_trig);
cmp_alt_time_trig_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => alt_time_trig_i,
synced_o => open,
npulse_o => open,
ppulse_o => alt_time_trig);
-- Internal hardware trigger
g_int_trig : for I in 1 to 4 generate
int_trig_data(I) <= data_calibr_out(16*I-1 downto 16*I-16);
......@@ -932,13 +946,15 @@ begin
begin
if rising_edge(fs_clk) then
if fs_rst_n = '0' then
sw_trig_fixed_delay <= (others => '0');
ext_trig_fixed_delay <= (others => '0');
time_trig_fixed_delay <= (others => '0');
sw_trig_fixed_delay <= (others => '0');
ext_trig_fixed_delay <= (others => '0');
time_trig_fixed_delay <= (others => '0');
alt_time_trig_fixed_delay <= (others => '0');
else
sw_trig_fixed_delay <= sw_trig_fixed_delay(sw_trig_fixed_delay'high -1 downto 0) & sw_trig;
ext_trig_fixed_delay <= ext_trig_fixed_delay(ext_trig_fixed_delay'high -1 downto 0) & ext_trig_d;
time_trig_fixed_delay <= time_trig_fixed_delay(time_trig_fixed_delay'high -1 downto 0) & time_trig;
alt_time_trig_fixed_delay <= alt_time_trig_fixed_delay(alt_time_trig_fixed_delay'high -1 downto 0) & alt_time_trig;
end if;
end if;
end process p_trig_shift;
......@@ -950,7 +966,10 @@ begin
(int_trig_d(2) and int_trig_en(2)) or
(int_trig_d(3) and int_trig_en(3)) or
(int_trig_d(4) and int_trig_en(4)) or
(time_trig_fixed_delay(time_trig_fixed_delay'HIGH) and time_trig_en);
(time_trig_fixed_delay(time_trig_fixed_delay'HIGH)
and time_trig_en) or
(alt_time_trig_fixed_delay(alt_time_trig_fixed_delay'HIGH)
and alt_time_trig_en);
------------------------------------------------------------------------------
-- Trigger source storage and synchronisation to system clock domain
......@@ -959,7 +978,9 @@ begin
trig_fifo_din <= trig & X"00000" &
int_trig_d(4) & int_trig_d(3) &
int_trig_d(2) & int_trig_d(1) &
"000" & time_trig_fixed_delay(time_trig_fixed_delay'HIGH) &
"00" &
alt_time_trig_fixed_delay(alt_time_trig_fixed_delay'HIGH) &
time_trig_fixed_delay(time_trig_fixed_delay'HIGH) &
"00" & sw_trig_fixed_delay(sw_trig_fixed_delay'HIGH) &
ext_trig_fixed_delay(ext_trig_fixed_delay'HIGH);
......
hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ cc9eb1c5
......@@ -78,8 +78,9 @@ package fmc_adc_100Ms_core_pkg is
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
alt_time_trig_i : in std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
......
hdl/rtl/fmc_adc_100Ms_csr.vhd
View file @ cc9eb1c5
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC 100MS/s core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- File : ../fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Mon Feb 19 14:22:24 2018
-- Created : Tue Nov 6 10:51:54 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -29,6 +29,8 @@ entity fmc_adc_100ms_csr is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
regs_i : in t_fmc_adc_100ms_csr_in_registers;
......@@ -59,6 +61,9 @@ signal fmc_adc_100ms_csr_trig_en_sw_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_time_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_time_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_time_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_alt_time_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_alt_time_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_alt_time_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch1_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch1_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch1_sync1 : std_logic ;
......@@ -207,8 +212,13 @@ signal fmc_adc_100ms_csr_ch4_trig_dly_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(7 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
......@@ -233,6 +243,7 @@ begin
fmc_adc_100ms_csr_trig_en_ext_int <= '0';
fmc_adc_100ms_csr_trig_en_sw_int <= '0';
fmc_adc_100ms_csr_trig_en_time_int <= '0';
fmc_adc_100ms_csr_trig_en_alt_time_int <= '0';
fmc_adc_100ms_csr_trig_en_ch1_int <= '0';
fmc_adc_100ms_csr_trig_en_ch2_int <= '0';
fmc_adc_100ms_csr_trig_en_ch3_int <= '0';
......@@ -500,6 +511,7 @@ begin
fmc_adc_100ms_csr_trig_en_ext_int <= wrdata_reg(0);
fmc_adc_100ms_csr_trig_en_sw_int <= wrdata_reg(1);
fmc_adc_100ms_csr_trig_en_time_int <= wrdata_reg(4);
fmc_adc_100ms_csr_trig_en_alt_time_int <= wrdata_reg(5);
fmc_adc_100ms_csr_trig_en_ch1_int <= wrdata_reg(8);
fmc_adc_100ms_csr_trig_en_ch2_int <= wrdata_reg(9);
fmc_adc_100ms_csr_trig_en_ch3_int <= wrdata_reg(10);
......@@ -508,13 +520,13 @@ begin
rddata_reg(0) <= fmc_adc_100ms_csr_trig_en_ext_int;
rddata_reg(1) <= fmc_adc_100ms_csr_trig_en_sw_int;
rddata_reg(4) <= fmc_adc_100ms_csr_trig_en_time_int;
rddata_reg(5) <= fmc_adc_100ms_csr_trig_en_alt_time_int;
rddata_reg(8) <= fmc_adc_100ms_csr_trig_en_ch1_int;
rddata_reg(9) <= fmc_adc_100ms_csr_trig_en_ch2_int;
rddata_reg(10) <= fmc_adc_100ms_csr_trig_en_ch3_int;
rddata_reg(11) <= fmc_adc_100ms_csr_trig_en_ch4_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(12) <= 'X';
......@@ -1430,6 +1442,22 @@ begin
end process;
-- Alternate timetag trigger
-- synchronizer chain for field : Alternate timetag trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_en_alt_time_o <= '0';
fmc_adc_100ms_csr_trig_en_alt_time_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_alt_time_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_en_alt_time_sync0 <= fmc_adc_100ms_csr_trig_en_alt_time_int;
fmc_adc_100ms_csr_trig_en_alt_time_sync1 <= fmc_adc_100ms_csr_trig_en_alt_time_sync0;
regs_o.trig_en_alt_time_o <= fmc_adc_100ms_csr_trig_en_alt_time_sync1;
end if;
end process;
-- Channel 1 internal threshold trigger
-- synchronizer chain for field : Channel 1 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
......@@ -1926,6 +1954,8 @@ begin
regs_o.ch4_trig_dly_o <= fmc_adc_100ms_csr_ch4_trig_dly_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
View file @ cc9eb1c5
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC 100MS/s core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- File : ../fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Mon Feb 19 14:22:24 2018
-- Created : Tue Nov 6 10:51:54 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -80,6 +80,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_en_ext_o : std_logic;
trig_en_sw_o : std_logic;
trig_en_time_o : std_logic;
trig_en_alt_time_o : std_logic;
trig_en_ch1_o : std_logic;
trig_en_ch2_o : std_logic;
trig_en_ch3_o : std_logic;
......@@ -139,6 +140,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_en_ext_o => '0',
trig_en_sw_o => '0',
trig_en_time_o => '0',
trig_en_alt_time_o => '0',
trig_en_ch1_o => '0',
trig_en_ch2_o => '0',
trig_en_ch3_o => '0',
......@@ -202,7 +204,7 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
if(x(i) = '1') then
tmp(i):= '1';
else
tmp(i):= '0';
......
hdl/rtl/fmc_adc_alt_trigin.vhd 0 → 100644
View file @ cc9eb1c5
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity alt_trigin is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Enable trigger, cleared when triggered
ctrl_enable_i : in std_logic;
-- Enable trigger, cleared when triggered
ctrl_enable_o : out std_logic;
ctrl_wr_o : out std_logic;
-- Time (seconds) to trigger
seconds_i : in std_logic_vector(63 downto 0);
-- Time (cycles) to trigger
cycles_i : in std_logic_vector(31 downto 0)
);
end alt_trigin;
architecture syn of alt_trigin is
signal wb_en : std_logic;
signal rd_int : std_logic;
signal wr_int : std_logic;
signal ack_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wr_ack_done_int : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
rd_int <= wb_en and not wb_i.we;
wr_int <= wb_en and wb_i.we;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
wr_ack_done_int <= '0';
ctrl_wr_o <= '0';
elsif rising_edge(clk_i) then
ctrl_wr_o <= '0';
if wr_int = '1' then
-- Write in progress
wr_ack_done_int <= wr_ack_int or wr_ack_done_int;
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register ctrl
ctrl_wr_o <= '1';
ctrl_enable_o <= wb_i.dat(1);
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register seconds
wr_ack_int <= not wr_ack_done_int;
when "1" =>
-- Register seconds
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register cycles
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
end case;
when others =>
end case;
else
wr_ack_int <= '0';
wr_ack_done_int <= '0';
end if;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
elsif rising_edge(clk_i) then
if rd_int = '1' and rd_ack1_int = '0' then
rd_ack1_int <= '1';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- ctrl
when others =>
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- seconds
reg_rdat_int <= seconds_i(63 downto 32);
when "1" =>
-- seconds
reg_rdat_int <= seconds_i(31 downto 0);
when others =>
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- cycles
reg_rdat_int <= cycles_i;
when others =>
end case;
when others =>
end case;
else
rd_ack1_int <= '0';
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
rd_ack_int <= '1';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- ctrl
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- seconds
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
-- seconds
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- cycles
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
end case;
when others =>
end case;
end process;
end syn;
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ cc9eb1c5
......@@ -64,6 +64,10 @@ entity fmc_adc_mezzanine is
eic_irq_o : out std_logic;
acq_cfg_ok_o : out std_logic;
-- Alternate trigger input wishbone interface
wb_trigin_slave_i : in t_wishbone_slave_in;
wb_trigin_slave_o : out t_wishbone_slave_out;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
......@@ -253,6 +257,14 @@ architecture rtl of fmc_adc_mezzanine is
signal trigger_tag : t_timetag;
signal time_trigger : std_logic;
-- Alternative time trigger
signal alt_trigin_enable_in : std_logic;
signal alt_trigin_enable_out : std_logic;
signal alt_trigin_enable_wr : std_logic;
signal alt_trigin_tag : t_timetag;
signal alt_time_trigger : std_logic;
signal alt_trigin_secs : std_logic_vector(63 downto 0);
signal alt_trigin_cycs : std_logic_vector(31 downto 0);
begin
------------------------------------------------------------------------------
......@@ -448,8 +460,9 @@ begin
acq_stop_p_o => acq_stop_p,
acq_end_p_o => acq_end_p,
trigger_tag_i => trigger_tag,
time_trig_i => time_trigger,
trigger_tag_i => trigger_tag,
time_trig_i => time_trigger,
alt_time_trig_i => alt_time_trigger,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
......@@ -577,6 +590,12 @@ begin
trig_tag_o => trigger_tag,
time_trig_o => time_trigger,
alt_trigin_enable_o => alt_trigin_enable_in,
alt_trigin_enable_i => alt_trigin_enable_out,
alt_trigin_enable_wr_i => alt_trigin_enable_wr,
alt_trigin_tag_i => alt_trigin_tag,
alt_trigin_o => alt_time_trigger,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_TIMETAG).dat,
......@@ -587,6 +606,26 @@ begin
wb_ack_o => cnx_slave_out(c_WB_SLAVE_TIMETAG).ack
);
cmp_alt_trigin : entity work.alt_trigin
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
wb_i => wb_trigin_slave_i,
wb_o => wb_trigin_slave_o,
ctrl_enable_i => alt_trigin_enable_in,
ctrl_enable_o => alt_trigin_enable_out,
ctrl_wr_o => alt_trigin_enable_wr,
seconds_i => alt_trigin_secs,
cycles_i => alt_trigin_cycs
);
alt_trigin_secs(39 downto 0) <= alt_trigin_tag.seconds;
alt_trigin_secs(63 downto 40) <= (others => '0');
alt_trigin_cycs(27 downto 0) <= alt_trigin_tag.coarse;
alt_trigin_cycs(31 downto 28) <= (others => '0');
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_TIMETAG).err <= '0';
cnx_slave_out(c_WB_SLAVE_TIMETAG).rty <= '0';
......
hdl/rtl/timetag_core/timetag_core.vhd
View file @ cc9eb1c5
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-11-18
-- Last update: 2016-06-22
-- Last update: 2018-11-06
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implements a UTC seconds counter and a 125MHz system clock
......@@ -63,6 +63,13 @@ entity timetag_core is
trig_tag_o : out t_timetag;
time_trig_o : out std_logic;
-- Alternative trigger in time
alt_trigin_enable_o : out std_logic;
alt_trigin_enable_i : in std_logic;
alt_trigin_enable_wr_i : in std_logic;
alt_trigin_tag_i : in t_timetag;
alt_trigin_o : out std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
......@@ -120,6 +127,10 @@ architecture rtl of timetag_core is
signal regin : t_timetag_core_in_registers;
signal regout : t_timetag_core_out_registers;
signal alt_trigin : std_logic;
signal alt_trigin_d : std_logic;
signal alt_trigin_enable : std_logic;
begin
-- logic to detect if WR is enabled and timecode is valid
......@@ -228,6 +239,41 @@ begin
time_trig_o <= time_trig or time_trig_d;
-- Alternative time trigger generation (also stretched).
alt_trigin <= alt_trigin_enable when alt_trigin_tag_i = current_time else '0';
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
alt_trigin_enable <= '0';
else
if alt_trigin_enable_wr_i = '1' then
-- User write.
alt_trigin_enable <= alt_trigin_enable_i;
elsif alt_trigin = '1' then
-- Auto clear after trigger.
alt_trigin_enable <= '0';
end if;
end if;
end if;
end process;
alt_trigin_enable_o <= alt_trigin_enable;
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
alt_trigin_d <= '0';
else
alt_trigin_d <= alt_trigin;
end if;
end if;
end process;
alt_trigin_o <= alt_trigin or alt_trigin_d;
------------------------------------------------------------------------------
-- Last trigger event time-tag
------------------------------------------------------------------------------
......
hdl/rtl/timetag_core/timetag_core_pkg.vhd
View file @ cc9eb1c5
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Last update: 2016-06-15
-- Last update: 2018-11-06
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
......@@ -55,26 +55,31 @@ package timetag_core_pkg is
------------------------------------------------------------------------------
component timetag_core is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
wr_enabled_i : in std_logic;
wr_tm_time_valid_i : in std_logic;
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
trig_tag_o : out t_timetag;
time_trig_o : out std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
clk_i : in std_logic;
rst_n_i : in std_logic;
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
wr_enabled_i : in std_logic;
wr_tm_time_valid_i : in std_logic;
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
trig_tag_o : out t_timetag;
time_trig_o : out std_logic;
alt_trigin_enable_o : out std_logic;
alt_trigin_enable_i : in std_logic;
alt_trigin_enable_wr_i : in std_logic;
alt_trigin_tag_i : in t_timetag;
alt_trigin_o : out std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component timetag_core;
end timetag_core_pkg;
......
hdl/rtl/wb_gen/Makefile
View file @ cc9eb1c5
WBGEN2=$(shell which wbgen2)
CHEBY=cheby
RTL=../
SIM=../../testbench/include/
TEX=../../../doc/manual/
......@@ -12,3 +13,10 @@ fmc_adc_100Ms_csr:
fmc_adc_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
fmc_adc_alt_trigin:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd -i $@.cheby
fmc_adc_alt_trigout:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd -i $@.cheby
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.h
View file @ cc9eb1c5
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Mon Feb 19 14:22:25 2018
* Created : Tue Nov 6 10:51:54 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -115,6 +115,9 @@
/* definitions for field: Timetag trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_TIME WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Alternate timetag trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Channel 1 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH1 WBGEN2_GEN_MASK(8, 1)
......
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.htm
View file @ cc9eb1c5
......@@ -851,10 +851,10 @@ CH4_TRIG_DLY
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
&rArr;
</td>
<td class="td_pblock_left">
rst_n_i
wb_adr_i[7:0]
</td>
<td class="td_sym_center">
......@@ -868,10 +868,10 @@ rst_n_i
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
&rArr;
</td>
<td class="td_pblock_left">
clk_sys_i
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
......@@ -885,10 +885,10 @@ fmc_adc_100ms_csr_ctl_fsm_cmd_o[1:0]
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
&lArr;
</td>
<td class="td_pblock_left">
wb_adr_i[7:0]
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
......@@ -902,10 +902,10 @@ fmc_adc_100ms_csr_ctl_fsm_cmd_wr_o
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
&rarr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
wb_cyc_i
</td>
<td class="td_sym_center">
......@@ -919,10 +919,10 @@ fmc_adc_100ms_csr_ctl_fmc_clk_oe_o
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
......@@ -939,7 +939,7 @@ fmc_adc_100ms_csr_ctl_offset_dac_clr_n_o
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
wb_stb_i
</td>
<td class="td_sym_center">
......@@ -953,10 +953,10 @@ fmc_adc_100ms_csr_ctl_man_bitslip_o
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
&rarr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
wb_we_i
</td>
<td class="td_sym_center">
......@@ -970,10 +970,10 @@ fmc_adc_100ms_csr_ctl_test_data_en_o
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
&larr;
</td>
<td class="td_pblock_left">
wb_stb_i
wb_ack_o
</td>
<td class="td_sym_center">
......@@ -987,10 +987,10 @@ fmc_adc_100ms_csr_ctl_trig_led_o
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
&larr;
</td>
<td class="td_pblock_left">
wb_we_i
wb_err_o
</td>
<td class="td_sym_center">
......@@ -1007,7 +1007,7 @@ fmc_adc_100ms_csr_ctl_acq_led_o
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
wb_rty_o
</td>
<td class="td_sym_center">
......@@ -1368,6 +1368,23 @@ fmc_adc_100ms_csr_trig_en_time_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_en_alt_time_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_en_ch1_o
......@@ -4693,8 +4710,8 @@ CH1
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
ALT_TIME
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TIME
......@@ -4727,6 +4744,10 @@ TIME
</b>[<i>read/write</i>]: Timetag trigger
<br>0: disable<br>1: enable
<li><b>
ALT_TIME
</b>[<i>read/write</i>]: Alternate timetag trigger
<br>0: disable<br>1: enable
<li><b>
CH1
</b>[<i>read/write</i>]: Channel 1 internal threshold trigger
<br>0: disable<br>1: enable
......
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.wb
View file @ cc9eb1c5
......@@ -227,6 +227,16 @@ peripheral {
clock = "fs_clk_i";
};
field {
name = "Alternate timetag trigger";
description = "0: disable\n1: enable";
prefix = "alt_time";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 8;
name = "Channel 1 internal threshold trigger";
......
hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby 0 → 100644
View file @ cc9eb1c5
memory-map:
bus: wb-32-be
name: alt_trigin
x-hdl:
busgroup: True
children:
- reg:
name: ctrl
description: Control register
access: rw
width: 32
children:
- field:
name: enable
description: Enable trigger, cleared when triggered
range: 1
x-hdl:
type: wire
x-hdl:
write-strobe: True
- reg:
name: seconds
description: Time (seconds) to trigger
width: 64
type: unsigned
access: ro
- reg:
name: cycles
description: Time (cycles) to trigger
width: 32
type: unsigned
access: ro
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ cc9eb1c5
......@@ -33,6 +33,7 @@ module main;
end
IVHDWishboneMaster Host ( clk_sys, rst_n );
IVHDWishboneMaster Trigin ( clk_sys, rst_n );
wire t_wishbone_slave_data64_out dummy_wb64_out =
'{ack: 1'b1, err: 1'b0, rty: 1'b0, stall: 1'b0, dat: 64'bx};
......@@ -54,6 +55,8 @@ module main;
.acq_end_irq_o (),
.eic_irq_o (),
.acq_cfg_ok_o (),
.wb_trigin_slave_i (Trigin.out),
.wb_trigin_slave_o (Trigin.in),
.ext_trigger_p_i (ext_trig),
.ext_trigger_n_i (~ext_trig),
.adc_dco_p_i (adc0_dco),
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ cc9eb1c5
......@@ -46,6 +46,8 @@
`define FMC_ADC_100MS_CSR_TRIG_EN_SW 32'h00000002
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME 32'h00000010
`define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET 5
`define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME 32'h00000020
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2_OFFSET 9
......
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