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FMC ADC 100M 14b 4cha
Commit aa8483fb authored by Tristan Gingold's avatar Tristan Gingold
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gateware/index.rst: refix ref code

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doc/gateware/index.rst
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...@@ -355,6 +355,7 @@ This block is clocked by the system clock (125 MHz). Therefore for a ...@@ -355,6 +355,7 @@ This block is clocked by the system clock (125 MHz). Therefore for a
SCLK of ~620 kHz, the divider configuration is ``DIVIDER=100``. SCLK of ~620 kHz, the divider configuration is ``DIVIDER=100``.
:: ::
f_sclk = f_sys / ((DIVIDER+1) * 2) f_sclk = f_sys / ((DIVIDER+1) * 2)
Mezzanine 1-wire Master Mezzanine 1-wire Master
...@@ -380,6 +381,7 @@ This block is clocked by the system clock (125 MHz). Therefore for a SCL ...@@ -380,6 +381,7 @@ This block is clocked by the system clock (125 MHz). Therefore for a SCL
clock of 100 kHz, the prescaler configuration is ``PRESCALER=249``. clock of 100 kHz, the prescaler configuration is ``PRESCALER=249``.
:: ::
PRESCALER = f_sys / (5 * f_scl) - 1 PRESCALER = f_sys / (5 * f_scl) - 1
......
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