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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
9fe7aae8
Commit
9fe7aae8
authored
Nov 07, 2018
by
Tristan Gingold
Committed by
Dimitris Lampridis
Jan 17, 2019
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timetag: generate (and use in testbench) the registers constants.
parent
24f5001b
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3 changed files
with
31 additions
and
8 deletions
+31
-8
Makefile
hdl/rtl/timetag_core/wb_gen/Makefile
+2
-1
main.sv
hdl/testbench/fmc_adc_mezzanine/main.sv
+11
-7
timetag_core_regs.v
hdl/testbench/include/timetag_core_regs.v
+18
-0
No files found.
hdl/rtl/timetag_core/wb_gen/Makefile
View file @
9fe7aae8
WBGEN2
=
$(
shell
which wbgen2
)
RTL
=
../
TEX
=
../../../../doc/manual/
SIM
=
../../../testbench/include/
timetag_core_regs
:
$(WBGEN2)
-l
vhdl
-H
record
-V
$(RTL)$@
.vhd
-p
$(RTL)$@
_wbgen2_pkg.vhd
-f
html
-D
$@
.htm
-C
$@
.h
$@
.wb
$(WBGEN2)
-l
vhdl
-H
record
-V
$(RTL)$@
.vhd
-p
$(RTL)$@
_wbgen2_pkg.vhd
-f
html
-D
$@
.htm
-C
$@
.h
-K
$(SIM)$@
.v
$@
.wb
$(WBGEN2)
-f
texinfo
-D
$(TEX)$@
.tex
$@
.wb
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @
9fe7aae8
...
...
@@ -2,6 +2,7 @@
`include
"vhd_wishbone_master.svh"
`include
"fmc_adc_100Ms_csr.v"
`include
"timetag_core_regs.v"
`define
SDB_ADDR
'
h0000
`define
CSR_BASE
'
h1000
...
...
@@ -220,9 +221,9 @@ module main;
#
1u
s
;
acc
.
write
(
`TAG_BASE
+
0
,
'h00000032
)
;
// timetag core seconds high
acc
.
write
(
`TAG_BASE
+
4
,
'h00005a34
)
;
// timetag core seconds low
acc
.
write
(
`TAG_BASE
+
8
,
'h00000000
)
;
// timetag core ticks
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_SECONDS_UPPER
,
'h00000032
)
;
// timetag core seconds high
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_SECONDS_LOWER
,
'h00005a34
)
;
// timetag core seconds low
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_COARSE
,
'h00000000
)
;
// timetag core ticks
wait
(
acq_fsm_state
==
1
)
;
$
display
(
"<%t> START ACQ 1/4"
,
$
realtime
)
;
...
...
@@ -279,14 +280,17 @@ module main;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SW_TRIG
,
'hFFFFFFFD
)
;
// soft trigger
wait
(
acq_fsm_state
==
1
)
;
$
display
(
"<%t> END ACQ 3
/4
"
,
$
realtime
)
;
$
display
(
"<%t> END ACQ 3"
,
$
realtime
)
;
#
1u
s
;
// set time trigger
acc
.
write
(
`TAG_BASE
+
'h0c
,
'h00000032
)
;
// timetag core seconds high
acc
.
write
(
`TAG_BASE
+
'h10
,
'h00005a34
)
;
// timetag core seconds low
acc
.
write
(
`TAG_BASE
+
'h14
,
'h00000e00
)
;
// timetag core ticks
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_UPPER
,
'h00000032
)
;
// timetag core seconds high
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_LOWER
,
'h00005a34
)
;
// timetag core seconds low
acc
.
write
(
`TAG_BASE
+
`ADDR_TIMETAG_CORE_TIME_TRIG_COARSE
,
'h00000e00
)
;
// timetag core ticks
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00000010
)
;
acc
.
write
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h00000080
)
;
...
...
hdl/testbench/include/timetag_core_regs.v
0 → 100644
View file @
9fe7aae8
`define
ADDR_TIMETAG_CORE_SECONDS_UPPER
7'h0
`define
ADDR_TIMETAG_CORE_SECONDS_LOWER 7
'
h4
`define
ADDR_TIMETAG_CORE_COARSE 7
'
h8
`define
ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_UPPER 7
'
hc
`define
ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_LOWER 7
'
h10
`define
ADDR_TIMETAG_CORE_TIME_TRIG_COARSE 7
'
h14
`define
ADDR_TIMETAG_CORE_TRIG_TAG_SECONDS_UPPER 7
'
h18
`define
ADDR_TIMETAG_CORE_TRIG_TAG_SECONDS_LOWER 7
'
h1c
`define
ADDR_TIMETAG_CORE_TRIG_TAG_COARSE 7
'
h20
`define
ADDR_TIMETAG_CORE_ACQ_START_TAG_SECONDS_UPPER 7
'
h24
`define
ADDR_TIMETAG_CORE_ACQ_START_TAG_SECONDS_LOWER 7
'
h28
`define
ADDR_TIMETAG_CORE_ACQ_START_TAG_COARSE 7
'
h2c
`define
ADDR_TIMETAG_CORE_ACQ_STOP_TAG_SECONDS_UPPER 7
'
h30
`define
ADDR_TIMETAG_CORE_ACQ_STOP_TAG_SECONDS_LOWER 7
'
h34
`define
ADDR_TIMETAG_CORE_ACQ_STOP_TAG_COARSE 7
'
h38
`define
ADDR_TIMETAG_CORE_ACQ_END_TAG_SECONDS_UPPER 7
'
h3c
`define
ADDR_TIMETAG_CORE_ACQ_END_TAG_SECONDS_LOWER 7
'
h40
`define
ADDR_TIMETAG_CORE_ACQ_END_TAG_COARSE 7
'
h44
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