Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha
Commits
79770e81
Commit
79770e81
authored
Dec 19, 2018
by
Tristan Gingold
Committed by
Dimitris Lampridis
Jan 17, 2019
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
alt_trigin: add a version register. Renaming in alt_trigout.
Also generate the doc.
parent
802eda5c
Hide whitespace changes
Inline
Side-by-side
Showing
7 changed files
with
31 additions
and
10 deletions
+31
-10
fmc_adc_alt_trigin.vhd
hdl/rtl/fmc_adc_alt_trigin.vhd
+10
-1
fmc_adc_alt_trigout.vhd
hdl/rtl/fmc_adc_alt_trigout.vhd
+3
-3
Makefile
hdl/rtl/wb_gen/Makefile
+2
-2
fmc_adc_alt_trigin.cheby
hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby
+8
-0
fmc_adc_alt_trigout.cheby
hdl/rtl/wb_gen/fmc_adc_alt_trigout.cheby
+2
-2
fmc_adc_alt_trigin.v
hdl/testbench/include/fmc_adc_alt_trigin.v
+4
-1
fmc_adc_alt_trigout.v
hdl/testbench/include/fmc_adc_alt_trigout.v
+2
-1
No files found.
hdl/rtl/fmc_adc_alt_trigin.vhd
View file @
79770e81
...
...
@@ -71,12 +71,14 @@ begin
when
"00"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- Register version
wr_ack_int
<=
not
wr_ack_done_int
;
when
"1"
=>
-- Register ctrl
ctrl_wr_o
<=
'1'
;
ctrl_enable_o
<=
wb_i
.
dat
(
0
);
wr_ack_int
<=
not
wr_ack_done_int
;
when
others
=>
wr_ack_int
<=
not
wr_ack_done_int
;
end
case
;
when
"01"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
...
...
@@ -122,6 +124,9 @@ begin
when
"00"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- version
reg_rdat_int
<=
"10101101110000010000000000000001"
;
when
"1"
=>
-- ctrl
reg_rdat_int
(
0
)
<=
ctrl_enable_i
;
when
others
=>
...
...
@@ -160,6 +165,10 @@ begin
when
"00"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- version
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1"
=>
-- ctrl
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
...
...
hdl/rtl/fmc_adc_alt_trigout.vhd
View file @
79770e81
...
...
@@ -116,7 +116,7 @@ begin
-- Register status
wr_ack_int
<=
not
wr_ack_done_int
;
when
"1"
=>
-- Register
ctrl
-- Register
enable
ch1_enable_reg
<=
wb_i
.
dat
(
0
);
ch2_enable_reg
<=
wb_i
.
dat
(
1
);
ch3_enable_reg
<=
wb_i
.
dat
(
2
);
...
...
@@ -174,7 +174,7 @@ begin
reg_rdat_int
(
2
)
<=
wr_valid_i
;
reg_rdat_int
(
8
)
<=
ts_present_i
;
when
"1"
=>
--
ctrl
--
enable
reg_rdat_int
(
0
)
<=
ch1_enable_reg
;
reg_rdat_int
(
1
)
<=
ch2_enable_reg
;
reg_rdat_int
(
2
)
<=
ch3_enable_reg
;
...
...
@@ -226,7 +226,7 @@ begin
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1"
=>
--
ctrl
--
enable
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
others
=>
...
...
hdl/rtl/wb_gen/Makefile
View file @
79770e81
...
...
@@ -15,7 +15,7 @@ fmc_adc_eic:
$(WBGEN2)
-f
texinfo
-D
$(TEX)$@
.tex
$@
.wb
fmc_adc_alt_trigin
:
$(CHEBY)
--gen-hdl
=
$(RTL)
/
$@
.vhd
--gen-consts
=
$(SIM)
/
$@
.v
-i
$@
.cheby
$(CHEBY)
--gen-hdl
=
$(RTL)
/
$@
.vhd
--gen-
doc
=
$@
.html
--gen-c
=
$@
.h
--gen-
consts
=
$(SIM)
/
$@
.v
-i
$@
.cheby
fmc_adc_alt_trigout
:
$(CHEBY)
--gen-hdl
=
$(RTL)
/
$@
.vhd
--gen-consts
=
$(SIM)
/
$@
.v
-i
$@
.cheby
$(CHEBY)
--gen-hdl
=
$(RTL)
/
$@
.vhd
--gen-
doc
=
$@
.html
--gen-c
=
$@
.h
--gen-
consts
=
$(SIM)
/
$@
.v
-i
$@
.cheby
hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby
View file @
79770e81
...
...
@@ -4,6 +4,14 @@ memory-map:
x-hdl:
busgroup: True
children:
- reg:
name: version
description: Core version
access: ro
width: 32
preset: 0xADC10001 # ADC Input 0001
x-hdl:
type: const
- reg:
name: ctrl
description: Control register
...
...
hdl/rtl/wb_gen/fmc_adc_alt_trigout.cheby
View file @
79770e81
...
...
@@ -28,8 +28,8 @@ memory-map:
description: Set when the timestamp fifo is not empty
range: 8
- reg:
name:
ctrl
description:
Control
register
name:
enable
description:
Enable
register
access: rw
width: 32
children:
...
...
hdl/testbench/include/fmc_adc_alt_trigin.v
View file @
79770e81
`define
ADDR_ALT_TRIGIN_CTRL
'h0
`define
ALT_TRIGIN_SIZE
20
`define
ADDR_ALT_TRIGIN_VERSION
'
h0
`define
ALT_TRIGIN_VERSION_PRESET
'
hadc10001
`define
ADDR_ALT_TRIGIN_CTRL
'
h4
`define
ALT_TRIGIN_CTRL_ENABLE_OFFSET 0
`define
ALT_TRIGIN_CTRL_ENABLE
'
h1
`define
ADDR_ALT_TRIGIN_SECONDS
'
h8
...
...
hdl/testbench/include/fmc_adc_alt_trigout.v
View file @
79770e81
`define
ALT_TRIGOUT_SIZE
20
`define
ADDR_ALT_TRIGOUT_STATUS
'
h0
`define
ALT_TRIGOUT_WR_ENABLE_OFFSET 0
`define
ALT_TRIGOUT_WR_ENABLE
'
h1
...
...
@@ -7,7 +8,7 @@
`define
ALT_TRIGOUT_WR_VALID
'
h4
`define
ALT_TRIGOUT_TS_PRESENT_OFFSET 8
`define
ALT_TRIGOUT_TS_PRESENT
'
h100
`define
ADDR_ALT_TRIGOUT_
CTRL
'
h4
`define
ADDR_ALT_TRIGOUT_
ENABLE
'
h4
`define
ALT_TRIGOUT_CH1_ENABLE_OFFSET 0
`define
ALT_TRIGOUT_CH1_ENABLE
'
h1
`define
ALT_TRIGOUT_CH2_ENABLE_OFFSET 1
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment