hdl: add FMC identification number to CSR status register.

Addresses HT-610 Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

hdl: add FMC identification number to CSR status register.
Addresses HT-610 Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
778a4401 · Dimitris Lampridis · 35e1f715 · 778a4401 · 778a4401 · 778a4401
Commit 778a4401 authored Aug 04, 2020 by Dimitris Lampridis
10 changed files
--- a/hdl/cheby/fmc_adc_100Ms_csr.cheby
+++ b/hdl/cheby/fmc_adc_100Ms_csr.cheby
@@ -123,6 +123,12 @@ memory-map:
            1: Valid acquisition configuration
            - Shot number > 0
            - Post-trigger sample > 0
+      - field:
+          name: fmc_nr
+          range: 7-6
+          description: FMC identification number
+          comment: |
+            Used to identify the FMC-ADC in case of a carrier with more than one FMC slot.
      - field:
          name: calib_busy
          range: 15

--- a/hdl/cheby/fmc_adc_100Ms_csr.vhd
+++ b/hdl/cheby/fmc_adc_100Ms_csr.vhd
@@ -79,6 +79,7 @@ package fmc_adc_100ms_csr_pkg is
    sta_serdes_pll   : std_logic;
    sta_serdes_synced : std_logic;
    sta_acq_cfg      : std_logic;
+    sta_fmc_nr       : std_logic_vector(1 downto 0);
    sta_calib_busy   : std_logic;
    trig_stat_ext    : std_logic;
    trig_stat_sw     : std_logic;
@@ -583,6 +584,7 @@ begin
          reg_rdat_int(3) <= fmc_adc_100ms_csr_i.sta_serdes_pll;
          reg_rdat_int(4) <= fmc_adc_100ms_csr_i.sta_serdes_synced;
          reg_rdat_int(5) <= fmc_adc_100ms_csr_i.sta_acq_cfg;
+          reg_rdat_int(7 downto 6) <= fmc_adc_100ms_csr_i.sta_fmc_nr;
          reg_rdat_int(15) <= fmc_adc_100ms_csr_i.sta_calib_busy;
          rd_ack1_int <= rd_int;
        when "0000010" => 

--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
@@ -48,6 +48,8 @@ entity fmc_adc_100Ms_core is
    g_TRIG_DELAY_EXT     : natural                        := 7;
    -- Software and time trigger delay calibration value
    g_TRIG_DELAY_SW      : natural                        := 9;
+    -- FMC-ADC identification number
+    g_FMC_ADC_NR         : natural                        := 0;
    -- WB interface configuration
    g_WB_CSR_MODE        : t_wishbone_interface_mode      := PIPELINED;
    g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE);
@@ -473,6 +475,7 @@ begin
  csr_regin.sta_serdes_pll    <= serdes_locked_sync;
  csr_regin.sta_serdes_synced <= serdes_synced_sync;
  csr_regin.sta_acq_cfg       <= acq_config_ok;
+  csr_regin.sta_fmc_nr        <= std_logic_vector(to_unsigned(g_FMC_ADC_NR, 2));
  csr_regin.sta_calib_busy    <= sync_calib_busy;
  csr_regin.trig_stat_ext     <= trig_storage(0);
  csr_regin.trig_stat_sw      <= trig_storage(1);

--- a/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
@@ -57,6 +57,8 @@ package fmc_adc_100Ms_core_pkg is
      g_TRIG_DELAY_EXT     : natural                        := 7;
      -- Software and time trigger delay calibration value
      g_TRIG_DELAY_SW      : natural                        := 9;
+      -- FMC-ADC identification number
+      g_FMC_ADC_NR         : natural                        := 0;
      -- WB interface configuration
      g_WB_CSR_MODE        : t_wishbone_interface_mode      := PIPELINED;
      g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE);

--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -50,6 +50,8 @@ entity fmc_adc_mezzanine is
    -- This is useful if you know that the system introduces
    -- some systematic delay wrt the actual trigger time
    g_TAG_ADJUST         : natural                        := 24;
+    -- FMC-ADC identification number
+    g_FMC_ADC_NR         : natural                        := 0;
    -- WB interface configuration
    g_WB_MODE            : t_wishbone_interface_mode      := PIPELINED;
    g_WB_GRANULARITY     : t_wishbone_address_granularity := BYTE);
@@ -332,6 +334,7 @@ begin
      g_SPARTAN6_USE_PLL   => g_SPARTAN6_USE_PLL,
      g_TRIG_DELAY_EXT     => g_TRIG_DELAY_EXT,
      g_TRIG_DELAY_SW      => g_TRIG_DELAY_SW,
+      g_FMC_ADC_NR         => g_FMC_ADC_NR,
      g_WB_CSR_MODE        => PIPELINED,
      g_WB_CSR_GRANULARITY => BYTE)
    port map (

--- a/hdl/rtl/fmc_adc_mezzanine_pkg.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine_pkg.vhd
@@ -55,6 +55,8 @@ package fmc_adc_mezzanine_pkg is
      -- This is useful if you know that the system introduces
      -- some systematic delay wrt the actual trigger time
      g_TAG_ADJUST         : natural                        := 24;
+      -- FMC-ADC identification number
+      g_FMC_ADC_NR         : natural                        := 0;
      -- WB interface configuration
      g_WB_MODE            : t_wishbone_interface_mode      := PIPELINED;
      g_WB_GRANULARITY     : t_wishbone_address_granularity := BYTE);

--- a/hdl/testbench/include/fmc_adc_100Ms_csr.v
+++ b/hdl/testbench/include/fmc_adc_100Ms_csr.v
@@ -27,6 +27,8 @@
 `define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 'h10
 `define FMC_ADC_100MS_CSR_STA_ACQ_CFG_OFFSET 5
 `define FMC_ADC_100MS_CSR_STA_ACQ_CFG 'h20
+`define FMC_ADC_100MS_CSR_STA_FMC_NR_OFFSET 6
+`define FMC_ADC_100MS_CSR_STA_FMC_NR 'hc0
 `define FMC_ADC_100MS_CSR_STA_CALIB_BUSY_OFFSET 15
 `define FMC_ADC_100MS_CSR_STA_CALIB_BUSY 'h8000
 `define ADDR_FMC_ADC_100MS_CSR_TRIG_STAT 'h8

--- a/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
@@ -11,7 +11,7 @@
 -- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
 -- Carrier (SPEC). See also: http://www.ohwr.org/projects/spec
 -------------------------------------------------------------------------------
-- Copyright (c) 2011-2018 CERN (BE-CO-HT)
+-- Copyright (c) 2011-2020 CERN (BE-CO-HT)
 -------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
 -------------------------------------------------------------------------------
@@ -462,6 +462,7 @@ begin  -- architecture arch
    generic map (
      g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
      g_SPARTAN6_USE_PLL   => FALSE,
+      g_FMC_ADC_NR         => 0,
      g_WB_MODE            => PIPELINED,
      g_WB_GRANULARITY     => BYTE)
    port map (

--- a/hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
@@ -11,7 +11,7 @@
 -- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
 -- Carrier (SVEC). See also: http://www.ohwr.org/projects/svec
 -------------------------------------------------------------------------------
-- Copyright (c) 2013-2018 CERN (BE-CO-HT)
+-- Copyright (c) 2013-2020 CERN (BE-CO-HT)
 -------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
 -------------------------------------------------------------------------------
@@ -545,6 +545,7 @@ begin -- architecture arch
      generic map (
        g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
        g_SPARTAN6_USE_PLL   => TRUE,
+        g_FMC_ADC_NR         => I,
        g_WB_MODE            => PIPELINED,
        g_WB_GRANULARITY     => BYTE)
      port map (

--- a/software/include/hw/fmc_adc_100Ms_csr.h
+++ b/software/include/hw/fmc_adc_100Ms_csr.h
@@ -22,6 +22,8 @@
 #define FMC_ADC_100MS_CSR_STA_SERDES_PLL 0x8UL
 #define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 0x10UL
 #define FMC_ADC_100MS_CSR_STA_ACQ_CFG 0x20UL
+#define FMC_ADC_100MS_CSR_STA_FMC_NR_MASK 0xc0UL
+#define FMC_ADC_100MS_CSR_STA_FMC_NR_SHIFT 6
 #define FMC_ADC_100MS_CSR_STA_CALIB_BUSY 0x8000UL
 /* Trigger status */