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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
77320acb
Commit
77320acb
authored
Jan 04, 2021
by
Dimitris Lampridis
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hdl: cleanup of unused signals
Signed-off-by:
Dimitris Lampridis
<
dimitris.lampridis@cern.ch
>
parent
1760481a
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fmc_adc_100Ms_core.vhd
hdl/rtl/fmc_adc_100Ms_core.vhd
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hdl/rtl/fmc_adc_100Ms_core.vhd
View file @
77320acb
...
...
@@ -140,12 +140,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal
serdes_arst
:
std_logic
;
-- Clocks and PLL
signal
clk_fb
:
std_logic
;
signal
clk_fb_buf
:
std_logic
;
signal
locked_in
:
std_logic
;
signal
serdes_clk
:
std_logic
;
signal
fs_clk
:
std_logic
;
signal
fs_clk_buf
:
std_logic
;
signal
fs_freq
:
std_logic_vector
(
31
downto
0
);
signal
fs_freq_t
:
std_logic_vector
(
31
downto
0
);
signal
fs_freq_valid
:
std_logic
;
...
...
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