Commit 6524363c authored by Federico Vaga's avatar Federico Vaga

doc: fix SPEC description

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent b70a84a3
......@@ -99,7 +99,7 @@ Wishbone address space.
FMC-ADC gateware architecture on SPEC carrier.
There are three different Wishbone bus interconnects in the design.
There are two different Wishbone bus interconnects in the design.
Mapped WB bus (blue)
This bus connects all the peripherals to the GN4142 core.
......
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