doc: simplify SVEC/SPEC pictures

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

doc: simplify SVEC/SPEC pictures
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
5ea7834c · Federico Vaga · c5696479 · 5ea7834c · 5ea7834c · 5ea7834c
Commit 5ea7834c authored Nov 23, 2020 by Federico Vaga
6 changed files
--- a/doc/fig/spec_fw_arch.svg
+++ b/doc/fig/spec_fw_arch.svg
--- a/doc/fig/spec_fw_arch.svg.2020_11_23_14_48_11.0.svg
+++ b/doc/fig/spec_fw_arch.svg.2020_11_23_14_48_11.0.svg
--- a/doc/fig/spec_fw_arch.svg.2020_11_23_15_11_39.0.svg
+++ b/doc/fig/spec_fw_arch.svg.2020_11_23_15_11_39.0.svg
--- a/doc/fig/svec_fw_arch.svg
+++ b/doc/fig/svec_fw_arch.svg
--- a/doc/fig/svec_fw_arch.svg.2020_11_23_16_22_06.0.svg
+++ b/doc/fig/svec_fw_arch.svg.2020_11_23_16_22_06.0.svg
--- a/doc/gateware/index.rst
+++ b/doc/gateware/index.rst
@@ -111,10 +111,6 @@ ADC core to memory controller (orange)
  This bus is used to write samples from the ADC core to the DDR memory.
  Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).

-Memory controller to GN4124 core (red)
-  This bus is used to read samples from the DDR memory.
-  Data: 32-bit, address: 32-bit (word aligned), clock: system clock (125MHz).
-
 Note that some of the cores from the `General Cores`_ library are
 based on cores from `OpenCores`_. Therefore, the documentation for
 those cores is hosted on the OpenCores website.
@@ -167,7 +163,7 @@ Mapped WB bus (blue)
  Data: 32-bit, address: 32-bit (word aligned),
  Clock: system clock (125MHz) and system clock / 2 (62.5MHz), see note below.

-ADC cores to memory controllers (2x, orange)**
+ADC cores to memory controllers (2x, orange)
  These two buses are used to write samples from the ADC cores to the DDR
  memories.
  Data: 64-bit, address: 32-bit (word aligned), clock: system clock (125MHz).