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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
3bf751db
Commit
3bf751db
authored
Aug 05, 2019
by
Dimitris Lampridis
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[hdl] rename undersampling to downsampling
Fixes
https://www.ohwr.org/project/fmc-adc-100m14b4cha/issues/3
.
parent
bb2303fc
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5 changed files
with
38 additions
and
38 deletions
+38
-38
fmc_adc_100Ms_core.vhd
hdl/rtl/fmc_adc_100Ms_core.vhd
+21
-21
fmc_adc_100Ms_csr.cheby
hdl/rtl/fmc_adc_100Ms_csr.cheby
+3
-3
fmc_adc_100Ms_csr.vhd
hdl/rtl/fmc_adc_100Ms_csr.vhd
+9
-9
fmc_adc_100Ms_csr.v
hdl/testbench/include/fmc_adc_100Ms_csr.v
+1
-1
fmc_adc_100Ms_csr.h
software/include/hw/fmc_adc_100Ms_csr.h
+4
-4
No files found.
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @
3bf751db
...
...
@@ -222,10 +222,10 @@ architecture rtl of fmc_adc_100Ms_core is
signal
trig_storage_clear
:
std_logic
;
signal
trig_src_vector
:
std_logic_vector
(
7
downto
0
);
--
Under
-sampling
signal
under
sample_factor
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
under
sample_cnt
:
unsigned
(
31
downto
0
);
signal
under
sample_en
:
std_logic
;
--
Down
-sampling
signal
down
sample_factor
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
down
sample_cnt
:
unsigned
(
31
downto
0
);
signal
down
sample_en
:
std_logic
;
-- Sync FIFO (from fs_clk to sys_clk_i)
signal
sync_fifo_din
:
std_logic_vector
(
72
downto
0
);
...
...
@@ -590,7 +590,7 @@ begin
data_i
=>
csr_regout
.
trig_en_alt_time
,
synced_o
=>
alt_time_trig_en
);
cmp_
under
sample_sync
:
gc_sync_word_wr
cmp_
down
sample_sync
:
gc_sync_word_wr
generic
map
(
g_AUTO_WR
=>
TRUE
,
g_WIDTH
=>
32
)
...
...
@@ -599,8 +599,8 @@ begin
rst_in_n_i
=>
'1'
,
clk_out_i
=>
fs_clk
,
rst_out_n_i
=>
'1'
,
data_i
=>
csr_regout
.
under
sample
,
data_o
=>
under
sample_factor
);
data_i
=>
csr_regout
.
down
sample
,
data_o
=>
down
sample_factor
);
cmp_ch_sta_sync
:
gc_sync_word_wr
generic
map
(
...
...
@@ -957,29 +957,29 @@ begin
trig
<=
f_reduce_or
(
trig_src_vector
);
------------------------------------------------------------------------------
--
Under
-sampling and trigger alignment
-- When
under
-sampling is enabled, if the trigger occurs between two
--
Down
-sampling and trigger alignment
-- When
down
-sampling is enabled, if the trigger occurs between two
-- samples it will be realigned to the next sample
------------------------------------------------------------------------------
p_
under
sample_cnt
:
process
(
fs_clk
)
p_
down
sample_cnt
:
process
(
fs_clk
)
begin
if
rising_edge
(
fs_clk
)
then
if
fs_rst_n
=
'0'
then
undersample_cnt
<=
to_unsigned
(
1
,
under
sample_cnt
'length
);
under
sample_en
<=
'0'
;
downsample_cnt
<=
to_unsigned
(
1
,
down
sample_cnt
'length
);
down
sample_en
<=
'0'
;
else
if
undersample_cnt
=
to_unsigned
(
0
,
under
sample_cnt
'length
)
then
if
under
sample_factor
/=
X"00000000"
then
undersample_cnt
<=
unsigned
(
under
sample_factor
)
-
1
;
if
downsample_cnt
=
to_unsigned
(
0
,
down
sample_cnt
'length
)
then
if
down
sample_factor
/=
X"00000000"
then
downsample_cnt
<=
unsigned
(
down
sample_factor
)
-
1
;
end
if
;
under
sample_en
<=
'1'
;
down
sample_en
<=
'1'
;
else
undersample_cnt
<=
under
sample_cnt
-
1
;
under
sample_en
<=
'0'
;
downsample_cnt
<=
down
sample_cnt
-
1
;
down
sample_en
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
p_
under
sample_cnt
;
end
process
p_
down
sample_cnt
;
p_trig_align
:
process
(
fs_clk
)
begin
...
...
@@ -989,7 +989,7 @@ begin
else
if
trig
=
'1'
then
trig_align
<=
trig_src_vector
&
trig
;
elsif
under
sample_en
=
'1'
then
elsif
down
sample_en
=
'1'
then
trig_align
<=
(
others
=>
'0'
);
end
if
;
end
if
;
...
...
@@ -1032,7 +1032,7 @@ begin
sync_fifo_din
(
63
downto
0
)
<=
data_calibr_out_d3
;
-- FIFO control
sync_fifo_wr
<=
under
sample_en
and
serdes_synced
and
(
not
sync_fifo_full
);
sync_fifo_wr
<=
down
sample_en
and
serdes_synced
and
(
not
sync_fifo_full
);
sync_fifo_rd
<=
not
sync_fifo_empty
;
sync_fifo_valid
<=
not
sync_fifo_empty
;
...
...
hdl/rtl/fmc_adc_100Ms_csr.cheby
View file @
3bf751db
...
...
@@ -377,13 +377,13 @@ memory-map:
comment: |
ADC sampling clock frequency in Hz
- reg:
name:
under
sample
name:
down
sample
address: 0x0000002c
width: 32
access: rw
description:
Under
sampling ratio
description:
Down
sampling ratio
comment: |
Undersampling ratio. Takes one sample every N samples and discards the others (N = under
sampling ratio)
Downsampling ratio. Takes one sample every N samples and discards the others (N = down
sampling ratio)
- reg:
name: pre_samples
address: 0x00000030
...
...
hdl/rtl/fmc_adc_100Ms_csr.vhd
View file @
3bf751db
...
...
@@ -40,7 +40,7 @@ package fmc_adc_100ms_csr_pkg is
sw_trig_wr
:
std_logic
;
shots_nbr
:
std_logic_vector
(
15
downto
0
);
shots_remain
:
std_logic_vector
(
15
downto
0
);
undersample
:
std_logic_vector
(
31
downto
0
);
downsample
:
std_logic_vector
(
31
downto
0
);
pre_samples
:
std_logic_vector
(
31
downto
0
);
post_samples
:
std_logic_vector
(
31
downto
0
);
ch1_ctl_ssr
:
std_logic_vector
(
6
downto
0
);
...
...
@@ -155,7 +155,7 @@ architecture syn of fmc_adc_100ms_csr is
signal
trig_pol_ch4_reg
:
std_logic
;
signal
ext_trig_dly_reg
:
std_logic_vector
(
31
downto
0
);
signal
shots_nbr_reg
:
std_logic_vector
(
15
downto
0
);
signal
undersample_reg
:
std_logic_vector
(
31
downto
0
);
signal
downsample_reg
:
std_logic_vector
(
31
downto
0
);
signal
pre_samples_reg
:
std_logic_vector
(
31
downto
0
);
signal
post_samples_reg
:
std_logic_vector
(
31
downto
0
);
signal
ch1_ctl_ssr_reg
:
std_logic_vector
(
6
downto
0
);
...
...
@@ -247,7 +247,7 @@ begin
fmc_adc_100ms_csr_o
.
trig_pol_ch4
<=
trig_pol_ch4_reg
;
fmc_adc_100ms_csr_o
.
ext_trig_dly
<=
ext_trig_dly_reg
;
fmc_adc_100ms_csr_o
.
shots_nbr
<=
shots_nbr_reg
;
fmc_adc_100ms_csr_o
.
undersample
<=
under
sample_reg
;
fmc_adc_100ms_csr_o
.
downsample
<=
down
sample_reg
;
fmc_adc_100ms_csr_o
.
pre_samples
<=
pre_samples_reg
;
fmc_adc_100ms_csr_o
.
post_samples
<=
post_samples_reg
;
fmc_adc_100ms_csr_o
.
ch1_ctl_ssr
<=
ch1_ctl_ssr_reg
;
...
...
@@ -311,7 +311,7 @@ begin
ext_trig_dly_reg
<=
"00000000000000000000000000000000"
;
fmc_adc_100ms_csr_o
.
sw_trig_wr
<=
'0'
;
shots_nbr_reg
<=
"0000000000000000"
;
under
sample_reg
<=
"00000000000000000000000000000000"
;
down
sample_reg
<=
"00000000000000000000000000000000"
;
pre_samples_reg
<=
"00000000000000000000000000000000"
;
post_samples_reg
<=
"00000000000000000000000000000000"
;
ch1_ctl_ssr_reg
<=
"0000000"
;
...
...
@@ -420,9 +420,9 @@ begin
when
"0001010"
=>
-- Register fs_freq
when
"0001011"
=>
-- Register
under
sample
-- Register
down
sample
if
wr_int
=
'1'
then
under
sample_reg
<=
wb_i
.
dat
;
down
sample_reg
<=
wb_i
.
dat
;
end
if
;
wr_ack_int
<=
wr_int
;
when
"0001100"
=>
...
...
@@ -667,8 +667,8 @@ begin
reg_rdat_int
<=
fmc_adc_100ms_csr_i
.
fs_freq
;
rd_ack1_int
<=
rd_int
;
when
"0001011"
=>
--
under
sample
reg_rdat_int
<=
under
sample_reg
;
--
down
sample
reg_rdat_int
<=
down
sample_reg
;
rd_ack1_int
<=
rd_int
;
when
"0001100"
=>
-- pre_samples
...
...
@@ -844,7 +844,7 @@ begin
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"0001011"
=>
--
under
sample
--
down
sample
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"0001100"
=>
...
...
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @
3bf751db
...
...
@@ -88,7 +88,7 @@
`define
ADDR_FMC_ADC_100MS_CSR_MULTI_DEPTH
'
h20
`define
ADDR_FMC_ADC_100MS_CSR_TRIG_POS
'
h24
`define
ADDR_FMC_ADC_100MS_CSR_FS_FREQ
'
h28
`define
ADDR_FMC_ADC_100MS_CSR_
UNDER
SAMPLE
'
h2c
`define
ADDR_FMC_ADC_100MS_CSR_
DOWN
SAMPLE
'
h2c
`define
ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
'
h30
`define
ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
'
h34
`define
ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT
'
h38
...
...
software/include/hw/fmc_adc_100Ms_csr.h
View file @
3bf751db
...
...
@@ -77,8 +77,8 @@
/* Sampling clock frequency */
#define FMC_ADC_100MS_CSR_FS_FREQ 0x28UL
/*
Under
sampling ratio */
#define FMC_ADC_100MS_CSR_
UNDER
SAMPLE 0x2cUL
/*
Down
sampling ratio */
#define FMC_ADC_100MS_CSR_
DOWN
SAMPLE 0x2cUL
/* Pre-trigger samples */
#define FMC_ADC_100MS_CSR_PRE_SAMPLES 0x30UL
...
...
@@ -251,8 +251,8 @@ struct fmc_adc_100ms_csr {
/* [0x28]: REG (ro) Sampling clock frequency */
uint32_t
fs_freq
;
/* [0x2c]: REG (rw)
Under
sampling ratio */
uint32_t
under
sample
;
/* [0x2c]: REG (rw)
Down
sampling ratio */
uint32_t
down
sample
;
/* [0x30]: REG (rw) Pre-trigger samples */
uint32_t
pre_samples
;
...
...
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