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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
1a901c7b
Commit
1a901c7b
authored
Jan 30, 2014
by
Matthieu Cattin
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doc: Change fmc_adc_eic description.
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aa03f438
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fmc_adc_eic.h
hdl/adc/wb_gen/fmc_adc_eic.h
+11
-11
fmc_adc_eic.htm
hdl/adc/wb_gen/fmc_adc_eic.htm
+12
-12
fmc_adc_eic.wb
hdl/adc/wb_gen/fmc_adc_eic.wb
+2
-2
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hdl/adc/wb_gen/fmc_adc_eic.h
View file @
1a901c7b
/*
Register definitions for slave core: Fmc-adc e
nhanc
ed interrupt controller
Register definitions for slave core: Fmc-adc e
mbedd
ed interrupt controller
* File : fmc_adc_eic.h
* Author : auto-generated by wbgen2 from fmc_adc_eic.wb
* Created : Wed
Dec 4 09:44:26 2013
* Created : Wed
Jan 22 11:18:26 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_eic.wb
...
...
@@ -34,36 +34,36 @@
/* definitions for register: Interrupt disable register */
/* definitions for field: Trigger interrupt in reg: Interrupt disable register */
#define
EIC_EIC_IDR_TRIG
WBGEN2_GEN_MASK(0, 1)
#define
FMC_ADC_EIC_EIC_IDR_TRIG
WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt disable register */
#define
EIC_EIC_IDR_ACQ_END
WBGEN2_GEN_MASK(1, 1)
#define
FMC_ADC_EIC_EIC_IDR_ACQ_END
WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Trigger interrupt in reg: Interrupt enable register */
#define
EIC_EIC_IER_TRIG
WBGEN2_GEN_MASK(0, 1)
#define
FMC_ADC_EIC_EIC_IER_TRIG
WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt enable register */
#define
EIC_EIC_IER_ACQ_END
WBGEN2_GEN_MASK(1, 1)
#define
FMC_ADC_EIC_EIC_IER_ACQ_END
WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Trigger interrupt in reg: Interrupt mask register */
#define
EIC_EIC_IMR_TRIG
WBGEN2_GEN_MASK(0, 1)
#define
FMC_ADC_EIC_EIC_IMR_TRIG
WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt mask register */
#define
EIC_EIC_IMR_ACQ_END
WBGEN2_GEN_MASK(1, 1)
#define
FMC_ADC_EIC_EIC_IMR_ACQ_END
WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Trigger interrupt in reg: Interrupt status register */
#define
EIC_EIC_ISR_TRIG
WBGEN2_GEN_MASK(0, 1)
#define
FMC_ADC_EIC_EIC_ISR_TRIG
WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt status register */
#define
EIC_EIC_ISR_ACQ_END
WBGEN2_GEN_MASK(1, 1)
#define
FMC_ADC_EIC_EIC_ISR_ACQ_END
WBGEN2_GEN_MASK(1, 1)
PACKED
struct
EIC_WB
{
PACKED
struct
FMC_ADC_
EIC_WB
{
/* [0x0]: REG Interrupt disable register */
uint32_t
EIC_IDR
;
/* [0x4]: REG Interrupt enable register */
...
...
hdl/adc/wb_gen/fmc_adc_eic.htm
View file @
1a901c7b
...
...
@@ -28,8 +28,8 @@
</HEAD>
<BODY>
<h1
class=
"heading"
>
fmc_adc_eic
</h1>
<h3>
Fmc-adc e
nhanc
ed interrupt controller
</h3>
<p>
E
nhanc
ed interrrupt controller for one fmc-adc mezzanine.
</p>
<h3>
Fmc-adc e
mbedd
ed interrupt controller
</h3>
<p>
E
mbedd
ed interrrupt controller for one fmc-adc mezzanine.
</p>
<h3>
Contents:
</h3>
<span
style=
"margin-left: 0px; "
>
1.
<A
href=
"#sect_1_0"
>
Memory map summary
</a></span><br/>
<span
style=
"margin-left: 0px; "
>
2.
<A
href=
"#sect_2_0"
>
HDL symbol
</a></span><br/>
...
...
@@ -71,7 +71,7 @@ REG
<A
href=
"#EIC_IDR"
>
Interrupt disable register
</a>
</td>
<td
class=
"td_code"
>
eic_eic_idr
fmc_adc_
eic_eic_idr
</td>
<td
class=
"td_code"
>
EIC_IDR
...
...
@@ -88,7 +88,7 @@ REG
<A
href=
"#EIC_IER"
>
Interrupt enable register
</a>
</td>
<td
class=
"td_code"
>
eic_eic_ier
fmc_adc_
eic_eic_ier
</td>
<td
class=
"td_code"
>
EIC_IER
...
...
@@ -105,7 +105,7 @@ REG
<A
href=
"#EIC_IMR"
>
Interrupt mask register
</a>
</td>
<td
class=
"td_code"
>
eic_eic_imr
fmc_adc_
eic_eic_imr
</td>
<td
class=
"td_code"
>
EIC_IMR
...
...
@@ -122,7 +122,7 @@ REG
<A
href=
"#EIC_ISR"
>
Interrupt status register
</a>
</td>
<td
class=
"td_code"
>
eic_eic_isr
fmc_adc_
eic_eic_isr
</td>
<td
class=
"td_code"
>
EIC_ISR
...
...
@@ -347,7 +347,7 @@ wb_int_o
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
eic_eic_idr
fmc_adc_
eic_eic_idr
</td>
</tr>
<tr>
...
...
@@ -612,7 +612,7 @@ ACQ_END
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
eic_eic_ier
fmc_adc_
eic_eic_ier
</td>
</tr>
<tr>
...
...
@@ -877,7 +877,7 @@ ACQ_END
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
eic_eic_imr
fmc_adc_
eic_eic_imr
</td>
</tr>
<tr>
...
...
@@ -1142,7 +1142,7 @@ ACQ_END
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
eic_eic_isr
fmc_adc_
eic_eic_isr
</td>
</tr>
<tr>
...
...
@@ -1410,7 +1410,7 @@ ACQ_END
<b>
HW prefix:
</b>
</td>
<td
>
eic_trig
fmc_adc_
eic_trig
</td>
</tr>
<tr>
...
...
@@ -1439,7 +1439,7 @@ rising edge
<b>
HW prefix:
</b>
</td>
<td
>
eic_acq_end
fmc_adc_
eic_acq_end
</td>
</tr>
<tr>
...
...
hdl/adc/wb_gen/fmc_adc_eic.wb
View file @
1a901c7b
peripheral {
name = "Fmc-adc e
nhanc
ed interrupt controller";
description = "E
nhanc
ed interrrupt controller for one fmc-adc mezzanine.";
name = "Fmc-adc e
mbedd
ed interrupt controller";
description = "E
mbedd
ed interrrupt controller for one fmc-adc mezzanine.";
hdl_entity = "fmc_adc_eic";
prefix = "fmc_adc_eic";
...
...
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