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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
1834a7e3
Commit
1834a7e3
authored
Jul 19, 2013
by
Matthieu Cattin
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sim, git: Update spec simulation files and gitignore.
parent
8d9629a4
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Showing
5 changed files
with
98 additions
and
58 deletions
+98
-58
.gitignore
.gitignore
+2
-0
cmd0.vec
hdl/spec/sim/cmd0.vec
+18
-11
spec.do
hdl/spec/sim/spec.do
+2
-2
tb_spec.vhd
hdl/spec/sim/testbench/tb_spec.vhd
+40
-40
wave_end_acq_irq.do
hdl/spec/sim/wave_end_acq_irq.do
+36
-5
No files found.
.gitignore
View file @
1834a7e3
...
...
@@ -2,6 +2,8 @@ hdl/ip_cores/ddr3-sp6-core/
hdl/ip_cores/general-cores/
hdl/ip_cores/gn4124-core/
hdl/ip_cores/vme64x-core/
hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/syn/_ngo/
...
...
hdl/spec/sim/cmd0.vec
View file @
1834a7e3
...
...
@@ -214,6 +214,9 @@ wait %d100
wr FF00000000001A00 F 0000000A
wait %d100
-- irq mask
wr FF00000000001508 F 0000000F
-- trigger config (sw trig enable)
wr FF00000000001908 F 00000008
-- trigger config (hw int trig enable)
...
...
@@ -226,13 +229,13 @@ wr FF00000000001908 F 00000008
wr FF0000000000191C F 00000001
-- pre-trig samples
wr FF00000000001920 F 00000
00A
wr FF00000000001920 F 00000
100
-- post-trig samples
wr FF00000000001924 F 0000
01
00
wr FF00000000001924 F 0000
10
00
-- number of shots
wr FF00000000001914 F 0000000
3
wr FF00000000001914 F 0000000
1
-- Channel 1 gain
wr FF00000000001934 F 00008000
...
...
@@ -255,31 +258,35 @@ wr FF00000000001964 F 00008000
wr FF00000000001968 F 00000000
-- Enable test data and sampling clock
wr FF00000000001900 F 00000024
--
wr FF00000000001900 F 00000024
-- Enable sampling clock
--
wr FF00000000001900 F 00000004
wr FF00000000001900 F 00000004
-- start acquisition
wr FF00000000001900 F 00000025
--
wr FF00000000001900 F 00000005
--
wr FF00000000001900 F 00000025
wr FF00000000001900 F 00000005
wait %d800
-- sw trigger
wr FF00000000001910 F FFFFFFFF
wait %d800
-- stop acquisition
wr FF00000000001900 F 00000006
wait %d800
-- sw trigger
wr FF00000000001910 F FFFFFFFF
--
wr FF00000000001910 F FFFFFFFF
wait %d800
-- sw trigger
wr FF00000000001910 F FFFFFFFF
--
wr FF00000000001910 F FFFFFFFF
--
wait %d800
wait %d800
-- sw trigger
--wr FF00000000001910 F FFFFFFFF
--
wait %d800
wait %d800
-- sw trigger
--wr FF00000000001910 F FFFFFFFF
...
...
hdl/spec/sim/spec.do
View file @
1834a7e3
...
...
@@ -5,9 +5,9 @@ log -r /*
##do wave_datapath.do
##do wave_multishot.do
##do wave_onewire.do
do wave_adc_core.do
##
do wave_adc_core.do
##do wave_gnum.do
##
do wave_end_acq_irq.do
do wave_end_acq_irq.do
##do wave_ddr_wb.do
view wave
...
...
hdl/spec/sim/testbench/tb_spec.vhd
View file @
1834a7e3
...
...
@@ -46,7 +46,7 @@ architecture TEST of TB_SPEC is
generic
(
STRING_MAX
:
integer
:
=
256
;
-- Command string maximum length
T_LCLK
:
time
:
=
5
ns
;
-- Local Bus Clock Period
T_LCLK
:
time
:
=
5
ns
;
-- Local Bus Clock Period
T_P2L_CLK_DLY
:
time
:
=
2
ns
;
-- Delay from LCLK to P2L_CLK
INSTANCE_LABEL
:
string
:
=
"GN412X_BFM"
;
-- Label string to be used as a prefix for messages from the model
MODE_PRIMARY
:
boolean
:
=
true
-- TRUE for BFM acting as GN412x, FALSE for BFM acting as the DUT
...
...
@@ -248,24 +248,24 @@ architecture TEST of TB_SPEC is
spi_cs_dac3_n_o
:
out
std_logic
;
-- SPI channel 3 offset DAC chip select (active low)
spi_cs_dac4_n_o
:
out
std_logic
;
-- SPI channel 4 offset DAC chip select (active low)
gpio_dac_clr_n_o
:
out
std_logic
;
-- offset DACs clear (active low)
gpio_led_
power
_o
:
out
std_logic
;
-- Mezzanine front panel power LED (PWR)
gpio_led_trig
ger_o
:
out
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 1 solid state relays control
gpio_ssr_ch2_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 2 solid state relays control
gpio_ssr_ch3_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 3 solid state relays control
gpio_ssr_ch4_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 4 solid state relays control
gpio_si570_oe_o
:
out
std_logic
;
-- Si570 (programmable oscillator) output enable
gpio_dac_clr_n_o
:
out
std_logic
;
-- offset DACs clear (active low)
gpio_led_
acq
_o
:
out
std_logic
;
-- Mezzanine front panel power LED (PWR)
gpio_led_trig
_o
:
out
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 1 solid state relays control
gpio_ssr_ch2_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 2 solid state relays control
gpio_ssr_ch3_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 3 solid state relays control
gpio_ssr_ch4_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 4 solid state relays control
gpio_si570_oe_o
:
out
std_logic
;
-- Si570 (programmable oscillator) output enable
si570_scl_b
:
inout
std_logic
;
-- I2C bus clock (Si570)
si570_sda_b
:
inout
std_logic
;
-- I2C bus data (Si570)
mezz_one_wire_b
:
inout
std_logic
;
-- 1-wire interface (DS18B20 thermometer + unique ID)
mezz_one_wire_b
:
inout
std_logic
;
-- 1-wire interface (DS18B20 thermometer + unique ID)
prsnt_m2c_n_i
:
in
std_logic
;
-- Mezzanine present (active low)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
-- Mezzanine system I2C data (EEPROM)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
-- Mezzanine system I2C data (EEPROM)
);
end
component
spec_top_fmc_adc_100Ms
;
...
...
@@ -334,11 +334,11 @@ architecture TEST of TB_SPEC is
-----------------------------------------------------------------------------
-- System signals
signal
clk20_vcxo_i
:
std_logic
:
=
'0'
;
-- 20MHz VCXO clock
signal
led_red_o
:
std_logic
;
signal
led_green_o
:
std_logic
;
signal
pcb_ver_i
:
std_logic_vector
(
3
downto
0
)
:
=
X"1"
;
signal
carrier_one_wire_b
:
std_logic
;
-- 1-wire interface (DS18B20)
signal
clk20_vcxo_i
:
std_logic
:
=
'0'
;
-- 20MHz VCXO clock
signal
led_red_o
:
std_logic
;
signal
led_green_o
:
std_logic
;
signal
pcb_ver_i
:
std_logic_vector
(
3
downto
0
)
:
=
X"1"
;
signal
carrier_one_wire_b
:
std_logic
;
-- 1-wire interface (DS18B20)
-- GN4124 interface
signal
RSTINn
:
std_logic
;
...
...
@@ -418,19 +418,19 @@ architecture TEST of TB_SPEC is
signal
spi_cs_dac3_n_o
:
std_logic
;
-- SPI channel 3 offset DAC chip select (active low)
signal
spi_cs_dac4_n_o
:
std_logic
;
-- SPI channel 4 offset DAC chip select (active low)
signal
gpio_dac_clr_n_o
:
std_logic
;
-- offset DACs clear (active low)
signal
gpio_led_
power
_o
:
std_logic
;
-- Mezzanine front panel power LED (PWR)
signal
gpio_led_trig
ger_o
:
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
signal
gpio_ssr_ch1_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 1 solid state relays control
signal
gpio_ssr_ch2_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 2 solid state relays control
signal
gpio_ssr_ch3_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 3 solid state relays control
signal
gpio_ssr_ch4_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 4 solid state relays control
signal
gpio_si570_oe_o
:
std_logic
;
-- Si570 (programmable oscillator) output enable
signal
gpio_dac_clr_n_o
:
std_logic
;
-- offset DACs clear (active low)
signal
gpio_led_
acq
_o
:
std_logic
;
-- Mezzanine front panel power LED (PWR)
signal
gpio_led_trig
_o
:
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
signal
gpio_ssr_ch1_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 1 solid state relays control
signal
gpio_ssr_ch2_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 2 solid state relays control
signal
gpio_ssr_ch3_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 3 solid state relays control
signal
gpio_ssr_ch4_o
:
std_logic_vector
(
6
downto
0
);
-- Channel 4 solid state relays control
signal
gpio_si570_oe_o
:
std_logic
;
-- Si570 (programmable oscillator) output enable
signal
si570_scl_b
:
std_logic
;
-- I2C bus clock (Si570)
signal
si570_sda_b
:
std_logic
;
-- I2C bus data (Si570)
signal
mezz_one_wire_b
:
std_logic
;
-- 1-wire interface (DS18B20)
signal
mezz_one_wire_b
:
std_logic
;
-- 1-wire interface (DS18B20)
signal
prsnt_m2c_n_i
:
std_logic
:
=
'0'
;
-- Mezzanine present (active low)
...
...
@@ -580,12 +580,12 @@ begin
g_SIMULATION
=>
"TRUE"
,
g_CALIB_SOFT_IP
=>
"FALSE"
)
port
map
(
clk20_vcxo_i
=>
clk20_vcxo_i
,
led_red_o
=>
LED_RED
,
led_green_o
=>
LED_GREEN
,
aux_leds_o
=>
aux_leds_o
,
aux_buttons_i
=>
aux_buttons_i
,
pcb_ver_i
=>
pcb_ver_i
,
clk20_vcxo_i
=>
clk20_vcxo_i
,
led_red_o
=>
LED_RED
,
led_green_o
=>
LED_GREEN
,
aux_leds_o
=>
aux_leds_o
,
aux_buttons_i
=>
aux_buttons_i
,
pcb_ver_i
=>
pcb_ver_i
,
carrier_one_wire_b
=>
carrier_one_wire_b
,
-- GN4124 interface
...
...
@@ -636,14 +636,14 @@ begin
spi_cs_dac3_n_o
=>
spi_cs_dac3_n_o
,
spi_cs_dac4_n_o
=>
spi_cs_dac4_n_o
,
gpio_dac_clr_n_o
=>
gpio_dac_clr_n_o
,
gpio_led_
power_o
=>
gpio_led_power
_o
,
gpio_led_trig
ger_o
=>
gpio_led_trigger
_o
,
gpio_ssr_ch1_o
=>
gpio_ssr_ch1_o
,
gpio_ssr_ch2_o
=>
gpio_ssr_ch2_o
,
gpio_ssr_ch3_o
=>
gpio_ssr_ch3_o
,
gpio_ssr_ch4_o
=>
gpio_ssr_ch4_o
,
gpio_si570_oe_o
=>
gpio_si570_oe_o
,
gpio_dac_clr_n_o
=>
gpio_dac_clr_n_o
,
gpio_led_
acq_o
=>
gpio_led_acq
_o
,
gpio_led_trig
_o
=>
gpio_led_trig
_o
,
gpio_ssr_ch1_o
=>
gpio_ssr_ch1_o
,
gpio_ssr_ch2_o
=>
gpio_ssr_ch2_o
,
gpio_ssr_ch3_o
=>
gpio_ssr_ch3_o
,
gpio_ssr_ch4_o
=>
gpio_ssr_ch4_o
,
gpio_si570_oe_o
=>
gpio_si570_oe_o
,
si570_scl_b
=>
si570_scl_b
,
si570_sda_b
=>
si570_sda_b
,
...
...
hdl/spec/sim/wave_end_acq_irq.do
View file @
1834a7e3
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-height 1
6 -radix hexadecimal} /tb_spec/ADC_DATA(1) {-height 16 -radix hexadecimal} /tb_spec/ADC_DATA(2) {-height 16 -radix hexadecimal} /tb_spec/ADC_DATA(3) {-height 16
-radix hexadecimal}} /tb_spec/ADC_DATA
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-height 1
7 -radix hexadecimal} /tb_spec/ADC_DATA(1) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(2) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(3) {-height 17
-radix hexadecimal}} /tb_spec/ADC_DATA
add wave -noupdate -divider {adc core}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_rst_n_i
...
...
@@ -27,15 +27,21 @@ add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_post_trig
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end_p_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_cnt
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
...
...
@@ -47,14 +53,38 @@ add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_count_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_full_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_led
add wave -noupdate -divider Multi-shot
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/multishot_buffer_sel
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_cnt
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_dina
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_dina
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_post_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addrb_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_doutb
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_doutb
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid_t
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_dout
add wave -noupdate -divider {ddr core}
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_full
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_empty
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_count
add wave -noupdate -divider irq
add wave -noupdate /tb_spec/U1/trigger_p
add wave -noupdate /tb_spec/U1/acq_end_p
add wave -noupdate /tb_spec/U1/acq_end_irq_p
add wave -noupdate /tb_spec/U1/acq_end
...
...
@@ -62,8 +92,9 @@ add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty_p
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty_d
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty
add wave -noupdate /tb_spec/U1/irq_sources(3)
add wave -noupdate /tb_spec/U1/irq_to_gn4124
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2
5017769 ps} 0} {{Cursor 2} {24288843
ps} 0}
WaveRestoreCursors {{Cursor 1} {2
7568195 ps} 0} {{Cursor 2} {15922570
ps} 0}
configure wave -namecolwidth 496
configure wave -valuecolwidth 172
configure wave -justifyvalue left
...
...
@@ -78,4 +109,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {
0 ps} {31500 n
s}
WaveRestoreZoom {
15798791 ps} {16099433 p
s}
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