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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
10d68343
Commit
10d68343
authored
Sep 18, 2013
by
Matthieu Cattin
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hdl: Adapt xwb_clock_crossing generic to general-cores proposed master branch.
parent
2f858137
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2 additions
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3 deletions
+2
-3
svec_top_fmc_adc_100Ms.vhd
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+1
-2
Manifest.py
hdl/svec/syn/Manifest.py
+1
-1
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hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @
10d68343
...
...
@@ -802,8 +802,7 @@ begin
-- Wishbone bus synchronisation from vme 62.5MHz clock to 125MHz system clock
cmp_xwb_clock_crossing
:
xwb_clock_crossing
generic
map
(
sync_depth
=>
3
,
log2fifo
=>
4
g_size
=>
16
)
port
map
(
slave_clk_i
=>
sys_clk_62_5
,
...
...
hdl/svec/syn/Manifest.py
View file @
10d68343
...
...
@@ -20,7 +20,7 @@ files = [
modules
=
{
"local"
:
[
"../rtl"
,
"../../adc/rtl"
,
"../../ip_cores/timetag_core/rtl"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git::
sdb_extension
"
,
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git::
proposed_master
"
,
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::svec_bank4_64b_32b_bank5_64b_32b"
,
"git://ohwr.org/hdl-core-lib/vme64x-core.git::master"
]}
...
...
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