hdl: further sanitise resets and switch the core to using synchronous resets (safer, easier to meet timing)

sim: Introduction of new, simpler testbench for FMC-ADC core, without any SPEC or SVEC specific details

hdl: fix bug where newly-arriving triggers could cause trigger delay logic to reset while counting for previous trigger

hdl: add bit to clear last trigger status, and prevent trigger status from updating when not in acquisition

hdl: removed carrier one-wire master (now handled by WR PTP core), introduced SPI Flash interface for WR PTP core, migrated all carrier HDL to 62.5MHz clock (FMC-ADC and DMA datapath still on 125MHz)

hdl: integrated WR PTP core (SPEC only for now), tested, works, need to review calibration procedure