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FMC ADC 100M 14b 4cha - Gateware
Commit 508b9f99 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: switch to records for wishbone interfaces

parent e7bcef61
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Showing with 178 additions and 297 deletions
general-cores @ 5c3207c0
Subproject commit 1a0f59f38dab795352f2f0093cec7bd81f465769
Subproject commit 5c3207c0ea2d6a0e83ab691817bd87b4a6bac896
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 508b9f99
......@@ -36,11 +36,14 @@ library work;
use work.timetag_core_pkg.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_100Ms_csr_wbgen2_pkg.all;
entity fmc_adc_100Ms_core is
generic(
g_multishot_ram_size : natural := 2048
g_MULTISHOT_RAM_SIZE : natural := 2048;
g_WB_CSR_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE
);
port (
-- Clock, reset
......@@ -48,25 +51,14 @@ entity fmc_adc_100Ms_core is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(7 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
wb_csr_slave_i : in t_wishbone_slave_in;
wb_csr_slave_o : out t_wishbone_slave_out;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
wb_ddr_clk_i : in std_logic;
wb_ddr_rst_n_i : in std_logic;
wb_ddr_master_i : in t_wishbone_master_data64_in;
wb_ddr_master_o : out t_wishbone_master_data64_out;
-- Events output pulses
trigger_p_o : out std_logic;
......@@ -368,8 +360,31 @@ architecture rtl of fmc_adc_100Ms_core is
signal acq_led : std_logic;
signal acq_led_man : std_logic;
-- from/to wb slave adapters
signal wb_csr_in : t_wishbone_slave_in;
signal wb_csr_out : t_wishbone_slave_out;
begin
------------------------------------------------------------------------------
-- WB slave adapters to/from the outside
------------------------------------------------------------------------------
cmp_csr_wb_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => TRUE,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => TRUE,
g_slave_mode => g_WB_CSR_MODE,
g_slave_granularity => g_WB_CSR_GRANULARITY)
port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
slave_i => wb_csr_slave_i,
slave_o => wb_csr_slave_o,
master_i => wb_csr_out,
master_o => wb_csr_in);
------------------------------------------------------------------------------
-- LEDs
......@@ -612,15 +627,15 @@ begin
port map(
rst_n_i => sys_rst_n_i,
clk_sys_i => sys_clk_i,
wb_adr_i => wb_csr_adr_i,
wb_dat_i => wb_csr_dat_i,
wb_dat_o => wb_csr_dat_o,
wb_cyc_i => wb_csr_cyc_i,
wb_sel_i => wb_csr_sel_i,
wb_stb_i => wb_csr_stb_i,
wb_we_i => wb_csr_we_i,
wb_ack_o => wb_csr_ack_o,
wb_stall_o => open,
wb_adr_i => wb_csr_in.adr(7 downto 0),
wb_dat_i => wb_csr_in.dat,
wb_dat_o => wb_csr_out.dat,
wb_cyc_i => wb_csr_in.cyc,
wb_sel_i => wb_csr_in.sel,
wb_stb_i => wb_csr_in.stb,
wb_we_i => wb_csr_in.we,
wb_ack_o => wb_csr_out.ack,
wb_stall_o => wb_csr_out.stall,
fs_clk_i => fs_clk,
regs_i => csr_regin,
regs_o => csr_regout);
......@@ -1589,43 +1604,43 @@ begin
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
p_wb_master : process (wb_ddr_clk_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
wb_ddr_stall_t <= '0';
elsif rising_edge(wb_ddr_clk_i) then
if wb_ddr_fifo_valid = '1' then --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
wb_ddr_stb_o <= '1';
wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_dat_o <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
if rising_edge(wb_ddr_clk_i) then
if wb_ddr_rst_n_i = '0' then
wb_ddr_master_o.cyc <= '0';
wb_ddr_master_o.we <= '0';
wb_ddr_master_o.stb <= '0';
wb_ddr_master_o.adr <= (others => '0');
wb_ddr_master_o.dat <= (others => '0');
wb_ddr_stall_t <= '0';
else
if wb_ddr_fifo_valid = '1' then
wb_ddr_master_o.stb <= '1';
wb_ddr_master_o.adr <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_master_o.dat <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
else
wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
end if;
else
wb_ddr_dat_o <= wb_ddr_fifo_dout(63 downto 0);
wb_ddr_master_o.stb <= '0';
end if;
else
wb_ddr_stb_o <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
--elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_master_o.cyc <= '1';
wb_ddr_master_o.we <= '1';
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_master_o.cyc <= '0';
wb_ddr_master_o.we <= '0';
end if;
wb_ddr_stall_t <= wb_ddr_stall_i;
wb_ddr_stall_t <= wb_ddr_master_i.stall;
end if;
end if;
end process p_wb_master;
wb_ddr_sel_o <= X"FF";
wb_ddr_master_o.sel <= X"FF";
end rtl;
hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ 508b9f99
......@@ -9,12 +9,11 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2012-11-16
-- Last update: 2018-10-26
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC 100Ms/s core.
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-- Copyright (c) 2011-2018 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
......@@ -37,7 +36,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
use work.wishbone_pkg.all;
package fmc_adc_100Ms_core_pkg is
......@@ -51,7 +50,11 @@ package fmc_adc_100Ms_core_pkg is
------------------------------------------------------------------------------
component fmc_adc_100Ms_core
generic(
g_multishot_ram_size : natural := 2048
g_MULTISHOT_RAM_SIZE : natural := 2048;
g_WB_CSR_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DDR_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_DDR_GRANULARITY : t_wishbone_address_granularity := BYTE
);
port (
-- Clock, reset
......@@ -59,25 +62,14 @@ package fmc_adc_100Ms_core_pkg is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(7 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
wb_csr_slave_i : in t_wishbone_slave_in;
wb_csr_slave_o : out t_wishbone_slave_out;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
wb_ddr_clk_i : in std_logic;
wb_ddr_rst_n_i : in std_logic;
wb_ddr_master_i : in t_wishbone_master_data64_in;
wb_ddr_master_o : out t_wishbone_master_data64_out;
-- Events output pulses
trigger_p_o : out std_logic;
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 508b9f99
......@@ -39,7 +39,7 @@ use work.timetag_core_pkg.all;
entity fmc_adc_mezzanine is
generic(
g_multishot_ram_size : natural := 2048
g_MULTISHOT_RAM_SIZE : natural := 2048
);
port (
-- Clock, reset
......@@ -47,26 +47,14 @@ entity fmc_adc_mezzanine is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(31 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
wb_csr_stall_o : out std_logic;
wb_csr_slave_i : in t_wishbone_slave_in;
wb_csr_slave_o : out t_wishbone_slave_out;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
wb_ddr_clk_i : in std_logic;
wb_ddr_rst_n_i : in std_logic;
wb_ddr_master_i : in t_wishbone_master_data64_in;
wb_ddr_master_o : out t_wishbone_master_data64_out;
-- Interrupts
ddr_wr_fifo_empty_i : in std_logic;
......@@ -148,8 +136,6 @@ architecture rtl of fmc_adc_mezzanine is
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
-- WARNING: All address in sdb and crossbar are BYTE addresses!
------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar
......@@ -247,10 +233,6 @@ architecture rtl of fmc_adc_mezzanine is
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- Wishbone bus from additional registers
signal xreg_slave_out : t_wishbone_slave_out;
signal xreg_slave_in : t_wishbone_slave_in;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
......@@ -300,8 +282,8 @@ begin
port map(
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
slave_i => xreg_slave_in,
slave_o => xreg_slave_out,
slave_i => wb_csr_slave_i,
slave_o => wb_csr_slave_o,
master_i => cnx_slave_out(c_WB_MASTER),
master_o => cnx_slave_in(c_WB_MASTER));
......@@ -321,18 +303,6 @@ begin
master_i => cnx_master_in,
master_o => cnx_master_out);
-- Connect crossbar slave port to entity port
xreg_slave_in.adr <= wb_csr_adr_i;
xreg_slave_in.dat <= wb_csr_dat_i;
xreg_slave_in.sel <= wb_csr_sel_i;
xreg_slave_in.stb <= wb_csr_stb_i;
xreg_slave_in.we <= wb_csr_we_i;
xreg_slave_in.cyc <= wb_csr_cyc_i;
wb_csr_dat_o <= xreg_slave_out.dat;
wb_csr_ack_o <= xreg_slave_out.ack;
wb_csr_stall_o <= xreg_slave_out.stall;
------------------------------------------------------------------------------
-- Mezzanine system managment I2C master
-- Access to mezzanine EEPROM
......@@ -451,30 +421,19 @@ begin
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map (
g_multishot_ram_size => g_multishot_ram_size
)
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE
)
port map(
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(9 downto 2), -- cnx_master_out.adr is byte address
wb_csr_dat_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_dat_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).cyc,
wb_csr_sel_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).sel,
wb_csr_stb_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).stb,
wb_csr_we_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).we,
wb_csr_ack_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).ack,
wb_ddr_clk_i => sys_clk_i,
wb_ddr_adr_o => wb_ddr_adr_o,
wb_ddr_dat_o => wb_ddr_dat_o,
wb_ddr_sel_o => wb_ddr_sel_o,
wb_ddr_stb_o => wb_ddr_stb_o,
wb_ddr_we_o => wb_ddr_we_o,
wb_ddr_cyc_o => wb_ddr_cyc_o,
wb_ddr_ack_i => wb_ddr_ack_i,
wb_ddr_stall_i => wb_ddr_stall_i,
wb_csr_slave_i => cnx_master_out(c_WB_SLAVE_FMC_ADC),
wb_csr_slave_o => cnx_master_in(c_WB_SLAVE_FMC_ADC),
wb_ddr_clk_i => wb_ddr_clk_i,
wb_ddr_rst_n_i => wb_ddr_rst_n_i,
wb_ddr_master_o => wb_ddr_master_o,
wb_ddr_master_i => wb_ddr_master_i,
trigger_p_o => trigger_p,
acq_start_p_o => acq_start_p,
......@@ -506,11 +465,6 @@ begin
gpio_si570_oe_o => gpio_si570_oe_o
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC_ADC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC_ADC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC_ADC).stall <= '0';
------------------------------------------------------------------------------
-- Mezzanine 1-wire master
-- DS18B20 (thermometer + unique ID)
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ 508b9f99
......@@ -8,12 +8,11 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-03
-- Last update: 2018-10-26
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC mezzanine
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-- Copyright (c) 2013-2018 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
......@@ -36,21 +35,16 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
use work.wishbone_pkg.all;
package fmc_adc_mezzanine_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component fmc_adc_mezzanine
generic(
g_multishot_ram_size : natural := 2048
g_MULTISHOT_RAM_SIZE : natural := 2048
);
port (
-- Clock, reset
......@@ -58,26 +52,14 @@ package fmc_adc_mezzanine_pkg is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(31 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
wb_csr_stall_o : out std_logic;
wb_csr_slave_i : in t_wishbone_slave_in;
wb_csr_slave_o : out t_wishbone_slave_out;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
wb_ddr_clk_i : in std_logic;
wb_ddr_rst_n_i : in std_logic;
wb_ddr_master_i : in t_wishbone_master_data64_in;
wb_ddr_master_o : out t_wishbone_master_data64_out;
-- Interrupt
ddr_wr_fifo_empty_i : in std_logic;
......
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ 508b9f99
......@@ -397,14 +397,8 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
signal wb_dma_rty : std_logic;
-- FMC ADC core to DDR wishbone bus
signal wb_ddr_adr : std_logic_vector(31 downto 0);
signal wb_ddr_dat_o : std_logic_vector(63 downto 0);
signal wb_ddr_sel : std_logic_vector(7 downto 0);
signal wb_ddr_cyc : std_logic;
signal wb_ddr_stb : std_logic;
signal wb_ddr_we : std_logic;
signal wb_ddr_ack : std_logic;
signal wb_ddr_stall : std_logic;
signal wb_ddr0_in : t_wishbone_master_data64_in;
signal wb_ddr0_out : t_wishbone_master_data64_out;
-- Interrupts stuff
signal dma_irq : std_logic_vector(1 downto 0);
......@@ -1005,25 +999,13 @@ begin
sys_clk_i => sys_clk_125,
sys_rst_n_i => fmc0_rst_n,
wb_csr_adr_i => cnx_fmc0_sync_master_out.adr,
wb_csr_dat_i => cnx_fmc0_sync_master_out.dat,
wb_csr_dat_o => cnx_fmc0_sync_master_in.dat,
wb_csr_cyc_i => cnx_fmc0_sync_master_out.cyc,
wb_csr_sel_i => cnx_fmc0_sync_master_out.sel,
wb_csr_stb_i => cnx_fmc0_sync_master_out.stb,
wb_csr_we_i => cnx_fmc0_sync_master_out.we,
wb_csr_ack_o => cnx_fmc0_sync_master_in.ack,
wb_csr_stall_o => cnx_fmc0_sync_master_in.stall,
wb_ddr_clk_i => sys_clk_125,
wb_ddr_adr_o => wb_ddr_adr,
wb_ddr_dat_o => wb_ddr_dat_o,
wb_ddr_sel_o => wb_ddr_sel,
wb_ddr_stb_o => wb_ddr_stb,
wb_ddr_we_o => wb_ddr_we,
wb_ddr_cyc_o => wb_ddr_cyc,
wb_ddr_ack_i => wb_ddr_ack,
wb_ddr_stall_i => wb_ddr_stall,
wb_csr_slave_i => cnx_fmc0_sync_master_out,
wb_csr_slave_o => cnx_fmc0_sync_master_in,
wb_ddr_clk_i => sys_clk_125,
wb_ddr_rst_n_i => fmc0_rst_n,
wb_ddr_master_i => wb_ddr0_in,
wb_ddr_master_o => wb_ddr0_out,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty,
trig_irq_o => trig_irq_p,
......@@ -1075,10 +1057,6 @@ begin
wr_enable_i => wrabbit_en
);
-- Unused wishbone signals
cnx_fmc0_sync_master_in.err <= '0';
cnx_fmc0_sync_master_in.rty <= '0';
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
......@@ -1122,15 +1100,15 @@ begin
wb0_rst_n_i => sys_rst_125_n,
wb0_clk_i => sys_clk_125,
wb0_sel_i => wb_ddr_sel,
wb0_cyc_i => wb_ddr_cyc,
wb0_stb_i => wb_ddr_stb,
wb0_we_i => wb_ddr_we,
wb0_addr_i => wb_ddr_adr,
wb0_data_i => wb_ddr_dat_o,
wb0_data_o => open,
wb0_ack_o => wb_ddr_ack,
wb0_stall_o => wb_ddr_stall,
wb0_sel_i => wb_ddr0_out.sel,
wb0_cyc_i => wb_ddr0_out.cyc,
wb0_stb_i => wb_ddr0_out.stb,
wb0_we_i => wb_ddr0_out.we,
wb0_addr_i => wb_ddr0_out.adr,
wb0_data_i => wb_ddr0_out.dat,
wb0_data_o => wb_ddr0_in.dat,
wb0_ack_o => wb_ddr0_in.ack,
wb0_stall_o => wb_ddr0_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
......@@ -1178,6 +1156,9 @@ begin
wb_dma_err <= '0';
wb_dma_rty <= '0';
wb_ddr0_in.err <= '0';
wb_ddr0_in.rty <= '0';
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 508b9f99
......@@ -483,23 +483,10 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
signal cnx_fmc1_sync_master_in : t_wishbone_master_in;
-- Wishbone buses from FMC ADC cores to DDR controller
signal wb_ddr0_adc_adr : std_logic_vector(31 downto 0);
signal wb_ddr0_adc_dat_o : std_logic_vector(63 downto 0);
signal wb_ddr0_adc_sel : std_logic_vector(7 downto 0);
signal wb_ddr0_adc_cyc : std_logic;
signal wb_ddr0_adc_stb : std_logic;
signal wb_ddr0_adc_we : std_logic;
signal wb_ddr0_adc_ack : std_logic;
signal wb_ddr0_adc_stall : std_logic;
signal wb_ddr1_adc_adr : std_logic_vector(31 downto 0);
signal wb_ddr1_adc_dat_o : std_logic_vector(63 downto 0);
signal wb_ddr1_adc_sel : std_logic_vector(7 downto 0);
signal wb_ddr1_adc_cyc : std_logic;
signal wb_ddr1_adc_stb : std_logic;
signal wb_ddr1_adc_we : std_logic;
signal wb_ddr1_adc_ack : std_logic;
signal wb_ddr1_adc_stall : std_logic;
signal wb_ddr0_in : t_wishbone_master_data64_in;
signal wb_ddr0_out : t_wishbone_master_data64_out;
signal wb_ddr1_in : t_wishbone_master_data64_in;
signal wb_ddr1_out : t_wishbone_master_data64_out;
-- Interrupts
signal ddr_wr_fifo_empty : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
......@@ -706,11 +693,7 @@ begin
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_slave_in(c_WB_MASTER_VME),
wb_i.ack => cnx_slave_out(c_WB_MASTER_VME).ack,
wb_i.err => cnx_slave_out(c_WB_MASTER_VME).err,
wb_i.rty => cnx_slave_out(c_WB_MASTER_VME).rty,
wb_i.stall => cnx_slave_out(c_WB_MASTER_VME).stall,
wb_i.dat => cnx_slave_out(c_WB_MASTER_VME).dat,
wb_i => cnx_slave_out(c_WB_MASTER_VME),
int_i => irq_to_vme);
......@@ -910,31 +893,19 @@ begin
cmp_fmc_adc_mezzanine_0 : fmc_adc_mezzanine
generic map(
g_multishot_ram_size => g_multishot_ram_size
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE
)
port map(
sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc0_rst_n,
wb_csr_adr_i => cnx_fmc0_sync_master_out.adr,
wb_csr_dat_i => cnx_fmc0_sync_master_out.dat,
wb_csr_dat_o => cnx_fmc0_sync_master_in.dat,
wb_csr_cyc_i => cnx_fmc0_sync_master_out.cyc,
wb_csr_sel_i => cnx_fmc0_sync_master_out.sel,
wb_csr_stb_i => cnx_fmc0_sync_master_out.stb,
wb_csr_we_i => cnx_fmc0_sync_master_out.we,
wb_csr_ack_o => cnx_fmc0_sync_master_in.ack,
wb_csr_stall_o => cnx_fmc0_sync_master_in.stall,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_adr_o => wb_ddr0_adc_adr,
wb_ddr_dat_o => wb_ddr0_adc_dat_o,
wb_ddr_sel_o => wb_ddr0_adc_sel,
wb_ddr_stb_o => wb_ddr0_adc_stb,
wb_ddr_we_o => wb_ddr0_adc_we,
wb_ddr_cyc_o => wb_ddr0_adc_cyc,
wb_ddr_ack_i => wb_ddr0_adc_ack,
wb_ddr_stall_i => wb_ddr0_adc_stall,
wb_csr_slave_i => cnx_fmc0_sync_master_out,
wb_csr_slave_o => cnx_fmc0_sync_master_in,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_rst_n_i => fmc0_rst_n,
wb_ddr_master_i => wb_ddr0_in,
wb_ddr_master_o => wb_ddr0_out,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty(0),
trig_irq_o => trig_irq_p(0),
......@@ -987,10 +958,6 @@ begin
);
-- Unused wishbone signals
cnx_fmc0_sync_master_in.err <= '0';
cnx_fmc0_sync_master_in.rty <= '0';
------------------------------------------------------------------------------
-- Slot 2 : FMC ADC mezzanine (wb bridge with cross-clocking)
-- Mezzanine system managment I2C master
......@@ -1017,31 +984,19 @@ begin
cmp_fmc_adc_mezzanine_1 : fmc_adc_mezzanine
generic map(
g_multishot_ram_size => g_multishot_ram_size
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE
)
port map(
sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc1_rst_n,
wb_csr_adr_i => cnx_fmc1_sync_master_out.adr,
wb_csr_dat_i => cnx_fmc1_sync_master_out.dat,
wb_csr_dat_o => cnx_fmc1_sync_master_in.dat,
wb_csr_cyc_i => cnx_fmc1_sync_master_out.cyc,
wb_csr_sel_i => cnx_fmc1_sync_master_out.sel,
wb_csr_stb_i => cnx_fmc1_sync_master_out.stb,
wb_csr_we_i => cnx_fmc1_sync_master_out.we,
wb_csr_ack_o => cnx_fmc1_sync_master_in.ack,
wb_csr_stall_o => cnx_fmc1_sync_master_in.stall,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_adr_o => wb_ddr1_adc_adr,
wb_ddr_dat_o => wb_ddr1_adc_dat_o,
wb_ddr_sel_o => wb_ddr1_adc_sel,
wb_ddr_stb_o => wb_ddr1_adc_stb,
wb_ddr_we_o => wb_ddr1_adc_we,
wb_ddr_cyc_o => wb_ddr1_adc_cyc,
wb_ddr_ack_i => wb_ddr1_adc_ack,
wb_ddr_stall_i => wb_ddr1_adc_stall,
wb_csr_slave_i => cnx_fmc1_sync_master_out,
wb_csr_slave_o => cnx_fmc1_sync_master_in,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_rst_n_i => fmc1_rst_n,
wb_ddr_master_i => wb_ddr1_in,
wb_ddr_master_o => wb_ddr1_out,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty(1),
trig_irq_o => trig_irq_p(1),
......@@ -1094,10 +1049,6 @@ begin
);
-- Unused wishbone signals
cnx_fmc1_sync_master_in.err <= '0';
cnx_fmc1_sync_master_in.rty <= '0';
------------------------------------------------------------------------------
-- DDR0 controller (bank 4)
------------------------------------------------------------------------------
......@@ -1140,15 +1091,15 @@ begin
wb0_rst_n_i => rst_ref_125m_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => wb_ddr0_adc_sel,
wb0_cyc_i => wb_ddr0_adc_cyc,
wb0_stb_i => wb_ddr0_adc_stb,
wb0_we_i => wb_ddr0_adc_we,
wb0_addr_i => wb_ddr0_adc_adr,
wb0_data_i => wb_ddr0_adc_dat_o,
wb0_data_o => open,
wb0_ack_o => wb_ddr0_adc_ack,
wb0_stall_o => wb_ddr0_adc_stall,
wb0_sel_i => wb_ddr0_out.sel,
wb0_cyc_i => wb_ddr0_out.cyc,
wb0_stb_i => wb_ddr0_out.stb,
wb0_we_i => wb_ddr0_out.we,
wb0_addr_i => wb_ddr0_out.adr,
wb0_data_i => wb_ddr0_out.dat,
wb0_data_o => wb_ddr0_in.dat,
wb0_ack_o => wb_ddr0_in.ack,
wb0_stall_o => wb_ddr0_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
......@@ -1190,6 +1141,9 @@ begin
);
wb_ddr0_in.err <= '0';
wb_ddr0_in.rty <= '0';
ddr0_calib_done <= ddr0_status(0);
-- DDR0 (bank 4) address counter
......@@ -1294,15 +1248,15 @@ begin
wb0_rst_n_i => rst_ref_125m_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => wb_ddr1_adc_sel,
wb0_cyc_i => wb_ddr1_adc_cyc,
wb0_stb_i => wb_ddr1_adc_stb,
wb0_we_i => wb_ddr1_adc_we,
wb0_addr_i => wb_ddr1_adc_adr,
wb0_data_i => wb_ddr1_adc_dat_o,
wb0_data_o => open,
wb0_ack_o => wb_ddr1_adc_ack,
wb0_stall_o => wb_ddr1_adc_stall,
wb0_sel_i => wb_ddr1_out.sel,
wb0_cyc_i => wb_ddr1_out.cyc,
wb0_stb_i => wb_ddr1_out.stb,
wb0_we_i => wb_ddr1_out.we,
wb0_addr_i => wb_ddr1_out.adr,
wb0_data_i => wb_ddr1_out.dat,
wb0_data_o => wb_ddr1_in.dat,
wb0_ack_o => wb_ddr1_in.ack,
wb0_stall_o => wb_ddr1_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
......@@ -1344,6 +1298,9 @@ begin
);
wb_ddr1_in.err <= '0';
wb_ddr1_in.rty <= '0';
ddr1_calib_done <= ddr1_status(0);
-- DDR1 (bank 5) address counter
......
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