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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
051e9b4c
Commit
051e9b4c
authored
Feb 26, 2018
by
Dimitris Lampridis
Committed by
Dimitris Lampridis
Oct 24, 2018
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hdl: remove ddr3_zio port, not used
parent
80f0b1f3
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6 changed files
with
1 addition
and
16 deletions
+1
-16
spec_top_fmc_adc_100Ms.vhd
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+0
-2
spec_top_fmc_adc_100Ms.ucf
hdl/spec/spec_top_fmc_adc_100Ms.ucf
+0
-2
main.sv
hdl/spec/testbench/top/main.sv
+1
-2
wave.do
hdl/spec/testbench/top/wave.do
+0
-2
svec_top_fmc_adc_100Ms.vhd
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+0
-4
svec_top_fmc_adc_100Ms.ucf
hdl/svec/svec_top_fmc_adc_100Ms.ucf
+0
-4
No files found.
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @
051e9b4c
...
...
@@ -128,7 +128,6 @@ entity spec_top_fmc_adc_100Ms is
DDR3_DQ
:
inout
std_logic_vector
(
15
downto
0
);
DDR3_A
:
out
std_logic_vector
(
13
downto
0
);
DDR3_BA
:
out
std_logic_vector
(
2
downto
0
);
DDR3_ZIO
:
inout
std_logic
;
DDR3_RZQ
:
inout
std_logic
;
-- SFP
...
...
@@ -1160,7 +1159,6 @@ begin
ddr3_clk_p_o
=>
DDR3_CK_P
,
ddr3_clk_n_o
=>
DDR3_CK_N
,
ddr3_rzq_b
=>
DDR3_RZQ
,
ddr3_zio_b
=>
DDR3_ZIO
,
wb0_rst_n_i
=>
sys_rst_125_n
,
wb0_clk_i
=>
sys_clk_125
,
...
...
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @
051e9b4c
...
...
@@ -439,8 +439,6 @@ NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
...
...
hdl/spec/testbench/top/main.sv
View file @
051e9b4c
...
...
@@ -43,7 +43,7 @@ module main;
wire
[
15
:
0
]
ddr_dq
;
wire
[
13
:
0
]
ddr_a
;
wire
[
2
:
0
]
ddr_ba
;
wire
ddr_
zio
,
ddr_
rzq
;
wire
ddr_rzq
;
wire
sfp_txp
,
sfp_txn
,
sfp_scl
,
sfp_sda
,
sfp_sda_en
;
pulldown
(
ddr_rzq
)
;
...
...
@@ -109,7 +109,6 @@ module main;
.
DDR3_DQ
(
ddr_dq
)
,
.
DDR3_A
(
ddr_a
)
,
.
DDR3_BA
(
ddr_ba
)
,
.
DDR3_ZIO
(
ddr_zio
)
,
.
DDR3_RZQ
(
ddr_rzq
)
,
...
...
hdl/spec/testbench/top/wave.do
View file @
051e9b4c
...
...
@@ -116,7 +116,6 @@ add wave -noupdate -group Top /main/DUT/DDR3_WE_N
add wave -noupdate -group Top /main/DUT/DDR3_DQ
add wave -noupdate -group Top /main/DUT/DDR3_A
add wave -noupdate -group Top /main/DUT/DDR3_BA
add wave -noupdate -group Top /main/DUT/DDR3_ZIO
add wave -noupdate -group Top /main/DUT/DDR3_RZQ
add wave -noupdate -group Top /main/DUT/adc0_ext_trigger_p_i
add wave -noupdate -group Top /main/DUT/adc0_ext_trigger_n_i
...
...
@@ -379,7 +378,6 @@ add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/ddr3_udqs_n_b
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/ddr3_clk_p_o
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/ddr3_clk_n_o
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/ddr3_rzq_b
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/ddr3_zio_b
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/wb0_clk_i
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/wb0_sel_i
add wave -noupdate -group DDRC /main/DUT/cmp_ddr_ctrl/wb0_cyc_i
...
...
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @
051e9b4c
...
...
@@ -169,7 +169,6 @@ entity svec_top_fmc_adc_100Ms is
ddr0_dq_b
:
inout
std_logic_vector
(
15
downto
0
);
ddr0_ba_o
:
out
std_logic_vector
(
2
downto
0
);
ddr0_a_o
:
out
std_logic_vector
(
13
downto
0
);
ddr0_zio_b
:
inout
std_logic
;
ddr0_rzq_b
:
inout
std_logic
;
------------------------------------------
...
...
@@ -192,7 +191,6 @@ entity svec_top_fmc_adc_100Ms is
ddr1_dq_b
:
inout
std_logic_vector
(
15
downto
0
);
ddr1_ba_o
:
out
std_logic_vector
(
2
downto
0
);
ddr1_a_o
:
out
std_logic_vector
(
13
downto
0
);
ddr1_zio_b
:
inout
std_logic
;
ddr1_rzq_b
:
inout
std_logic
;
------------------------------------------
...
...
@@ -1191,7 +1189,6 @@ begin
ddr3_clk_p_o
=>
ddr0_ck_p_o
,
ddr3_clk_n_o
=>
ddr0_ck_n_o
,
ddr3_rzq_b
=>
ddr0_rzq_b
,
ddr3_zio_b
=>
ddr0_zio_b
,
wb0_rst_n_i
=>
rst_ref_125m_n
,
wb0_clk_i
=>
clk_ref_125m
,
...
...
@@ -1348,7 +1345,6 @@ begin
ddr3_clk_p_o
=>
ddr1_ck_p_o
,
ddr3_clk_n_o
=>
ddr1_ck_n_o
,
ddr3_rzq_b
=>
ddr1_rzq_b
,
ddr3_zio_b
=>
ddr1_zio_b
,
wb0_rst_n_i
=>
rst_ref_125m_n
,
wb0_clk_i
=>
clk_ref_125m
,
...
...
hdl/svec/svec_top_fmc_adc_100Ms.ucf
View file @
051e9b4c
...
...
@@ -211,7 +211,6 @@ NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DDR0 (bank 4)
#----------------------------------------
NET "ddr0_zio_b" LOC = J6;
NET "ddr0_rzq_b" LOC = L7;
NET "ddr0_we_n_o" LOC = F4;
NET "ddr0_udqs_p_b" LOC = K2;
...
...
@@ -261,7 +260,6 @@ NET "ddr0_a_o[3]" LOC = E5;
NET "ddr0_a_o[2]" LOC = A3;
NET "ddr0_a_o[1]" LOC = D3;
NET "ddr0_a_o[0]" LOC = D4;
NET "ddr0_zio_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
...
...
@@ -315,7 +313,6 @@ NET "ddr0_a_o[0]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# DDR1 (bank 5)
#----------------------------------------
NET "ddr1_zio_b" LOC = L24;
NET "ddr1_rzq_b" LOC = G25;
NET "ddr1_we_n_o" LOC = E26;
NET "ddr1_udqs_p_b" LOC = K28;
...
...
@@ -365,7 +362,6 @@ NET "ddr1_a_o[3]" LOC = E29;
NET "ddr1_a_o[2]" LOC = C30;
NET "ddr1_a_o[1]" LOC = D30;
NET "ddr1_a_o[0]" LOC = D28;
NET "ddr1_zio_b" IOSTANDARD = "SSTL15_II";
NET "ddr1_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr1_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr1_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
...
...
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