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FMC ADC 100M 14b 4cha - Gateware
Commit 549db126 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: various fixes to WRPC and testbench update. Tested on SPEC, works.

parent fd95d097
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wr-cores @ 1e01c22d
Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
Subproject commit 1e01c22d441248dfd0206b754afb20af2cc08716
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 549db126
......@@ -139,7 +139,7 @@ entity spec_top_fmc_adc_100Ms is
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
......@@ -667,12 +667,12 @@ begin
sfp_rxp_i => sfp_rxp_i,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => open,
sfp_tx_disable_o => sfp_tx_disable_o,
pll_locked_o => pll_locked,
phy8_o => phy8_to_wrc,
phy8_i => phy8_from_wrc);
sfp_tx_disable_o <= '0';
sfp_rate_select_o <= '1';
------------------------------------------------------------------------------
-- System reset
......@@ -920,7 +920,8 @@ begin
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
led_act_o => led_red,
led_link_o => wrabbit_en);
led_link_o => led_green,
link_ok_o => wrabbit_en);
------------------------------------------------------------------------------
-- Carrier CSR
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 549db126
......@@ -20,24 +20,19 @@ NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
# !! SFP_TX_DISABLE and SFP_MOD_DEF1 are swapped in V1.1 schematics for control signals
#----------------------------------------
NET "SFP_RXN_I" LOC = C15;
NET "SFP_RXN_I" IOSTANDARD = "LVCMOS25";
NET "SFP_RXP_I" LOC = D15;
NET "SFP_RXP_I" IOSTANDARD = "LVCMOS25";
NET "SFP_TXN_O" LOC = A16;
NET "SFP_TXN_O" IOSTANDARD = "LVCMOS25";
NET "SFP_TXP_O" LOC = B16;
NET "SFP_TXP_O" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_B" LOC = C17;
NET "SFP_MOD_DEF1_B" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_I" LOC = G15;
NET "SFP_MOD_DEF0_I" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_B" LOC = G16;
NET "SFP_MOD_DEF2_B" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_B" LOC = H14;
NET "SFP_RATE_SELECT_B" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_O" LOC = H14;
NET "SFP_RATE_SELECT_O" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_I" LOC = B18;
NET "SFP_TX_FAULT_I" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_O" LOC = F17;
......@@ -583,6 +578,11 @@ NET "DDR3_UDQS_N" IN_TERM = NONE;
# Timing constraints
#===============================================================================
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
......@@ -592,15 +592,15 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
#NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
#TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "cmp_xwrc_platform_xilinx/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_platform_xilinx/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_platform_xilinx_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_platform_xilinx/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "adc0_dco_n_i" TNM_NET = adc_dco_n_i;
TIMESPEC TS_adc_dco_n_i = PERIOD "adc_dco_n_i" 2.5 ns HIGH 50%;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
#TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
NET "ddr_clk_buf" TNM_NET = ddr_clk;
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
......
hdl/spec/testbench/top/Manifest.py
View file @ 549db126
......@@ -7,6 +7,7 @@ syn_device="xc6slx45t"
include_dirs=["../include","gn4124_bfm", "ddr3"]
files = [
"sfp_i2c_adapter.vhd",
"main.sv",
"ddr3/ddr3.v"]
......
hdl/spec/testbench/top/main.sv
View file @ 549db126
......@@ -44,9 +44,23 @@ module main;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_zio, ddr_rzq;
wire sfp_txp, sfp_txn, sfp_scl, sfp_sda, sfp_sda_en;
pulldown(ddr_rzq);
sfp_i2c_adapter
SFP_I2C (
.clk_i(clk_125m_pllref_p),
.rst_n_i(1'b1),
.scl_i(sfp_scl),
.sda_i(sfp_sda),
.sda_en_o(sfp_sda_en),
.sfp_det_valid_i(1'b1),
.sfp_data_i(128'h0123456789ABCDEF0123456789ABCDEF)
);
assign sfp_sda = (sfp_sda_en) ? 1'b0:1'bz;
spec_top_fmc_adc_100Ms
#(
.g_simulation(1),
......@@ -59,6 +73,15 @@ module main;
.clk_125m_pllref_n_i(clk_125m_pllref_n),
.clk_125m_gtp_p_i(clk_125m_gtp_p),
.clk_125m_gtp_n_i(clk_125m_gtp_n),
.sfp_txp_o(sfp_txp),
.sfp_txn_o(sfp_txn),
.sfp_rxp_i(sfp_txp),
.sfp_rxn_i(sfp_txn),
.sfp_los_i(1'b0),
.sfp_tx_fault_i(1'b0),
.sfp_mod_def0_i(1'b0),
.sfp_mod_def1_b(sfp_scl),
.sfp_mod_def2_b(sfp_sda),
.adc0_ext_trigger_p_i(ext_trig),
.adc0_ext_trigger_n_i(~ext_trig),
.adc0_dco_p_i(adc0_dco),
......
hdl/spec/testbench/top/run.do
View file @ 549db126
......@@ -3,6 +3,6 @@ set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 70us
run 10000us
wave zoomfull
radix -hexadecimal
hdl/spec/testbench/top/sfp_i2c_adapter.vhd 0 → 100644
View file @ 549db126
-------------------------------------------------------------------------------
-- Title : SFP I2C adapter for VFC-HD board
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : sfp_i2c_adapter.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-11-25
-- Last update: 2016-11-28
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Simple interface betweent the I2C master port of the WR PTP
-- core (used to retrieve the SFP configuration) and the parallel interface
-- provided by the VFC-HD board. Uses internally the I2C slave from
-- general-cores.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity sfp_i2c_adapter is
port (
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
sda_i : in std_logic;
sda_en_o : out std_logic;
-- HIGH if both of the following are true:
-- 1. SFP is detected (plugged in)
-- 2. The part number has been successfully read after the SFP detection
sfp_det_valid_i : in std_logic;
-- 16 byte vendor Part Number (PN)
-- (ASCII encoded, first character byte in bits 127 downto 120)
sfp_data_i : in std_logic_vector (127 downto 0)
);
end entity sfp_i2c_adapter;
architecture rtl of sfp_i2c_adapter is
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
-- 64-byte array representing the DDM serial ID area of the SFP management
type t_sfp_ddm_serial_id is array (0 to 63) of std_logic_vector(7 downto 0);
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal sfp_i2c_tx_byte : std_logic_vector(7 downto 0);
signal sfp_i2c_rx_byte : std_logic_vector(7 downto 0);
signal sfp_i2c_r_done : std_logic;
signal sfp_i2c_w_done : std_logic;
signal sfp_ddm_din : t_sfp_ddm_serial_id := (others => (others => '0'));
signal sfp_ddm_reg : t_sfp_ddm_serial_id := (others => (others => '0'));
signal sfp_ddm_addr : unsigned(5 downto 0);
signal sfp_ddm_sum : unsigned(7 downto 0);
begin -- architecture rtl
cmp_gc_i2c_slave : gc_i2c_slave
generic map (
g_auto_addr_ack => TRUE)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
scl_i => scl_i,
-- clock streching not implemented by module
scl_o => open,
scl_en_o => open,
sda_i => sda_i,
-- sda_o is not necessary, sda_en has all the info that we need
sda_o => open,
sda_en_o => sda_en_o,
-- standard SFP management I2C address
i2c_addr_i => "1010000",
-- no need to ACK, we use auto address ACK
-- and only use one byte writes
ack_i => '0',
tx_byte_i => sfp_i2c_tx_byte,
rx_byte_o => sfp_i2c_rx_byte,
-- we only care about r_done (new address)
-- and w_done (load next byte from serial_id)
i2c_sta_p_o => open,
i2c_sto_p_o => open,
addr_good_p_o => open,
r_done_p_o => sfp_i2c_r_done,
w_done_p_o => sfp_i2c_w_done,
op_o => open);
-- Populate the sfp_ddm Vendor PN using the sfp_data_i input
gen_sfp_ddm_data : for i in 0 to 15 generate
sfp_ddm_din(40+i) <= sfp_data_i(127-i*8 downto 120-i*8);
end generate gen_sfp_ddm_data;
-- Calculate CC_BASE for the last byte of the sfp_ddm.
-- We only sum the 16 bytes, all other bytes are zero anyway.
sfp_ddm_sum <=
(((unsigned(sfp_data_i(127 downto 120)) + unsigned(sfp_data_i(119 downto 112))) +
(unsigned(sfp_data_i(111 downto 104)) + unsigned(sfp_data_i(103 downto 96)))) +
((unsigned(sfp_data_i(95 downto 88)) + unsigned(sfp_data_i(87 downto 80))) +
(unsigned(sfp_data_i(79 downto 72)) + unsigned(sfp_data_i(71 downto 64))))) +
(((unsigned(sfp_data_i(63 downto 56)) + unsigned(sfp_data_i(55 downto 48))) +
(unsigned(sfp_data_i(47 downto 40)) + unsigned(sfp_data_i(39 downto 32)))) +
((unsigned(sfp_data_i(31 downto 24)) + unsigned(sfp_data_i(23 downto 16))) +
(unsigned(sfp_data_i(15 downto 8)) + unsigned(sfp_data_i(7 downto 0)))));
sfp_ddm_din(63) <= std_logic_vector(sfp_ddm_sum);
-- always offer to send the next byte pointed to by the address counter
sfp_i2c_tx_byte <= sfp_ddm_reg(to_integer(sfp_ddm_addr));
-- Drive the SFP DDM based on the r_done/w_done pulses
p_sfp_ddm_addr_counter : process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sfp_ddm_addr <= (others => '0');
sfp_ddm_reg <= (others => (others => '0'));
else
-- check valid flag to load DDM register
if sfp_det_valid_i = '1' then
sfp_ddm_reg <= sfp_ddm_din;
else
sfp_ddm_reg <= (others => (others => '0'));
end if;
if sfp_i2c_r_done = '1' then
-- update address pointer with new value
sfp_ddm_addr <= unsigned(sfp_i2c_rx_byte(5 downto 0));
elsif sfp_i2c_w_done = '1' then
-- increase address pointer
sfp_ddm_addr <= sfp_ddm_addr + 1;
end if;
end if;
end if;
end process p_sfp_ddm_addr_counter;
end architecture rtl;
hdl/spec/testbench/top/wave.do
View file @ 549db126
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group wrpc -group platform /main/DUT/cmp_xwrc_platform_xilinx/*
add wave -noupdate -group wrpc -group endpoint /main/DUT/cmp_xwrc_board_common/cmp_xwr_core/WRPC/U_Endpoint/U_Wrapped_Endpoint/*
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/clk_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/rst_n_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_irq_o
......@@ -76,7 +78,7 @@ add wave -noupdate -group Top /main/DUT/led_green_o
add wave -noupdate -group Top /main/DUT/aux_leds_o
#add wave -noupdate -group Top /main/DUT/aux_buttons_i
add wave -noupdate -group Top /main/DUT/pcb_ver_i
add wave -noupdate -group Top /main/DUT/carrier_one_wire_b
add wave -noupdate -group Top /main/DUT/carrier_onewire_b
add wave -noupdate -group Top /main/DUT/L_RST_N
add wave -noupdate -group Top /main/DUT/P2L_RDY
add wave -noupdate -group Top /main/DUT/P2L_CLKn
......
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