hdl: Fix ddr adr and data wb slave number, add carrier type generic, increment ddr address counter on cyc falling edge.

syn: Updated wbgen2 cores, new serdes clock pll feedback scheme, new memory mapping, new version of the ddr3 interface.

Serdes pll feedback is now cancelling the clock path delay.
See UG382 Spartan-6 FPGA Clocking Resources page 33.

spec -> feedback through a buffer.
svec -> direct feedback (without buffer).

The timetag core is meant to be shared between different carriers.