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FMC ADC 100M 14b 4cha - Gateware
Commit 2565e724 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Update wbgen2 and re-generate cores.

parent 414ece4f
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documentation/manuals/firmware/svec/carrier_csr.tex 0 → 100644
View file @ 2565e724
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{carrier} @tab
Carrier type and PCB version
@item @code{0x4} @tab
REG @tab
@code{stat} @tab
Status
@item @code{0x8} @tab
REG @tab
@code{ctrl} @tab
Control
@end multitable
@regsection @code{carrier} - Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/O @tab
@code{PCB_REV}
@tab @code{X} @tab
PCB revision
@item @code{15...5}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved register
@item @code{31...16}
@tab R/O @tab
@code{TYPE}
@tab @code{X} @tab
Carrier type
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pcb_rev} @tab Binary coded PCB layout revision.
@item @code{reserved} @tab Ignore on read, write with 0's.
@item @code{type} @tab Carrier type identifier@*1 = SPEC@*2 = SVEC@*3 = VFC@*4 = SPEXI
@end multitable
@regsection @code{stat} - Status
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{FMC0_PRES}
@tab @code{X} @tab
FMC 1 presence
@item @code{1}
@tab R/O @tab
@code{FMC1_PRES}
@tab @code{X} @tab
FMC 2 presence
@item @code{2}
@tab R/O @tab
@code{SYS_PLL_LCK}
@tab @code{X} @tab
System clock PLL status
@item @code{3}
@tab R/O @tab
@code{DDR0_CAL_DONE}
@tab @code{X} @tab
DDR3 bank 4 calibration status
@item @code{4}
@tab R/O @tab
@code{DDR1_CAL_DONE}
@tab @code{X} @tab
DDR3 bank 5 calibration status
@item @code{31...5}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_pres} @tab 0: FMC slot 1 is populated@*1: FMC slot 1 is not populated.
@item @code{fmc1_pres} @tab 0: FMC slot 2 is populated@*1: FMC slot 2 is not populated.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr0_cal_done} @tab 0: not done@*1: done.
@item @code{ddr1_cal_done} @tab 0: not done@*1: done.
@item @code{reserved} @tab Ignore on read, write with 0's.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{FP_LEDS_MAN}
@tab @code{0} @tab
Front panel LED manual control
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
documentation/manuals/firmware/svec/irq_controller.tex 0 → 100644
View file @ 2565e724
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0xc} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{FMC0_TRIG}
@tab @code{0} @tab
FMC slot 1 trigger interrupt
@item @code{1}
@tab W/O @tab
@code{FMC0_ACQ_END}
@tab @code{0} @tab
FMC slot 1 end of acquisition interrupt
@item @code{2}
@tab W/O @tab
@code{FMC1_TRIG}
@tab @code{0} @tab
FMC slot 2 trigger interrupt
@item @code{3}
@tab W/O @tab
@code{FMC1_ACQ_END}
@tab @code{0} @tab
FMC slot 2 end of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_trig} @tab write 1: disable interrupt 'FMC slot 1 trigger interrupt'@*write 0: no effect
@item @code{fmc0_acq_end} @tab write 1: disable interrupt 'FMC slot 1 end of acquisition interrupt'@*write 0: no effect
@item @code{fmc1_trig} @tab write 1: disable interrupt 'FMC slot 2 trigger interrupt'@*write 0: no effect
@item @code{fmc1_acq_end} @tab write 1: disable interrupt 'FMC slot 2 end of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IER} - Interrupt enable register
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{FMC0_TRIG}
@tab @code{0} @tab
FMC slot 1 trigger interrupt
@item @code{1}
@tab W/O @tab
@code{FMC0_ACQ_END}
@tab @code{0} @tab
FMC slot 1 end of acquisition interrupt
@item @code{2}
@tab W/O @tab
@code{FMC1_TRIG}
@tab @code{0} @tab
FMC slot 2 trigger interrupt
@item @code{3}
@tab W/O @tab
@code{FMC1_ACQ_END}
@tab @code{0} @tab
FMC slot 2 end of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_trig} @tab write 1: enable interrupt 'FMC slot 1 trigger interrupt'@*write 0: no effect
@item @code{fmc0_acq_end} @tab write 1: enable interrupt 'FMC slot 1 end of acquisition interrupt'@*write 0: no effect
@item @code{fmc1_trig} @tab write 1: enable interrupt 'FMC slot 2 trigger interrupt'@*write 0: no effect
@item @code{fmc1_acq_end} @tab write 1: enable interrupt 'FMC slot 2 end of acquisition interrupt'@*write 0: no effect
@end multitable
@regsection @code{EIC_IMR} - Interrupt mask register
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{FMC0_TRIG}
@tab @code{X} @tab
FMC slot 1 trigger interrupt
@item @code{1}
@tab R/O @tab
@code{FMC0_ACQ_END}
@tab @code{X} @tab
FMC slot 1 end of acquisition interrupt
@item @code{2}
@tab R/O @tab
@code{FMC1_TRIG}
@tab @code{X} @tab
FMC slot 2 trigger interrupt
@item @code{3}
@tab R/O @tab
@code{FMC1_ACQ_END}
@tab @code{X} @tab
FMC slot 2 end of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_trig} @tab read 1: interrupt 'FMC slot 1 trigger interrupt' is enabled@*read 0: interrupt 'FMC slot 1 trigger interrupt' is disabled
@item @code{fmc0_acq_end} @tab read 1: interrupt 'FMC slot 1 end of acquisition interrupt' is enabled@*read 0: interrupt 'FMC slot 1 end of acquisition interrupt' is disabled
@item @code{fmc1_trig} @tab read 1: interrupt 'FMC slot 2 trigger interrupt' is enabled@*read 0: interrupt 'FMC slot 2 trigger interrupt' is disabled
@item @code{fmc1_acq_end} @tab read 1: interrupt 'FMC slot 2 end of acquisition interrupt' is enabled@*read 0: interrupt 'FMC slot 2 end of acquisition interrupt' is disabled
@end multitable
@regsection @code{EIC_ISR} - Interrupt status register
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0_TRIG}
@tab @code{X} @tab
FMC slot 1 trigger interrupt
@item @code{1}
@tab R/W @tab
@code{FMC0_ACQ_END}
@tab @code{X} @tab
FMC slot 1 end of acquisition interrupt
@item @code{2}
@tab R/W @tab
@code{FMC1_TRIG}
@tab @code{X} @tab
FMC slot 2 trigger interrupt
@item @code{3}
@tab R/W @tab
@code{FMC1_ACQ_END}
@tab @code{X} @tab
FMC slot 2 end of acquisition interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_trig} @tab read 1: interrupt 'FMC slot 1 trigger interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'FMC slot 1 trigger interrupt'@*write 0: no effect
@item @code{fmc0_acq_end} @tab read 1: interrupt 'FMC slot 1 end of acquisition interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'FMC slot 1 end of acquisition interrupt'@*write 0: no effect
@item @code{fmc1_trig} @tab read 1: interrupt 'FMC slot 2 trigger interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'FMC slot 2 trigger interrupt'@*write 0: no effect
@item @code{fmc1_acq_end} @tab read 1: interrupt 'FMC slot 2 end of acquisition interrupt' is pending@*read 0: interrupt not pending@*write 1: clear interrupt 'FMC slot 2 end of acquisition interrupt'@*write 0: no effect
@end multitable
hdl/svec/rtl/carrier_csr.vhd
View file @ 2565e724
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/svec_carrier_csr.vhd
-- Author : auto-generated by wbgen2 from svec_carrier_csr.wb
-- Created : Fri Jul 5 10:44:08 2013
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue Jul 23 15:22:16 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_carrier_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......
hdl/svec/rtl/irq_controller.vhd
View file @ 2565e724
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller.vhd
-- Author : auto-generated by wbgen2 from irq_controller.wb
-- Created : Mon Jul 22 11:13:45 2013
-- Created : Tue Jul 23 15:22:16 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller.wb
......
hdl/svec/wb_gen/Makefile
View file @ 2565e724
WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
TEX=../../../documentation/manuals/firmware/
TEX=../../../documentation/manuals/firmware/svec/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
irq_controller_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
irq_controller:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
\ No newline at end of file
hdl/svec/wb_gen/carrier_csr.h
View file @ 2565e724
/*
Register definitions for slave core: SVEC carrier control and status registers
* File : svec_carrier_csr.h
* Author : auto-generated by wbgen2 from svec_carrier_csr.wb
* Created : Fri Jul 5 10:44:08 2013
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue Jul 23 15:22:16 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_carrier_csr.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SVEC_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_SVEC_CARRIER_CSR_WB
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#include <inttypes.h>
......
hdl/svec/wb_gen/irq_controller.h
View file @ 2565e724
......@@ -3,7 +3,7 @@
* File : irq_controller.h
* Author : auto-generated by wbgen2 from irq_controller.wb
* Created : Mon Jul 22 11:13:45 2013
* Created : Tue Jul 23 15:22:16 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller.wb
......
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