hdl: Add carrier type generic to fmc-adc core to select serdes pll feedback method.

spec -> feedback through a buffer. svec -> direct feedback (without buffer).

hdl: Add carrier type generic to fmc-adc core to select serdes pll feedback method.
spec -> feedback through a buffer. svec -> direct feedback (without buffer).
9837d5f9 · Matthieu Cattin · 74bb1049 · 9837d5f9 · 9837d5f9 · 9837d5f9
Commit 9837d5f9 authored Jul 17, 2013 by Matthieu Cattin
5 changed files
--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
@@ -50,7 +50,8 @@ use work.genram_pkg.all;

 entity fmc_adc_100Ms_core is
  generic(
-    g_multishot_ram_size : natural := 2048
+    g_multishot_ram_size : natural := 2048;
+    g_carrier_type : string := "SPEC"
    );
  port (
    -- Clock, reset
@@ -531,11 +532,22 @@ begin
      I => fs_clk_buf
      );

-  cmp_fb_clk_buf : BUFG
-    port map (
-      O => clk_fb,
-      I => clk_fb_buf
-      );
+  gen_fb_clk_check: if (g_carrier_type /= "SPEC" and
+                        g_carrier_type /= "SVEC") generate
+    assert false report "[fmc_adc_100Ms_core] Selected carrier type not supported. Must be SPEC or SVEC." severity failure;
+  end generate gen_fb_clk_check;
+
+  gen_fb_clk_spec: if g_carrier_type = "SPEC" generate
+    cmp_fb_clk_buf : BUFG
+      port map (
+        O => clk_fb,
+        I => clk_fb_buf
+        );
+  end generate gen_fb_clk_spec;
+
+  gen_fb_clk_svec: if g_carrier_type = "SVEC" generate
+        clk_fb <= clk_fb_buf;
+  end generate gen_fb_clk_svec;

  ------------------------------------------------------------------------------
  -- ADC data and frame SerDes

--- a/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
@@ -50,7 +50,8 @@ package fmc_adc_100Ms_core_pkg is
  ------------------------------------------------------------------------------
  component fmc_adc_100Ms_core
    generic(
-      g_multishot_ram_size : natural := 2048
+      g_multishot_ram_size : natural := 2048;
+      g_carrier_type : string := "SPEC"
      );
    port (
      -- Clock, reset

--- a/hdl/adc/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine.vhd
@@ -47,7 +47,8 @@ use work.wishbone_pkg.all;

 entity fmc_adc_mezzanine is
  generic(
-    g_multishot_ram_size : natural := 2048
+    g_multishot_ram_size : natural := 2048;
+    g_carrier_type : string := "SPEC"
    );
  port (
    -- Clock, reset
@@ -415,7 +416,8 @@ begin
  ------------------------------------------------------------------------------
  cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
    generic map (
-      g_multishot_ram_size => g_multishot_ram_size
+      g_multishot_ram_size => g_multishot_ram_size,
+      g_carrier_type => g_carrier_type
      )
    port map(
      sys_clk_i   => sys_clk_i,

--- a/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
@@ -50,7 +50,8 @@ package fmc_adc_mezzanine_pkg is
  ------------------------------------------------------------------------------
  component fmc_adc_mezzanine
    generic(
-      g_multishot_ram_size : natural := 2048
+      g_multishot_ram_size : natural := 2048;
+      g_carrier_type : string := "SPEC"
      );
    port (
      -- Clock, reset

--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -844,7 +844,8 @@ begin
  ------------------------------------------------------------------------------
  cmp_fmc_adc_mezzanine_0 : fmc_adc_mezzanine
    generic map(
-      g_multishot_ram_size => 2048
+      g_multishot_ram_size => 2048,
+      g_carrier_type => "SPEC"
      )
    port map(
      sys_clk_i   => sys_clk_125,