- 29 Jul, 2013 8 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
hdl: Fix ddr adr and data wb slave number, add carrier type generic, increment ddr address counter on cyc falling edge.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 26 Jul, 2013 2 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 25 Jul, 2013 1 commit
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Matthieu Cattin authored
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- 23 Jul, 2013 6 commits
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Matthieu Cattin authored
syn: Updated wbgen2 cores, new serdes clock pll feedback scheme, new memory mapping, new version of the ddr3 interface.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 19 Jul, 2013 4 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
Serdes pll feedback is now cancelling the clock path delay. See UG382 Spartan-6 FPGA Clocking Resources page 33.
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- 17 Jul, 2013 19 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
spec -> feedback through a buffer. svec -> direct feedback (without buffer).
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
The timetag core is meant to be shared between different carriers.
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Matthieu Cattin authored
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Matthieu Cattin authored
The ip_cores dir is meant to be shared between different carriers.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
The new module contains another wb crossbar. Therefore the memory mapping has changed. This has been done for the future svec design with two fmc slots.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
This solves the problem of trigger firing even when the data was below the threshold.
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Matthieu Cattin authored
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