@@ -190,7 +190,7 @@ The fmc-adc firmware depends on the following hdl cores and libraries:
This chapter describes the internal blocks of the FPGA.
All blocks (except the memory controller) are connected to the PCIe bridge interface using a Wishbone bus. The DDR memory can only be access through DMA.
The @ref{fig:firmware_arch} illustrates the FPGA architecture. The peripherals connected to each block are also shown.
The @ref{fig:spec_fw_arch} illustrates the FPGA architecture. The peripherals connected to each block are also shown.
A crossbar from the general-cores@footnote{@uref{http://www.ohwr.org/projects/general-cores}} library is used to map the Wishbone slaves in the BAR 0 address space.
The @ref{tab:memory_map} shows the Wishbone slaves mapping.
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@@ -244,8 +244,8 @@ OpenCores@footnote{@uref{http://opencores.org/}}. Therefore, the documentation f
The register description for the cores for the carrier control and status, the time-tagging core, the interrupt controller and the ADC core can be found in annexe (@xref{ADC Core Registers}, @ref{Interrupt Controller Registers}, @ref{Time-tagging Core Registers} and @ref{Carrier Registers}). The registers for those cores have been generated using @command{wbgen2}@footnote{@uref{http://www.ohwr.org/projects/wishbone-gen}}.
