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FMC ADC 100M 14b 4cha - Gateware
Commit 238666a4 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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initial port of SPEC REF to the Convention

parent d98dbd10
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.gitmodules
View file @ 238666a4
...@@ -13,3 +13,6 @@ ...@@ -13,3 +13,6 @@
[submodule "hdl/ip_cores/wr-cores"] [submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
ddr3-sp6-core @ 1a129390
Subproject commit bb5b8f75e6f85335b43fef320375404686a74008 Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores @ be61ce73
Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3 Subproject commit be61ce73a43d0231e8edc2f12133b918e3d1c9e4
gn4124-core @ 91d5efac
Subproject commit 72adf76dab9a6fc33fbff7c86d786c31e175a46a Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ 531dec91
Subproject commit 531dec9158aa05caa7aa10f91306999a39f3b1ef
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 238666a4
...@@ -119,9 +119,6 @@ entity fmc_adc_mezzanine is ...@@ -119,9 +119,6 @@ entity fmc_adc_mezzanine is
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID) mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i : in std_logic; -- WR link status bit wr_tm_link_up_i : in std_logic; -- WR link status bit
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
...@@ -234,14 +231,6 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -234,14 +231,6 @@ architecture rtl of fmc_adc_mezzanine is
signal wb_csr_out : t_wishbone_slave_in; signal wb_csr_out : t_wishbone_slave_in;
signal wb_csr_in : t_wishbone_slave_out; signal wb_csr_in : t_wishbone_slave_out;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
-- Mezzanine SPI -- Mezzanine SPI
signal spi_din_t : std_logic_vector(3 downto 0) := (others => '0'); signal spi_din_t : std_logic_vector(3 downto 0) := (others => '0');
signal spi_ss_t : std_logic_vector(7 downto 0); signal spi_ss_t : std_logic_vector(7 downto 0);
...@@ -349,20 +338,12 @@ begin ...@@ -349,20 +338,12 @@ begin
slave_o => cnx_slave_out(c_WB_SLAVE_FMC_SYS_I2C), slave_o => cnx_slave_out(c_WB_SLAVE_FMC_SYS_I2C),
desc_o => open, desc_o => open,
scl_pad_i(0) => sys_scl_in, scl_pad_i(0) => '1',
scl_pad_o(0) => sys_scl_out, scl_pad_o(0) => open,
scl_padoen_o(0) => sys_scl_oe_n, scl_padoen_o(0) => open,
sda_pad_i(0) => sys_sda_in, sda_pad_i(0) => '1',
sda_pad_o(0) => sys_sda_out, sda_pad_o(0) => open,
sda_padoen_o(0) => sys_sda_oe_n sda_padoen_o(0) => open);
);
-- Tri-state buffer for SDA and SCL
sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= sys_scl_b;
sys_sda_b <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
sys_sda_in <= sys_sda_b;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Mezzanine SPI master -- Mezzanine SPI master
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ 238666a4
...@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is ...@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID) mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i : in std_logic; -- WR link status bit wr_tm_link_up_i : in std_logic; -- WR link status bit
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
......
hdl/syn/spec_ref_design_wr/Manifest.py
View file @ 238666a4
...@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms" ...@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms"
syn_project = syn_top + "_wr.xise" syn_project = syn_top + "_wr.xise"
syn_tool = "ise" syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
files = [ files = [
syn_top + "_wr.ucf", syn_top + "_wr.ucf",
"buildinfo_pkg.vhd",
] ]
modules = { modules = {
"local" : [ "local" : [
"../../top/spec_ref_design" "../../top/spec_ref_design"
], ],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
],
} }
fetchto="../../ip_cores" # Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_64b_32b" ] syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd = ( spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \ ctrls = ["bank3_64b_32b" ]
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
hdl/top/spec_ref_design/Manifest.py
View file @ 238666a4
...@@ -4,8 +4,17 @@ files = [ ...@@ -4,8 +4,17 @@ files = [
"dma_eic.vhd", "dma_eic.vhd",
] ]
fetchto = "../../ip_cores"
modules = { modules = {
"local" : [ "local" : [
"../../../", "../../../",
], ],
"git" : [
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/spec.git",
],
} }
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