Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit d98dbd10 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

Merge branch 'feature/cheby' into proposed_master

parents 6c5b1142 d1834cdc
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 11633 additions and 31041 deletions
.gitignore
View file @ d98dbd10
......@@ -69,7 +69,6 @@ hdl/svec/sim/testbench/top/transcript
hdl/svec/sim/testbench/top/vsim.wlf
hdl/svec/sim/testbench/top/vsim_stacktrace.vstf
hdl/svec/sim/testbench/top/work/
doc/manual/*.html
doc/manual/fmcadc100m14b4cha_gateware_manual.info
doc/manual/fmcadc100m14b4cha_gateware_manual.pdf
doc/manual/fmcadc100m14b4cha_gateware_manual.txt
......
doc/manual/fmc_adc_100Ms_csr.html 0 → 100644
View file @ d98dbd10
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/rtl/wb_gen/fmc_adc_alt_trigin.html → doc/manual/fmc_adc_alt_trigin.html
View file @ d98dbd10
......@@ -2,53 +2,52 @@
<HEAD>
<TITLE>alt_trigin</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30;
color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22;
color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16;
color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right;
font-size:12;}
.td_arrow_right { padding:0px; background: #ffffff; text-align: left;
font-size:12;}
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0;
text-align: right; font-weight:bold;
padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0;
padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier;
background: #e0e0f0;
padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040;
font-size:10; width: 70px;
font-family:Courier New,Courier; padding: 3px;
text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center;
border: solid 1px black; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080;
padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30;
color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22;
color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16;
color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right;
font-size:12; }
.td_arrow_right { padding:0px; background: #ffffff; text-align: left;
font-size:12; }
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0;
text-align: right; font-weight:bold;
padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0;
padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier;
background: #e0e0f0;
padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040;
font-size:10; width: 70px;
font-family:Courier New,Courier; padding: 3px;
text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center;
border: solid 1px black; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080;
padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">alt_trigin</h1>
<h3>None</h3>
<h3>FMC ADC alt trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>H/W Address</th>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
......@@ -88,10 +87,10 @@
<a name="version"></a>
<h3><a name="sect_3_1">2.1. version</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_version</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">version</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x0</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Core version
......@@ -158,10 +157,10 @@ version
<a name="ctrl"></a>
<h3><a name="sect_3_2">2.2. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_ctrl</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x4</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Control register
......@@ -256,10 +255,10 @@ enable
<a name="seconds"></a>
<h3><a name="sect_3_3">2.3. seconds</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_seconds</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">seconds</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x8</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) to trigger
......@@ -378,10 +377,10 @@ seconds
<a name="cycles"></a>
<h3><a name="sect_3_4">2.4. cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_cycles</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">cycles</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x10</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time (cycles) to trigger
......
hdl/rtl/wb_gen/fmc_adc_alt_trigout.html → doc/manual/fmc_adc_alt_trigout.html
View file @ d98dbd10
......@@ -2,53 +2,52 @@
<HEAD>
<TITLE>alt_trigout</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30;
color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22;
color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16;
color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right;
font-size:12;}
.td_arrow_right { padding:0px; background: #ffffff; text-align: left;
font-size:12;}
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0;
text-align: right; font-weight:bold;
padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0;
padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier;
background: #e0e0f0;
padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040;
font-size:10; width: 70px;
font-family:Courier New,Courier; padding: 3px;
text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center;
border: solid 1px black; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080;
padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30;
color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22;
color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16;
color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right;
font-size:12; }
.td_arrow_right { padding:0px; background: #ffffff; text-align: left;
font-size:12; }
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0;
text-align: right; font-weight:bold;
padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0;
padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier;
background: #e0e0f0;
padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040;
font-size:10; width: 70px;
font-family:Courier New,Courier; padding: 3px;
text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center;
border: solid 1px black; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080;
padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">alt_trigout</h1>
<h3>None</h3>
<h3>FMC ADC alt trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>H/W Address</th>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
......@@ -81,10 +80,10 @@
<a name="status"></a>
<h3><a name="sect_3_1">2.1. status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_status</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">status</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x0</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Status register
......@@ -188,10 +187,10 @@ ts_present
<a name="ts_mask_sec"></a>
<h3><a name="sect_3_2">2.2. ts_mask_sec</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_ts_mask_sec</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x8</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) of the last event
......@@ -346,10 +345,10 @@ ext_mask
<a name="ts_cycles"></a>
<h3><a name="sect_3_3">2.3. ts_cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_ts_cycles</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x10</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Cycles part of timestamp fifo.
......
doc/manual/fmc_adc_aux_trigin.html 0 → 100644
View file @ d98dbd10
This diff is collapsed.
doc/manual/fmc_adc_aux_trigout.html 0 → 100644
View file @ d98dbd10
This diff is collapsed.
doc/manual/fmcadc100m14b4cha_gateware_manual.in
View file @ d98dbd10
......@@ -735,6 +735,13 @@ The frame rate signal is used to align the de-serialiser to data words.
The four channel data (16-bit) are concatenated together to form a 64-bit vector.
As shown in @ref{fig:ltc2174_mode}, the two LSB bits of a data word are always set to zero.
@strong{Important:} Upon reset the ADC defaults to ``offset binary''
representation for the channel data. However, the ADC core expects
``two's complement''. Therefore, it is important to change the
relevant configuration register in the ADC itself. When using the
provided FMC-ADC driver, this is done automatically during driver
initialisation.
@c ==========================================================================
@section Control and Status Registers
......
doc/manual/spec_carrier_csr.html 0 → 100644
View file @ d98dbd10
This diff is collapsed.
doc/manual/svec_carrier_csr.html 0 → 100644
View file @ d98dbd10
This diff is collapsed.
doc/manual/timetag_core_regs.html 0 → 100644
View file @ d98dbd10
This diff is collapsed.
general-cores @ eaacde90
Subproject commit 28cd756047ce9f85cf7c134367c7439f1189114d
Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3
hdl/rtl/Makefile 0 → 100644
View file @ d98dbd10
SIM =../testbench/include
DOC =../../doc/manual
SW =../../software/include/hw
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
hdl/rtl/Manifest.py
View file @ d98dbd10
......@@ -4,15 +4,10 @@ files = [
"fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_100Ms_csr_wbgen2_pkg.vhd",
"fmc_adc_alt_trigin.vhd",
"fmc_adc_alt_trigout.vhd",
"fmc_adc_aux_trigin.vhd",
"fmc_adc_aux_trigout.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd",
"timetag_core_regs.vhd",
"timetag_core.vhd",
]
modules = {
"local" : [
"timetag_core",
],
}
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ d98dbd10
......@@ -35,7 +35,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
use work.timetag_core_defs_pkg.all;
use work.wishbone_pkg.all;
package fmc_adc_100Ms_core_pkg is
......@@ -91,7 +91,7 @@ package fmc_adc_100Ms_core_pkg is
-- Trigger time-tag input
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
alt_time_trig_i : in std_logic;
aux_time_trig_i : in std_logic;
-- WR status (for trigout).
wr_tm_link_up_i : in std_logic;
......
hdl/rtl/fmc_adc_100Ms_csr.cheby 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/fmc_adc_100Ms_csr.vhd
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby → hdl/rtl/fmc_adc_aux_trigin.cheby
View file @ d98dbd10
memory-map:
bus: wb-32-be
name: alt_trigin
name: aux_trigin
description: FMC ADC aux trigger out registers
x-hdl:
busgroup: True
children:
......
hdl/rtl/fmc_adc_alt_trigin.vhd → hdl/rtl/fmc_adc_aux_trigin.vhd
View file @ d98dbd10
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_aux_trigin.cheby --gen-hdl=fmc_adc_aux_trigin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity alt_trigin is
entity aux_trigin is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -12,8 +15,6 @@ entity alt_trigin is
-- Enable trigger, cleared when triggered
ctrl_enable_i : in std_logic;
-- Enable trigger, cleared when triggered
ctrl_enable_o : out std_logic;
ctrl_wr_o : out std_logic;
......@@ -23,26 +24,48 @@ entity alt_trigin is
-- Time (cycles) to trigger
cycles_o : out std_logic_vector(31 downto 0)
);
end alt_trigin;
end aux_trigin;
architecture syn of alt_trigin is
signal wb_en : std_logic;
architecture syn of aux_trigin is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal ack_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal seconds_reg : std_logic_vector(63 downto 0);
signal cycles_reg : std_logic_vector(31 downto 0);
signal wr_ack_done_int : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
rd_int <= wb_en and not wb_i.we;
wr_int <= wb_en and wb_i.we;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
......@@ -54,71 +77,72 @@ begin
cycles_o <= cycles_reg;
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
wr_ack_done_int <= '0';
ctrl_wr_o <= '0';
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
cycles_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
ctrl_wr_o <= '0';
if wr_int = '1' then
-- Write in progress
wr_ack_done_int <= wr_ack_int or wr_ack_done_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
ctrl_wr_o <= '0';
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
cycles_reg <= "00000000000000000000000000000000";
else
wr_ack_int <= '0';
ctrl_wr_o <= '0';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register version
wr_ack_int <= not wr_ack_done_int;
when "1" =>
-- Register ctrl
ctrl_wr_o <= '1';
ctrl_enable_o <= wb_i.dat(0);
wr_ack_int <= not wr_ack_done_int;
ctrl_wr_o <= wr_int;
if wr_int = '1' then
ctrl_enable_o <= wb_i.dat(0);
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register seconds
seconds_reg(63 downto 32) <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
if wr_int = '1' then
seconds_reg(63 downto 32) <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "1" =>
-- Register seconds
seconds_reg(31 downto 0) <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
if wr_int = '1' then
seconds_reg(31 downto 0) <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register cycles
cycles_reg <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
if wr_int = '1' then
cycles_reg <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
wr_ack_int <= wr_int;
end case;
when others =>
wr_ack_int <= wr_int;
end case;
else
wr_ack_int <= '0';
wr_ack_done_int <= '0';
end if;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
elsif rising_edge(clk_i) then
if rd_int = '1' and rd_ack1_int = '0' then
rd_ack1_int <= '1';
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(4 downto 3) is
when "00" =>
......@@ -126,32 +150,43 @@ begin
when "0" =>
-- version
reg_rdat_int <= "10101101110000010000000000000001";
rd_ack1_int <= rd_int;
when "1" =>
-- ctrl
reg_rdat_int(0) <= ctrl_enable_i;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- seconds
reg_rdat_int <= seconds_reg(63 downto 32);
rd_ack1_int <= rd_int;
when "1" =>
-- seconds
reg_rdat_int <= seconds_reg(31 downto 0);
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- cycles
reg_rdat_int <= cycles_reg;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
else
rd_ack1_int <= '0';
end if;
end if;
end process;
......@@ -160,7 +195,6 @@ begin
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
rd_ack_int <= '1';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
......@@ -173,6 +207,7 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
......@@ -185,6 +220,7 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
......@@ -193,8 +229,10 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/timetag_core/Manifest.py deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core/timetag_core_pkg.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core/timetag_core_regs.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core/timetag_core_regs_wbgen2_pkg.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core/wb_gen/Makefile deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.h deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.htm deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core/wb_gen/timetag_core_regs.wb deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/timetag_core_regs.cheby 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/timetag_core_regs.vhd 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/wb_gen/Makefile
View file @ d98dbd10
This diff is collapsed.
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.h deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.htm deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.wb deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ d98dbd10
This diff is collapsed.
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ d98dbd10
This diff is collapsed.
hdl/testbench/include/fmc_adc_alt_trigin.v deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/testbench/include/fmc_adc_alt_trigout.v deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/testbench/include/fmc_adc_aux_trigin.v 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/testbench/include/fmc_adc_aux_trigout.v 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/testbench/include/spec_carrier_csr.v 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/testbench/include/svec_carrier_csr.v 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/testbench/include/timetag_core_regs.v
View file @ d98dbd10
This diff is collapsed.
hdl/testbench/svec_ref_design/main.sv
View file @ d98dbd10
This diff is collapsed.
hdl/top/spec_ref_design/Makefile 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/top/spec_ref_design/Manifest.py
View file @ d98dbd10
This diff is collapsed.
hdl/top/spec_ref_design/carrier_csr.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/spec_ref_design/carrier_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/spec_ref_design/spec_carrier_csr.cheby 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/top/spec_ref_design/spec_carrier_csr.vhd 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/top/spec_ref_design/wb_gen/Makefile
View file @ d98dbd10
This diff is collapsed.
hdl/top/spec_ref_design/wb_gen/carrier_csr.h deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/spec_ref_design/wb_gen/carrier_csr.htm deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/spec_ref_design/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/svec_ref_design/Makefile 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/top/svec_ref_design/Manifest.py
View file @ d98dbd10
This diff is collapsed.
hdl/top/svec_ref_design/carrier_csr.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/svec_ref_design/carrier_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/svec_ref_design/svec_carrier_csr.cheby 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/top/svec_ref_design/svec_carrier_csr.vhd 0 → 100644
View file @ d98dbd10
This diff is collapsed.
hdl/top/svec_ref_design/wb_gen/Makefile deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/svec_ref_design/wb_gen/carrier_csr.h deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/svec_ref_design/wb_gen/carrier_csr.htm deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
hdl/top/svec_ref_design/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ 6c5b1142
This diff is collapsed.
software/include/hw/fmc_adc_100Ms_csr.h 0 → 100644
View file @ d98dbd10
This diff is collapsed.
software/include/hw/spec_carrier_csr.h 0 → 100644
View file @ d98dbd10
This diff is collapsed.
software/include/hw/svec_carrier_csr.h 0 → 100644
View file @ d98dbd10
This diff is collapsed.
software/include/hw/timetag_core_regs.h 0 → 100644
View file @ d98dbd10
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment