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FMC ADC 100M 14b 4cha - Gateware
Commit 238666a4 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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initial port of SPEC REF to the Convention

parent d98dbd10
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.gitmodules
View file @ 238666a4
......@@ -13,3 +13,6 @@
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
ddr3-sp6-core @ 1a129390
Subproject commit bb5b8f75e6f85335b43fef320375404686a74008
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores @ be61ce73
Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3
Subproject commit be61ce73a43d0231e8edc2f12133b918e3d1c9e4
gn4124-core @ 91d5efac
Subproject commit 72adf76dab9a6fc33fbff7c86d786c31e175a46a
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ 531dec91
Subproject commit 531dec9158aa05caa7aa10f91306999a39f3b1ef
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 238666a4
......@@ -119,9 +119,6 @@ entity fmc_adc_mezzanine is
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i : in std_logic; -- WR link status bit
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
......@@ -234,14 +231,6 @@ architecture rtl of fmc_adc_mezzanine is
signal wb_csr_out : t_wishbone_slave_in;
signal wb_csr_in : t_wishbone_slave_out;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
-- Mezzanine SPI
signal spi_din_t : std_logic_vector(3 downto 0) := (others => '0');
signal spi_ss_t : std_logic_vector(7 downto 0);
......@@ -349,20 +338,12 @@ begin
slave_o => cnx_slave_out(c_WB_SLAVE_FMC_SYS_I2C),
desc_o => open,
scl_pad_i(0) => sys_scl_in,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => sys_sda_in,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= sys_scl_b;
sys_sda_b <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
sys_sda_in <= sys_sda_b;
scl_pad_i(0) => '1',
scl_pad_o(0) => open,
scl_padoen_o(0) => open,
sda_pad_i(0) => '1',
sda_pad_o(0) => open,
sda_padoen_o(0) => open);
------------------------------------------------------------------------------
-- Mezzanine SPI master
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ 238666a4
......@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i : in std_logic; -- WR link status bit
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
......
hdl/syn/spec_ref_design_wr/Manifest.py
View file @ 238666a4
......@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms"
syn_project = syn_top + "_wr.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
files = [
syn_top + "_wr.ucf",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/spec_ref_design"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
],
}
fetchto="../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_64b_32b" ]
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
ctrls = ["bank3_64b_32b" ]
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @ 238666a4
......@@ -2,292 +2,6 @@
# IO Constraints
#===============================================================================
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_gpio_b[1]" LOC = U16;
NET "gn_gpio_b[0]" LOC = AB19;
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_?_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_?_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DDR Memory
#----------------------------------------
# DDR (bank 3)
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
NET "ddr_udqs_p_b" LOC = V2;
NET "ddr_udqs_n_b" LOC = V1;
NET "ddr_udm_o" LOC = P3;
NET "ddr_reset_n_o" LOC = E3;
NET "ddr_ras_n_o" LOC = M5;
NET "ddr_odt_o" LOC = L6;
NET "ddr_ldqs_p_b" LOC = N3;
NET "ddr_ldqs_n_b" LOC = N1;
NET "ddr_ldm_o" LOC = N4;
NET "ddr_cke_o" LOC = F2;
NET "ddr_ck_p_o" LOC = K4;
NET "ddr_ck_n_o" LOC = K3;
NET "ddr_cas_n_o" LOC = M4;
NET "ddr_dq_b[15]" LOC = Y1;
NET "ddr_dq_b[14]" LOC = Y2;
NET "ddr_dq_b[13]" LOC = W1;
NET "ddr_dq_b[12]" LOC = W3;
NET "ddr_dq_b[11]" LOC = U1;
NET "ddr_dq_b[10]" LOC = U3;
NET "ddr_dq_b[9]" LOC = T1;
NET "ddr_dq_b[8]" LOC = T2;
NET "ddr_dq_b[7]" LOC = M1;
NET "ddr_dq_b[6]" LOC = M2;
NET "ddr_dq_b[5]" LOC = L1;
NET "ddr_dq_b[4]" LOC = L3;
NET "ddr_dq_b[3]" LOC = P1;
NET "ddr_dq_b[2]" LOC = P2;
NET "ddr_dq_b[1]" LOC = R1;
NET "ddr_dq_b[0]" LOC = R3;
NET "ddr_ba_o[2]" LOC = H1;
NET "ddr_ba_o[1]" LOC = J1;
NET "ddr_ba_o[0]" LOC = J3;
NET "ddr_a_o[13]" LOC = J6;
NET "ddr_a_o[12]" LOC = F1;
NET "ddr_a_o[11]" LOC = E1;
NET "ddr_a_o[10]" LOC = J4;
NET "ddr_a_o[9]" LOC = G1;
NET "ddr_a_o[8]" LOC = G3;
NET "ddr_a_o[7]" LOC = K6;
NET "ddr_a_o[6]" LOC = L4;
NET "ddr_a_o[5]" LOC = M3;
NET "ddr_a_o[4]" LOC = H3;
NET "ddr_a_o[3]" LOC = M6;
NET "ddr_a_o[2]" LOC = K5;
NET "ddr_a_o[1]" LOC = K1;
NET "ddr_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b" IN_TERM = NONE;
NET "ddr_ldqs_n_b" IN_TERM = NONE;
NET "ddr_udqs_p_b" IN_TERM = NONE;
NET "ddr_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_rxn_i" LOC = C15;
NET "sfp_rxp_i" LOC = D15;
NET "sfp_txn_o" LOC = A16;
NET "sfp_txp_o" LOC = B16;
NET "sfp_los_i" LOC = D18;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll20dac_sync_n_o" LOC = B3;
NET "plldac_din_o" LOC = C4;
NET "plldac_sclk_o" LOC = A4;
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AA3;
NET "spi_sclk_o" LOC = Y20;
NET "spi_mosi_o" LOC = AB20;
NET "spi_miso_i" LOC = AA20;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = B2;
NET "uart_rxd_i" LOC = A2;
NET "uart_txd_o" IOSTANDARD = "LVCMOS25";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_sfp_red_o" LOC = D5;
NET "led_sfp_green_o" LOC = E5;
NET "led_sfp_red_o" IOSTANDARD = "LVCMOS25";
NET "led_sfp_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# PCB Buttons and LEDs
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_scl_b" LOC = F7;
NET "fmc_sda_b" LOC = F8;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
#----------------------------------------
......@@ -381,136 +95,51 @@ NET "adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
# PCB LEDs
#----------------------------------------
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#===============================================================================
# Timing Constraints
# Timing constraints and exceptions
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_ref;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_ref;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "adc_dco_p_i" TNM_NET = adc_dco;
NET "adc_dco_n_i" TNM_NET = adc_dco;
TIMESPEC TS_adc_dco = PERIOD "adc_dco" 2.5 ns HIGH 50%;
NET "gn_p2l_clk_p_i" TNM_NET = "p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X30Y2;
#----------------------------------------
# Xilinx MCB tweaks
# IOB exceptions
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#----------------------------------------
# Asynchronous resets
# Clocks
#----------------------------------------
# GN4124
NET "gn_rst_n_i" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
NET "adc_dco_p_i" TNM_NET = adc_dco;
NET "adc_dco_n_i" TNM_NET = adc_dco;
TIMESPEC TS_adc_dco = PERIOD "adc_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMEGRP "adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "adc_sync_ffs" TIG;
TIMEGRP "adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = "sync_reg";
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "adc_sync_ffs" TIG;
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMEGRP "adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMEGRP "adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "adc_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "adc_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X30Y2;
TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 30ns DATAPATHONLY;
hdl/top/spec_ref_design/Manifest.py
View file @ 238666a4
......@@ -4,8 +4,17 @@ files = [
"dma_eic.vhd",
]
fetchto = "../../ip_cores"
modules = {
"local" : [
"../../../",
],
"git" : [
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/spec.git",
],
}
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ 238666a4
......@@ -35,16 +35,11 @@ use UNISIM.vcomponents.all;
library work;
use work.gn4124_core_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.synthesis_descriptor.all;
use work.spec_carrier_csr_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
entity spec_ref_fmc_adc_100Ms is
generic(
......@@ -67,14 +62,14 @@ entity spec_ref_fmc_adc_100Ms is
clk_125m_gtp_p_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n_o : out std_logic; -- 25MHz VCXO
pll20dac_sync_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
pll25dac_cs_n_o : out std_logic; -- 25MHz VCXO
pll20dac_cs_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier front panel LEDs
led_sfp_red_o : out std_logic;
led_sfp_green_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
......@@ -83,7 +78,7 @@ entity spec_ref_fmc_adc_100Ms is
pcbrev_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_onewire_b : inout std_logic;
onewire_b : inout std_logic;
-- SFP
sfp_txp_o : out std_logic;
......@@ -111,8 +106,8 @@ entity spec_ref_fmc_adc_100Ms is
------------------------------------------
-- GN4124 interface
--
-- gn_gpio_b[0] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[1] -> U16 -> GN4124 GPIO8
-- gn_gpio_b[1] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[0] -> U16 -> GN4124 GPIO8
------------------------------------------
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
......@@ -200,14 +195,15 @@ entity spec_ref_fmc_adc_100Ms is
------------------------------------------
-- FMC slot management
------------------------------------------
fmc_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
fmc_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
fmc_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
fmc0_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
fmc0_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
fmc0_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
);
end spec_ref_fmc_adc_100Ms;
architecture rtl of spec_ref_fmc_adc_100Ms is
architecture arch of spec_ref_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
......@@ -217,120 +213,28 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 6;
constant c_NUM_WB_SLAVES : integer := 2;
-- Wishbone master(s)
constant c_WB_MASTER_GENNUM : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_DMA : integer := 0; -- DMA controller in the Gennum core
constant c_WB_SLAVE_SPEC_CSR : integer := 1; -- SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 2; -- Vectored interrupt controller
constant c_WB_SLAVE_DMA_EIC : integer := 3; -- DMA interrupt controller
constant c_WB_SLAVE_FMC_ADC : integer := 4; -- FMC ADC mezzanine
constant c_WB_SLAVE_WR_CORE : integer := 5; -- WR PTP core
-- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
-- Devices sdb description
constant c_WB_DMA_CTRL_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_WB_SPEC_CSR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603",
version => x"00000001",
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_WB_DMA_EIC_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"d5735ab4", -- echo "WB-DMA.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-DMA.EIC ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_FMC_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_WR_CORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) :=
(
c_WB_SLAVE_DMA => f_sdb_embed_device(c_WB_DMA_CTRL_SDB, x"00001000"),
c_WB_SLAVE_SPEC_CSR => f_sdb_embed_device(c_WB_SPEC_CSR_SDB, x"00001200"),
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00001300"),
c_WB_SLAVE_DMA_EIC => f_sdb_embed_device(c_WB_DMA_EIC_SDB, x"00001400"),
c_WB_SLAVE_FMC_ADC => f_sdb_embed_bridge(c_FMC_BRIDGE_SDB, x"00002000"),
c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_WR_CORE_BRIDGE_SDB, x"00040000"),
c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO));
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00003500",
1 => x"00001400");
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC_ADC : integer := 1; -- FMC ADC mezzanine
------------------------------------------------------------------------------
-- Other constants declaration
------------------------------------------------------------------------------
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FMC_ADC => x"0000_4000");
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
-- Conversion of g_simulation to string needed for DDR controller
function f_int2string (n : natural) return string is
begin
if n = 0 then
return "FALSE";
else
return "TRUE ";
end if;
end;
constant c_SIMULATION_STR : string := f_int2string(g_SIMULATION);
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FMC_ADC => x"0003_e000"); -- 0x2000 bytes
------------------------------------------------------------------------------
-- Signals declaration
......@@ -339,29 +243,9 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
-- Clocks and resets
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
signal rst_ddr_333m_n : std_logic := '0';
signal sw_rst_fmc : std_logic := '1';
signal sw_rst_fmc_sync : std_logic := '1';
signal fmc_rst_ref_n : std_logic := '0';
signal fmc_rst_sys_n : std_logic := '0';
signal ddr_rst : std_logic := '1';
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of clk_ddr_333m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
-- GN4124
signal gn4124_status : std_logic_vector(31 downto 0);
signal gn4124_access : std_logic;
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -375,336 +259,183 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
signal cnx_fmc_sync_master_out : t_wishbone_master_out;
signal cnx_fmc_sync_master_in : t_wishbone_master_in;
-- GN4124 core DMA port to DDR wishbone bus
signal gn_wb_ddr_in : t_wishbone_master_in;
signal gn_wb_ddr_out : t_wishbone_master_out;
-- FMC ADC core to DDR wishbone bus
signal fmc_wb_ddr_in : t_wishbone_master_data64_in;
signal fmc_wb_ddr_out : t_wishbone_master_data64_out;
-- Interrupts and status
signal dma_irq : std_logic_vector(1 downto 0);
signal irq_sources : std_logic_vector(3 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(3 downto 0);
signal ddr_wr_fifo_empty : std_logic;
signal dma_eic_irq : std_logic;
signal fmc_irq : std_logic;
signal fmc_acq_cfg_ok : std_logic;
-- Resync interrupts to sys domain
signal dma_irq_sync : std_logic_vector(1 downto 0);
signal ddr_wr_fifo_empty_sync : std_logic;
signal fmc_irq_sync : std_logic;
-- Front panel LED control
signal led_red : std_logic;
signal led_green : std_logic;
-- DDR
signal ddr_status : std_logic_vector(31 downto 0);
signal ddr_calib_done : std_logic;
-- SFP
signal sfp_scl_out : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_sda_in : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- White Rabbit
signal wrabbit_en : std_logic;
signal wrc_scl_out : std_logic;
signal wrc_scl_in : std_logic;
signal wrc_sda_out : std_logic;
signal wrc_sda_in : std_logic;
signal pps_led : std_logic;
signal wr_led_act : std_logic;
signal wr_led_link : std_logic;
signal irq_vector : std_logic_vector(0 downto 0);
signal gn4124_access : std_logic;
-- WR PTP core timing interface
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_time_valid_sync : std_logic;
signal wrabbit_en : std_logic;
signal pps_led : std_logic;
-- IO for CSR registers
signal csr_regin : t_carrier_csr_master_in;
signal csr_regout : t_carrier_csr_master_out;
begin
------------------------------------------------------------------------------
-- Reset logic
------------------------------------------------------------------------------
sys_clk_pll_locked <= '1';
begin -- architecture arch
-- reset for mezzanine
-- including soft reset, with re-sync from 62.5MHz domain
-- and registers to help with timing
cmp_fmc_sw_reset_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => sw_rst_fmc,
synced_o => sw_rst_fmc_sync);
fmc_rst_ref_n <= rst_ref_125m_n and not sw_rst_fmc_sync;
fmc_rst_sys_n <= rst_sys_62m5_n and not sw_rst_fmc;
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst <= not rst_ddr_333m_n or sw_rst_fmc;
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
-- Reduce the default FIFO sizes to make it easier for the 45T Spartan6.
cmp_gn4124_core : xwb_gn4124_core
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12,
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175)
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4301", -- "ADC1"
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
rst_n_a_i => gn_rst_n_i,
status_o => gn4124_status,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
l2p_clk_p_o => gn_l2p_clk_p_o,
l2p_clk_n_o => gn_l2p_clk_n_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
vc_rdy_i => gn_vc_rdy_i,
dma_irq_o => dma_irq,
irq_p_i => irq_to_gn4124,
irq_p_o => gn_gpio_b(1),
wb_master_clk_i => clk_sys_62m5,
wb_master_rst_n_i => rst_sys_62m5_n,
wb_master_i => cnx_master_in(c_WB_MASTER_GENNUM),
wb_master_o => cnx_master_out(c_WB_MASTER_GENNUM),
wb_dma_cfg_clk_i => clk_sys_62m5,
wb_dma_cfg_rst_n_i => rst_sys_62m5_n,
wb_dma_cfg_i => cnx_slave_in(c_WB_SLAVE_DMA),
wb_dma_cfg_o => cnx_slave_out(c_WB_SLAVE_DMA),
wb_dma_dat_clk_i => clk_sys_62m5,
wb_dma_dat_rst_n_i => rst_sys_62m5_n,
wb_dma_dat_i => gn_wb_ddr_in,
wb_dma_dat_o => gn_wb_ddr_out);
-- Assign unused outputs
gn_gpio_b(0) <= '0';
------------------------------------------------------------------------------
-- Primary wishbone crossbar
------------------------------------------------------------------------------
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
cmp_sdb_crossbar : xwb_sdb_crossbar
inst_spec_base : entity work.spec_base_wr
generic map (
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_WRAPAROUND => TRUE,
g_LAYOUT => c_INTERCONNECT_LAYOUT,
g_SDB_ADDR => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
-------------------------------------------------------------------------------
-- White Rabbit Core (SPEC board package)
-------------------------------------------------------------------------------
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for Carrier OneWire
carrier_onewire_b <= '0' when onewire_oe = '1' else 'Z';
onewire_data <= carrier_onewire_b;
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_SIMULATION => g_SIMULATION,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_FABRIC_IFACE => PLAIN)
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 64,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 1,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 0,
g_FABRIC_IFACE => plain,
g_SIMULATION => f_int2bool(g_SIMULATION))
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
areset_n_i => button1_n_i,
areset_edge_n_i => gn_rst_n_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_sync_n_o,
pll20dac_cs_n_o => pll20dac_sync_n_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
flash_sclk_o => spi_sclk_o,
flash_ncs_o => spi_ncs_o,
flash_mosi_o => spi_mosi_o,
flash_miso_i => spi_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WR_CORE),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WR_CORE),
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_wb_cyc_i => fmc_wb_ddr_out.cyc,
ddr_dma_wb_stb_i => fmc_wb_ddr_out.stb,
ddr_dma_wb_adr_i => fmc_wb_ddr_out.adr,
ddr_dma_wb_sel_i => fmc_wb_ddr_out.sel,
ddr_dma_wb_we_i => fmc_wb_ddr_out.we,
ddr_dma_wb_dat_i => fmc_wb_ddr_out.dat,
ddr_dma_wb_ack_o => fmc_wb_ddr_in.ack,
ddr_dma_wb_stall_o => fmc_wb_ddr_in.stall,
ddr_dma_wb_dat_o => fmc_wb_ddr_in.dat,
ddr_wr_fifo_empty_o => ddr_wr_fifo_empty,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
clk_125m_ref_o => clk_ref_125m,
rst_125m_ref_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => open,
pps_led_o => pps_led,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
link_ok_o => wrabbit_en);
link_ok_o => wrabbit_en,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.spec_carrier_csr
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR),
wb_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR),
carrier_csr_i => csr_regin,
carrier_csr_o => csr_regout);
csr_regin.carrier_pcb_rev <= pcbrev_i;
csr_regin.carrier_reserved <= (others => '0');
csr_regin.carrier_type <= c_CARRIER_TYPE;
csr_regin.stat_fmc_pres <= fmc_prsnt_m2c_n_i;
csr_regin.stat_p2l_pll_lck <= gn4124_status(0);
csr_regin.stat_sys_pll_lck <= sys_clk_pll_locked;
csr_regin.stat_ddr3_cal_done <= ddr_calib_done;
led_red <= csr_regout.ctrl_led_red;
led_green <= csr_regout.ctrl_led_green;
sw_rst_fmc <= csr_regout.rst_fmc0;
fmc_wb_ddr_in.err <= '0';
fmc_wb_ddr_in.rty <= '0';
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq,
synced_o => fmc_irq_sync);
cmp_vic : xwb_vic
cmp_crossbar : xwb_crossbar
generic map (
g_INTERFACE_MODE => PIPELINED,
g_ADDRESS_GRANULARITY => BYTE,
g_NUM_INTERRUPTS => 2,
g_INIT_VECTORS => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_irq_sync,
irqs_i(1) => dma_eic_irq,
irq_master_o => irq_to_gn4124);
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
gen_dma_irq : for I in 0 to 1 generate
cmp_dma_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => dma_irq(I),
synced_o => dma_irq_sync(I));
end generate gen_dma_irq;
cmp_dma_eic : entity work.dma_eic
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map (
rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).ack,
wb_stall_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).stall,
wb_int_o => dma_eic_irq,
irq_dma_done_i => dma_irq_sync(0),
irq_dma_error_i => dma_irq_sync(1)
);
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_DMA_EIC).err <= '0';
cnx_slave_out(c_WB_SLAVE_DMA_EIC).rty <= '0';
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking)
......@@ -718,21 +449,28 @@ begin
cmp_xwb_clock_bridge : xwb_clock_bridge
port map (
slave_clk_i => clk_sys_62m5,
slave_rst_n_i => fmc_rst_sys_n,
slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
master_clk_i => clk_ref_125m,
master_rst_n_i => fmc_rst_ref_n,
master_rst_n_i => rst_ref_125m_n,
master_i => cnx_fmc_sync_master_in,
master_o => cnx_fmc_sync_master_out
);
cmp_fmc_ddr_wr_fifo_sync : gc_sync_ffs
cmp_tm_time_valid_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => ddr_wr_fifo_empty,
synced_o => ddr_wr_fifo_empty_sync);
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
cmp_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq,
synced_o => irq_vector(0));
cmp_fmc_adc_mezzanine : fmc_adc_mezzanine
generic map (
......@@ -742,17 +480,17 @@ begin
g_WB_GRANULARITY => BYTE)
port map (
sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc_rst_ref_n,
sys_rst_n_i => rst_ref_125m_n,
wb_csr_slave_i => cnx_fmc_sync_master_out,
wb_csr_slave_o => cnx_fmc_sync_master_in,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_rst_n_i => fmc_rst_ref_n,
wb_ddr_rst_n_i => rst_ref_125m_n,
wb_ddr_master_i => fmc_wb_ddr_in,
wb_ddr_master_o => fmc_wb_ddr_out,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty_sync,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty,
trig_irq_o => open,
acq_end_irq_o => open,
eic_irq_o => fmc_irq,
......@@ -793,119 +531,13 @@ begin
mezz_one_wire_b => adc_one_wire_b,
sys_scl_b => fmc_scl_b,
sys_sda_b => fmc_sda_b,
wr_tm_link_up_i => tm_link_up,
wr_tm_time_valid_i => tm_time_valid,
wr_tm_time_valid_i => tm_time_valid_sync,
wr_tm_tai_i => tm_tai,
wr_tm_cycles_i => tm_cycles,
wr_enable_i => wrabbit_en
);
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl_bank3 : ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_SIMULATION_STR,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => ddr_rst,
status_o => ddr_status,
ddr3_dq_b => ddr_dq_b,
ddr3_a_o => ddr_a_o,
ddr3_ba_o => ddr_ba_o,
ddr3_ras_n_o => ddr_ras_n_o,
ddr3_cas_n_o => ddr_cas_n_o,
ddr3_we_n_o => ddr_we_n_o,
ddr3_odt_o => ddr_odt_o,
ddr3_rst_n_o => ddr_reset_n_o,
ddr3_cke_o => ddr_cke_o,
ddr3_dm_o => ddr_ldm_o,
ddr3_udm_o => ddr_udm_o,
ddr3_dqs_p_b => ddr_ldqs_p_b,
ddr3_dqs_n_b => ddr_ldqs_n_b,
ddr3_udqs_p_b => ddr_udqs_p_b,
ddr3_udqs_n_b => ddr_udqs_n_b,
ddr3_clk_p_o => ddr_ck_p_o,
ddr3_clk_n_o => ddr_ck_n_o,
ddr3_rzq_b => ddr_rzq_b,
wb0_rst_n_i => fmc_rst_ref_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => fmc_wb_ddr_out.sel,
wb0_cyc_i => fmc_wb_ddr_out.cyc,
wb0_stb_i => fmc_wb_ddr_out.stb,
wb0_we_i => fmc_wb_ddr_out.we,
wb0_addr_i => fmc_wb_ddr_out.adr,
wb0_data_i => fmc_wb_ddr_out.dat,
wb0_data_o => fmc_wb_ddr_in.dat,
wb0_ack_o => fmc_wb_ddr_in.ack,
wb0_stall_o => fmc_wb_ddr_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
wb1_we_i => gn_wb_ddr_out.we,
wb1_addr_i => gn_wb_ddr_out.adr,
wb1_data_i => gn_wb_ddr_out.dat,
wb1_data_o => gn_wb_ddr_in.dat,
wb1_ack_o => gn_wb_ddr_in.ack,
wb1_stall_o => gn_wb_ddr_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr_calib_done <= ddr_status(0);
-- unused Wishbone signals
gn_wb_ddr_in.err <= '0';
gn_wb_ddr_in.rty <= '0';
fmc_wb_ddr_in.err <= '0';
fmc_wb_ddr_in.rty <= '0';
------------------------------------------------------------------------------
-- Carrier LEDs
------------------------------------------------------------------------------
......@@ -924,8 +556,4 @@ begin
aux_leds_o(2) <= not tm_time_valid;
aux_leds_o(3) <= not pps_led;
-- SPEC front panel leds
led_sfp_red_o <= led_red or wr_led_act;
led_sfp_green_o <= led_green or wr_led_link;
end rtl;
end architecture arch;
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