diff --git a/.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xci b/.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xci
deleted file mode 100644
index f46c9e604eccc808cb65c0307edaff5aa7be9bb9..0000000000000000000000000000000000000000
--- a/.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xci
+++ /dev/null
@@ -1,44 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>xci</spirit:library>
- <spirit:name>unknown</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>clock_temp</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="signal.param" spirit:name="clock" spirit:version="1.0"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_ASYNC_RESET">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_BUSIF">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_CLKEN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_MMCM_LOCK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_RESET">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DOMAIN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clock_temp</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ_HZ">100000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortWidth">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z030</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg676</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_BusInterface</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
diff --git a/.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xml b/.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xml
deleted file mode 100644
index 0b1f84f279107f9219d2b4d7164871359349bb0c..0000000000000000000000000000000000000000
--- a/.Xil/Vivado-27812-lapte24154/coregen/clock_temp/clock_temp.xml
+++ /dev/null
@@ -1,91 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>customized_ip</spirit:library>
- <spirit:name>clock_temp</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:model>
- <spirit:ports>
- <spirit:port>
- <spirit:name>const</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">0</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:description>intf_clock_v1_0</spirit:description>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>PortWidth</spirit:name>
- <spirit:displayName>Portwidth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PortWidth" spirit:order="1100">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_CLKEN</spirit:name>
- <spirit:displayName>Associated Clken</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_CLKEN" spirit:order="1200">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:displayName>Associated Reset</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_RESET" spirit:order="1300">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
- <spirit:displayName>Associated Async Reset</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_ASYNC_RESET" spirit:order="1400">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:displayName>Associated MMCM Lock</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_MMCM_LOCK" spirit:order="1500">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:displayName>Associated Busif</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_BUSIF" spirit:order="1600">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:displayName>Clk Domain</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_DOMAIN" spirit:order="1700">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:displayName>Phase</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE" spirit:order="1800">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:displayName>Frequency</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ_HZ" spirit:order="1900">100000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clock_temp</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:coreExtensions>
- <xilinx:displayName>intf_clock_v1_0</xilinx:displayName>
- <xilinx:coreRevision>1</xilinx:coreRevision>
- <xilinx:tags>
- <xilinx:tag xilinx:name="nopcore"/>
- </xilinx:tags>
- </xilinx:coreExtensions>
- <xilinx:packagingInfo>
- <xilinx:xilinxVersion>2013.3.0</xilinx:xilinxVersion>
- </xilinx:packagingInfo>
- </spirit:vendorExtensions>
-</spirit:component>
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
index 82ecd47d8f2dfb3567505e0961043a14b53cd094..5808333c6137546b8eb38e9e3fbdb15653830107 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Jun 21 08:28:38 2017
+--Date : Wed Oct 11 12:10:21 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design.bd
--Design : system_design
@@ -4009,12 +4009,46 @@ architecture STRUCTURE of system_design is
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_design_rst_wrc_1p_kintex7_0_62M_0;
- component system_design_axi_wb_i2c_master_0_1 is
+ component system_design_wrc_1p_kintex7_0_0 is
port (
- i2c_scl_io : inout STD_LOGIC;
- i2c_sda_io : inout STD_LOGIC;
+ clk_20m_vcxo_i : in STD_LOGIC;
+ gtp_dedicated_clk_p_i : in STD_LOGIC;
+ gtp_dedicated_clk_n_i : in STD_LOGIC;
+ clk_dmtd_o : out STD_LOGIC;
+ clk_ref_o : out STD_LOGIC;
+ clk_rx_rbclk_o : out STD_LOGIC;
+ gtp0_activity_led_o : out STD_LOGIC;
+ gtp0_synced_led_o : out STD_LOGIC;
+ gtp0_link_led_o : out STD_LOGIC;
+ gtp0_wrmode_led_o : out STD_LOGIC;
+ dac_sclk_o : out STD_LOGIC;
+ dac_din_o : out STD_LOGIC;
+ dac_cs1_n_o : out STD_LOGIC;
+ dac_cs2_n_o : out STD_LOGIC;
+ fpga_scl_b : inout STD_LOGIC;
+ fpga_sda_b : inout STD_LOGIC;
+ button_rst_n_i : in STD_LOGIC;
+ thermo_id : inout STD_LOGIC;
+ gtp0_txp_o : out STD_LOGIC;
+ gtp0_txn_o : out STD_LOGIC;
+ gtp0_rxp_i : in STD_LOGIC;
+ gtp0_rxn_i : in STD_LOGIC;
+ gtp0_mod_def0_b : in STD_LOGIC;
+ gtp0_mod_def1_b : inout STD_LOGIC;
+ gtp0_mod_def2_b : inout STD_LOGIC;
+ gtp0_rate_select_b : inout STD_LOGIC;
+ gtp0_tx_fault_i : in STD_LOGIC;
+ gtp0_tx_disable_o : out STD_LOGIC;
+ gtp0_los_i : in STD_LOGIC;
+ uart_rxd_i : in STD_LOGIC;
+ uart_txd_o : out STD_LOGIC;
+ ext_clk_i : in STD_LOGIC;
+ pps_i : in STD_LOGIC;
+ pps_ctrl_o : out STD_LOGIC;
+ term_en_o : out STD_LOGIC;
+ pps_o : out STD_LOGIC;
axi_int_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aclk_o : out STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -4036,8 +4070,8 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_0_1;
- component system_design_axi_wb_i2c_master_2_0 is
+ end component system_design_wrc_1p_kintex7_0_0;
+ component system_design_axi_wb_i2c_master_0_1 is
port (
i2c_scl_io : inout STD_LOGIC;
i2c_sda_io : inout STD_LOGIC;
@@ -4064,47 +4098,13 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_2_0;
- component system_design_wrc_1p_kintex7_0_0 is
+ end component system_design_axi_wb_i2c_master_0_1;
+ component system_design_axi_wb_i2c_master_2_0 is
port (
- clk_20m_vcxo_i : in STD_LOGIC;
- gtp_dedicated_clk_p_i : in STD_LOGIC;
- gtp_dedicated_clk_n_i : in STD_LOGIC;
- clk_dmtd_o : out STD_LOGIC;
- clk_ref_o : out STD_LOGIC;
- clk_rx_rbclk_o : out STD_LOGIC;
- gtp0_activity_led_o : out STD_LOGIC;
- gtp0_synced_led_o : out STD_LOGIC;
- gtp0_link_led_o : out STD_LOGIC;
- gtp0_wrmode_led_o : out STD_LOGIC;
- dac_sclk_o : out STD_LOGIC;
- dac_din_o : out STD_LOGIC;
- dac_cs1_n_o : out STD_LOGIC;
- dac_cs2_n_o : out STD_LOGIC;
- fpga_scl_b : inout STD_LOGIC;
- fpga_sda_b : inout STD_LOGIC;
- button_rst_n_i : in STD_LOGIC;
- thermo_id : inout STD_LOGIC;
- gtp0_txp_o : out STD_LOGIC;
- gtp0_txn_o : out STD_LOGIC;
- gtp0_rxp_i : in STD_LOGIC;
- gtp0_rxn_i : in STD_LOGIC;
- gtp0_mod_def0_b : in STD_LOGIC;
- gtp0_mod_def1_b : inout STD_LOGIC;
- gtp0_mod_def2_b : inout STD_LOGIC;
- gtp0_rate_select_b : inout STD_LOGIC;
- gtp0_tx_fault_i : in STD_LOGIC;
- gtp0_tx_disable_o : out STD_LOGIC;
- gtp0_los_i : in STD_LOGIC;
- uart_rxd_i : in STD_LOGIC;
- uart_txd_o : out STD_LOGIC;
- ext_clk_i : in STD_LOGIC;
- pps_i : in STD_LOGIC;
- pps_ctrl_o : out STD_LOGIC;
- term_en_o : out STD_LOGIC;
- pps_o : out STD_LOGIC;
+ i2c_scl_io : inout STD_LOGIC;
+ i2c_sda_io : inout STD_LOGIC;
axi_int_o : out STD_LOGIC;
- s00_axi_aclk_o : out STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -4126,7 +4126,7 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_wrc_1p_kintex7_0_0;
+ end component system_design_axi_wb_i2c_master_2_0;
component system_design_fasec_hwtest_0_0 is
port (
ps_clk_i : in STD_LOGIC;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd
index 4657c9fc3a8d73bc4ce1b6f609db701a92eb1466..14acdc5e54dcb294788c6e66ea473c07d125cc94 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.1
--- IP Revision: 5
+-- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.2
+-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
deleted file mode 100644
index a4bceb7fe25adae9e77849d7793a202974eb2728..0000000000000000000000000000000000000000
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
+++ /dev/null
@@ -1,4068 +0,0 @@
-// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Tue Jun 20 20:06:19 2017
-// Host : lapte24154 running 64-bit openSUSE Leap 42.2
-// Command : write_verilog -force -mode funcsim
-// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
-// Design : system_design_axi_wb_i2c_master_0_1
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z030ffg676-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "system_design_axi_wb_i2c_master_0_1,axi_wb_i2c_master,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_wb_i2c_master,Vivado 2016.2" *)
-(* NotValidForBitStream *)
-module system_design_axi_wb_i2c_master_0_1
- (i2c_scl_io,
- i2c_sda_io,
- axi_int_o,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_awaddr,
- s00_axi_awprot,
- s00_axi_awvalid,
- s00_axi_awready,
- s00_axi_wdata,
- s00_axi_wstrb,
- s00_axi_wvalid,
- s00_axi_wready,
- s00_axi_bresp,
- s00_axi_bvalid,
- s00_axi_bready,
- s00_axi_araddr,
- s00_axi_arprot,
- s00_axi_arvalid,
- s00_axi_arready,
- s00_axi_rdata,
- s00_axi_rresp,
- s00_axi_rvalid,
- s00_axi_rready);
- inout i2c_scl_io;
- inout i2c_sda_io;
- output axi_int_o;
- (* x_interface_info = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *) input s00_axi_aclk;
- (* x_interface_info = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *) input s00_axi_aresetn;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *) input [31:0]s00_axi_awaddr;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *) input [2:0]s00_axi_awprot;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *) input s00_axi_awvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *) output s00_axi_awready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *) input [31:0]s00_axi_wdata;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *) input [3:0]s00_axi_wstrb;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *) input s00_axi_wvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *) output s00_axi_wready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *) output [1:0]s00_axi_bresp;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *) output s00_axi_bvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *) input s00_axi_bready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *) input [31:0]s00_axi_araddr;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *) input [2:0]s00_axi_arprot;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *) input s00_axi_arvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *) output s00_axi_arready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *) output [31:0]s00_axi_rdata;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *) output [1:0]s00_axi_rresp;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *) output s00_axi_rvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *) input s00_axi_rready;
-
- wire axi_int_o;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire s00_axi_aclk;
- wire [31:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire [2:0]s00_axi_arprot;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [31:0]s00_axi_awaddr;
- wire [2:0]s00_axi_awprot;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [1:0]s00_axi_bresp;
- wire s00_axi_bvalid;
- wire [31:0]s00_axi_rdata;
- wire s00_axi_rready;
- wire [1:0]s00_axi_rresp;
- wire s00_axi_rvalid;
- wire [31:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire [3:0]s00_axi_wstrb;
- wire s00_axi_wvalid;
-
- (* C_S00_AXI_ADDR_WIDTH = "32" *)
- (* C_S00_AXI_DATA_WIDTH = "32" *)
- system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master U0
- (.axi_int_o(axi_int_o),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_araddr(s00_axi_araddr),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arprot(s00_axi_arprot),
- .s00_axi_arready(s00_axi_arready),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awaddr(s00_axi_awaddr),
- .s00_axi_awprot(s00_axi_awprot),
- .s00_axi_awready(s00_axi_awready),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_bready(s00_axi_bready),
- .s00_axi_bresp(s00_axi_bresp),
- .s00_axi_bvalid(s00_axi_bvalid),
- .s00_axi_rdata(s00_axi_rdata),
- .s00_axi_rready(s00_axi_rready),
- .s00_axi_rresp(s00_axi_rresp),
- .s00_axi_rvalid(s00_axi_rvalid),
- .s00_axi_wdata(s00_axi_wdata),
- .s00_axi_wready(s00_axi_wready),
- .s00_axi_wstrb(s00_axi_wstrb),
- .s00_axi_wvalid(s00_axi_wvalid));
-endmodule
-
-(* C_S00_AXI_ADDR_WIDTH = "32" *) (* C_S00_AXI_DATA_WIDTH = "32" *) (* ORIG_REF_NAME = "axi_wb_i2c_master" *)
-module system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
- (i2c_scl_io,
- i2c_sda_io,
- axi_int_o,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_awaddr,
- s00_axi_awprot,
- s00_axi_awvalid,
- s00_axi_awready,
- s00_axi_wdata,
- s00_axi_wstrb,
- s00_axi_wvalid,
- s00_axi_wready,
- s00_axi_bresp,
- s00_axi_bvalid,
- s00_axi_bready,
- s00_axi_araddr,
- s00_axi_arprot,
- s00_axi_arvalid,
- s00_axi_arready,
- s00_axi_rdata,
- s00_axi_rresp,
- s00_axi_rvalid,
- s00_axi_rready);
- inout i2c_scl_io;
- inout i2c_sda_io;
- output axi_int_o;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [31:0]s00_axi_awaddr;
- input [2:0]s00_axi_awprot;
- input s00_axi_awvalid;
- output s00_axi_awready;
- input [31:0]s00_axi_wdata;
- input [3:0]s00_axi_wstrb;
- input s00_axi_wvalid;
- output s00_axi_wready;
- output [1:0]s00_axi_bresp;
- output s00_axi_bvalid;
- input s00_axi_bready;
- input [31:0]s00_axi_araddr;
- input [2:0]s00_axi_arprot;
- input s00_axi_arvalid;
- output s00_axi_arready;
- output [31:0]s00_axi_rdata;
- output [1:0]s00_axi_rresp;
- output s00_axi_rvalid;
- input s00_axi_rready;
-
- wire \<const0> ;
- wire axi_int_o;
- wire cmp_axis_wbm_bridge_n_11;
- wire cmp_axis_wbm_bridge_n_12;
- wire cmp_axis_wbm_bridge_n_13;
- wire cmp_axis_wbm_bridge_n_14;
- wire cmp_axis_wbm_bridge_n_15;
- wire cmp_axis_wbm_bridge_n_16;
- wire cmp_axis_wbm_bridge_n_17;
- wire cmp_axis_wbm_bridge_n_18;
- wire cmp_axis_wbm_bridge_n_19;
- wire cmp_axis_wbm_bridge_n_21;
- wire cmp_axis_wbm_bridge_n_7;
- wire cmp_i2c_master_top_n_4;
- wire cmp_i2c_master_top_n_5;
- wire ena;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire s00_axi_aclk;
- wire [31:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [31:0]s00_axi_awaddr;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [1:1]\^s00_axi_bresp ;
- wire s00_axi_bvalid;
- wire [7:0]\^s00_axi_rdata ;
- wire s00_axi_rready;
- wire s00_axi_rvalid;
- wire [31:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire s00_axi_wvalid;
- wire wb_ack_i;
- wire [2:0]wb_adr_o;
- wire wb_cyc_o;
- wire [7:0]wb_dat_o;
- wire wb_rst_o;
- wire wb_we_o;
-
- assign s00_axi_bresp[1] = \^s00_axi_bresp [1];
- assign s00_axi_bresp[0] = \<const0> ;
- assign s00_axi_rdata[31] = \<const0> ;
- assign s00_axi_rdata[30] = \<const0> ;
- assign s00_axi_rdata[29] = \<const0> ;
- assign s00_axi_rdata[28] = \<const0> ;
- assign s00_axi_rdata[27] = \<const0> ;
- assign s00_axi_rdata[26] = \<const0> ;
- assign s00_axi_rdata[25] = \<const0> ;
- assign s00_axi_rdata[24] = \<const0> ;
- assign s00_axi_rdata[23] = \<const0> ;
- assign s00_axi_rdata[22] = \<const0> ;
- assign s00_axi_rdata[21] = \<const0> ;
- assign s00_axi_rdata[20] = \<const0> ;
- assign s00_axi_rdata[19] = \<const0> ;
- assign s00_axi_rdata[18] = \<const0> ;
- assign s00_axi_rdata[17] = \<const0> ;
- assign s00_axi_rdata[16] = \<const0> ;
- assign s00_axi_rdata[15] = \<const0> ;
- assign s00_axi_rdata[14] = \<const0> ;
- assign s00_axi_rdata[13] = \<const0> ;
- assign s00_axi_rdata[12] = \<const0> ;
- assign s00_axi_rdata[11] = \<const0> ;
- assign s00_axi_rdata[10] = \<const0> ;
- assign s00_axi_rdata[9] = \<const0> ;
- assign s00_axi_rdata[8] = \<const0> ;
- assign s00_axi_rdata[7:0] = \^s00_axi_rdata [7:0];
- assign s00_axi_rresp[1] = \<const0> ;
- assign s00_axi_rresp[0] = \<const0> ;
- GND GND
- (.G(\<const0> ));
- system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge cmp_axis_wbm_bridge
- (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
- .E(cmp_axis_wbm_bridge_n_11),
- .Q(ena),
- .\cr_reg[2] (cmp_axis_wbm_bridge_n_7),
- .\cr_reg[4] (cmp_axis_wbm_bridge_n_16),
- .\ctr_reg[0] (cmp_axis_wbm_bridge_n_19),
- .iack_o_reg(cmp_axis_wbm_bridge_n_21),
- .iack_o_reg_0(cmp_i2c_master_top_n_4),
- .iack_o_reg_1(cmp_i2c_master_top_n_5),
- .\prer_reg[8] ({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_araddr(s00_axi_araddr[4:2]),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arready(s00_axi_arready),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awaddr(s00_axi_awaddr[4:2]),
- .s00_axi_awready(s00_axi_awready),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_bready(s00_axi_bready),
- .s00_axi_bresp(\^s00_axi_bresp ),
- .s00_axi_bvalid(s00_axi_bvalid),
- .s00_axi_rdata(\^s00_axi_rdata ),
- .s00_axi_rready(s00_axi_rready),
- .s00_axi_rvalid(s00_axi_rvalid),
- .s00_axi_wdata(s00_axi_wdata[7:4]),
- .s00_axi_wready(s00_axi_wready),
- .s00_axi_wvalid(s00_axi_wvalid),
- .wb_ack_i(wb_ack_i),
- .wb_adr_o(wb_adr_o),
- .wb_cyc_o(wb_cyc_o),
- .\wb_dat_o_reg[7] (wb_dat_o),
- .wb_rst_o(wb_rst_o),
- .wb_we_o(wb_we_o));
- system_design_axi_wb_i2c_master_0_1_i2c_master_top cmp_i2c_master_top
- (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
- .E({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
- .Q(ena),
- .axi_int_o(axi_int_o),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .iack_o_reg_0(cmp_axis_wbm_bridge_n_16),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_wdata(s00_axi_wdata[7:0]),
- .\s_addr_reg[4] (cmp_axis_wbm_bridge_n_7),
- .\s_rdata_reg[0] (cmp_i2c_master_top_n_5),
- .\s_rdata_reg[7] (wb_dat_o),
- .s_stb_r_reg(cmp_i2c_master_top_n_4),
- .s_stb_r_reg_0(cmp_axis_wbm_bridge_n_21),
- .s_we_r_reg(cmp_axis_wbm_bridge_n_19),
- .s_we_r_reg_0(cmp_axis_wbm_bridge_n_11),
- .wb_ack_i(wb_ack_i),
- .wb_adr_o(wb_adr_o),
- .wb_cyc_o(wb_cyc_o),
- .wb_rst_o(wb_rst_o),
- .wb_we_o(wb_we_o));
-endmodule
-
-(* ORIG_REF_NAME = "axis_wbm_bridge" *)
-module system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge
- (s00_axi_awready,
- s00_axi_wready,
- s00_axi_arready,
- wb_we_o,
- wb_cyc_o,
- s00_axi_bresp,
- s00_axi_bvalid,
- \cr_reg[2] ,
- wb_adr_o,
- E,
- D,
- \cr_reg[4] ,
- \prer_reg[8] ,
- \ctr_reg[0] ,
- s00_axi_rvalid,
- iack_o_reg,
- s00_axi_rdata,
- wb_rst_o,
- s00_axi_aclk,
- iack_o_reg_0,
- Q,
- s00_axi_aresetn,
- wb_ack_i,
- s00_axi_awvalid,
- s00_axi_arvalid,
- s00_axi_bready,
- s00_axi_rready,
- s00_axi_wvalid,
- s00_axi_wdata,
- s00_axi_araddr,
- s00_axi_awaddr,
- iack_o_reg_1,
- \wb_dat_o_reg[7] );
- output s00_axi_awready;
- output s00_axi_wready;
- output s00_axi_arready;
- output wb_we_o;
- output wb_cyc_o;
- output [0:0]s00_axi_bresp;
- output s00_axi_bvalid;
- output \cr_reg[2] ;
- output [2:0]wb_adr_o;
- output [0:0]E;
- output [3:0]D;
- output \cr_reg[4] ;
- output [1:0]\prer_reg[8] ;
- output [0:0]\ctr_reg[0] ;
- output s00_axi_rvalid;
- output iack_o_reg;
- output [7:0]s00_axi_rdata;
- input wb_rst_o;
- input s00_axi_aclk;
- input iack_o_reg_0;
- input [0:0]Q;
- input s00_axi_aresetn;
- input wb_ack_i;
- input s00_axi_awvalid;
- input s00_axi_arvalid;
- input s00_axi_bready;
- input s00_axi_rready;
- input s00_axi_wvalid;
- input [3:0]s00_axi_wdata;
- input [2:0]s00_axi_araddr;
- input [2:0]s00_axi_awaddr;
- input [0:0]iack_o_reg_1;
- input [7:0]\wb_dat_o_reg[7] ;
-
- wire [3:0]D;
- wire [0:0]E;
- wire [0:0]Q;
- wire \cr[2]_i_3_n_0 ;
- wire \cr_reg[2] ;
- wire \cr_reg[4] ;
- wire [0:0]\ctr_reg[0] ;
- wire iack_o_reg;
- wire iack_o_reg_0;
- wire [0:0]iack_o_reg_1;
- wire [1:0]\prer_reg[8] ;
- wire s00_axi_aclk;
- wire [2:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [2:0]s00_axi_awaddr;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [0:0]s00_axi_bresp;
- wire s00_axi_bvalid;
- wire [7:0]s00_axi_rdata;
- wire s00_axi_rready;
- wire s00_axi_rvalid;
- wire [3:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire s00_axi_wvalid;
- wire \s_addr[2]_i_1_n_0 ;
- wire \s_addr[3]_i_1_n_0 ;
- wire \s_addr[4]_i_1_n_0 ;
- wire s_arready_i_1_n_0;
- wire s_awready_i_1_n_0;
- wire \s_bresp[1]_i_1_n_0 ;
- wire s_bvalid;
- wire s_bvalid_i_1_n_0;
- wire s_rvalid;
- wire s_rvalid_i_1_n_0;
- wire s_we_r_i_1_n_0;
- wire s_wready_i_1_n_0;
- wire wb_ack_i;
- wire [2:0]wb_adr_o;
- wire wb_cyc_o;
- wire [7:0]\wb_dat_o_reg[7] ;
- wire wb_rst_o;
- wire wb_we_o;
-
- LUT6 #(
- .INIT(64'hFFFF0008FFFFFFFF))
- \cr[2]_i_2
- (.I0(wb_adr_o[2]),
- .I1(Q),
- .I2(wb_adr_o[1]),
- .I3(wb_adr_o[0]),
- .I4(\cr[2]_i_3_n_0 ),
- .I5(s00_axi_aresetn),
- .O(\cr_reg[2] ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT2 #(
- .INIT(4'h7))
- \cr[2]_i_3
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .O(\cr[2]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[4]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[0]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[0]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[5]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[1]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[1]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[6]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[2]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[2]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[7]_i_2
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[3]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[3]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF7FFF))
- \cr[7]_i_3
- (.I0(wb_ack_i),
- .I1(wb_we_o),
- .I2(wb_adr_o[2]),
- .I3(Q),
- .I4(wb_adr_o[1]),
- .I5(wb_adr_o[0]),
- .O(\cr_reg[4] ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h0080FFFF))
- \ctr[7]_i_1
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .I2(wb_adr_o[1]),
- .I3(wb_adr_o[0]),
- .I4(s00_axi_aresetn),
- .O(\ctr_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT2 #(
- .INIT(4'h2))
- iack_o_i_1
- (.I0(wb_cyc_o),
- .I1(wb_ack_i),
- .O(iack_o_reg));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h75555555))
- \prer[15]_i_1
- (.I0(s00_axi_aresetn),
- .I1(wb_adr_o[1]),
- .I2(wb_ack_i),
- .I3(wb_we_o),
- .I4(wb_adr_o[0]),
- .O(\prer_reg[8] [1]));
- LUT6 #(
- .INIT(64'h5555555557555555))
- \prer[7]_i_1
- (.I0(s00_axi_aresetn),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[2]),
- .I3(wb_ack_i),
- .I4(wb_we_o),
- .I5(wb_adr_o[0]),
- .O(\prer_reg[8] [0]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT2 #(
- .INIT(4'h8))
- s00_axi_bvalid_INST_0
- (.I0(s_bvalid),
- .I1(wb_we_o),
- .O(s00_axi_bvalid));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT2 #(
- .INIT(4'h2))
- s00_axi_rvalid_INST_0
- (.I0(s_rvalid),
- .I1(wb_we_o),
- .O(s00_axi_rvalid));
- LUT5 #(
- .INIT(32'hAACFAAC0))
- \s_addr[2]_i_1
- (.I0(s00_axi_araddr[0]),
- .I1(s00_axi_awaddr[0]),
- .I2(s00_axi_awvalid),
- .I3(s00_axi_arvalid),
- .I4(wb_adr_o[0]),
- .O(\s_addr[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hAACFAAC0))
- \s_addr[3]_i_1
- (.I0(s00_axi_araddr[1]),
- .I1(s00_axi_awaddr[1]),
- .I2(s00_axi_awvalid),
- .I3(s00_axi_arvalid),
- .I4(wb_adr_o[1]),
- .O(\s_addr[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hAACFAAC0))
- \s_addr[4]_i_1
- (.I0(s00_axi_araddr[2]),
- .I1(s00_axi_awaddr[2]),
- .I2(s00_axi_awvalid),
- .I3(s00_axi_arvalid),
- .I4(wb_adr_o[2]),
- .O(\s_addr[4]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_addr_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_addr[2]_i_1_n_0 ),
- .Q(wb_adr_o[0]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_addr_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_addr[3]_i_1_n_0 ),
- .Q(wb_adr_o[1]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_addr_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_addr[4]_i_1_n_0 ),
- .Q(wb_adr_o[2]),
- .R(wb_rst_o));
- LUT2 #(
- .INIT(4'h2))
- s_arready_i_1
- (.I0(s00_axi_arvalid),
- .I1(s00_axi_arready),
- .O(s_arready_i_1_n_0));
- FDRE s_arready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_arready_i_1_n_0),
- .Q(s00_axi_arready),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'h08))
- s_awready_i_1
- (.I0(s00_axi_wvalid),
- .I1(s00_axi_awvalid),
- .I2(s00_axi_awready),
- .O(s_awready_i_1_n_0));
- FDRE s_awready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_awready_i_1_n_0),
- .Q(s00_axi_awready),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'hFF7F0000))
- \s_bresp[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(wb_we_o),
- .I2(wb_ack_i),
- .I3(s_bvalid),
- .I4(s00_axi_bresp),
- .O(\s_bresp[1]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_bresp_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_bresp[1]_i_1_n_0 ),
- .Q(s00_axi_bresp),
- .R(1'b0));
- LUT4 #(
- .INIT(16'h0F88))
- s_bvalid_i_1
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .I2(s00_axi_bready),
- .I3(s_bvalid),
- .O(s_bvalid_i_1_n_0));
- FDRE s_bvalid_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_bvalid_i_1_n_0),
- .Q(s_bvalid),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[0]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [0]),
- .Q(s00_axi_rdata[0]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[1]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [1]),
- .Q(s00_axi_rdata[1]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[2]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [2]),
- .Q(s00_axi_rdata[2]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[3]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [3]),
- .Q(s00_axi_rdata[3]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[4]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [4]),
- .Q(s00_axi_rdata[4]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[5]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [5]),
- .Q(s00_axi_rdata[5]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[6]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [6]),
- .Q(s00_axi_rdata[6]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[7]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [7]),
- .Q(s00_axi_rdata[7]),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT4 #(
- .INIT(16'h4F44))
- s_rvalid_i_1
- (.I0(s00_axi_rready),
- .I1(s_rvalid),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(s_rvalid_i_1_n_0));
- FDRE s_rvalid_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_rvalid_i_1_n_0),
- .Q(s_rvalid),
- .R(wb_rst_o));
- FDRE s_stb_r_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(iack_o_reg_0),
- .Q(wb_cyc_o),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h00E0))
- s_we_r_i_1
- (.I0(wb_we_o),
- .I1(s00_axi_awvalid),
- .I2(s00_axi_aresetn),
- .I3(s00_axi_arvalid),
- .O(s_we_r_i_1_n_0));
- FDRE s_we_r_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_we_r_i_1_n_0),
- .Q(wb_we_o),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'h08))
- s_wready_i_1
- (.I0(s00_axi_wvalid),
- .I1(s00_axi_awvalid),
- .I2(s00_axi_wready),
- .O(s_wready_i_1_n_0));
- FDRE s_wready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_wready_i_1_n_0),
- .Q(s00_axi_wready),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h8000FFFF))
- \txr[7]_i_1
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .I2(wb_adr_o[0]),
- .I3(wb_adr_o[1]),
- .I4(s00_axi_aresetn),
- .O(E));
-endmodule
-
-(* ORIG_REF_NAME = "i2c_master_bit_ctrl" *)
-module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
- (iscl_oen_reg_0,
- E,
- irq_flag1_out,
- al,
- D,
- \statemachine.core_cmd_reg[3] ,
- \statemachine.ld_reg ,
- \statemachine.core_txd_reg ,
- \statemachine.shift_reg ,
- \statemachine.host_ack_reg ,
- \statemachine.ack_out_reg ,
- \cr_reg[4] ,
- \sr_reg[0] ,
- \FSM_sequential_statemachine.c_state_reg[2] ,
- i2c_sda_io,
- i2c_scl_io,
- s00_axi_aclk,
- s00_axi_aresetn,
- out,
- \cr_reg[0] ,
- cmd_ack,
- irq_flag,
- Q,
- \ctr_reg[7] ,
- \statemachine.core_cmd_reg[3]_0 ,
- \st_irq_block.al_reg ,
- \cr_reg[7] ,
- wb_adr_o,
- \sr_reg[6] ,
- \txr_reg[6] ,
- \FSM_sequential_statemachine.c_state_reg[1] ,
- core_cmd,
- \FSM_sequential_statemachine.c_state_reg[1]_0 ,
- cnt_done,
- ack_out,
- iack_o_reg,
- wb_we_o,
- iack_o_reg_0,
- \statemachine.ld_reg_0 ,
- \FSM_sequential_statemachine.c_state_reg[1]_1 ,
- \FSM_sequential_statemachine.c_state_reg[1]_2 ,
- ack_in,
- \sr_reg[7] ,
- \cr_reg[7]_0 ,
- \statemachine.core_txd_reg_0 );
- output iscl_oen_reg_0;
- output [0:0]E;
- output irq_flag1_out;
- output al;
- output [0:0]D;
- output [3:0]\statemachine.core_cmd_reg[3] ;
- output \statemachine.ld_reg ;
- output \statemachine.core_txd_reg ;
- output \statemachine.shift_reg ;
- output \statemachine.host_ack_reg ;
- output \statemachine.ack_out_reg ;
- output [0:0]\cr_reg[4] ;
- output [0:0]\sr_reg[0] ;
- output [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [2:0]out;
- input \cr_reg[0] ;
- input cmd_ack;
- input irq_flag;
- input [15:0]Q;
- input [0:0]\ctr_reg[7] ;
- input [3:0]\statemachine.core_cmd_reg[3]_0 ;
- input \st_irq_block.al_reg ;
- input [3:0]\cr_reg[7] ;
- input [2:0]wb_adr_o;
- input \sr_reg[6] ;
- input [1:0]\txr_reg[6] ;
- input \FSM_sequential_statemachine.c_state_reg[1] ;
- input [0:0]core_cmd;
- input \FSM_sequential_statemachine.c_state_reg[1]_0 ;
- input cnt_done;
- input ack_out;
- input iack_o_reg;
- input wb_we_o;
- input iack_o_reg_0;
- input \statemachine.ld_reg_0 ;
- input \FSM_sequential_statemachine.c_state_reg[1]_1 ;
- input \FSM_sequential_statemachine.c_state_reg[1]_2 ;
- input ack_in;
- input [0:0]\sr_reg[7] ;
- input \cr_reg[7]_0 ;
- input \statemachine.core_txd_reg_0 ;
-
- wire [0:0]D;
- wire [0:0]E;
- wire \FSM_sequential_c_state[0]_i_1_n_0 ;
- wire \FSM_sequential_c_state[0]_i_2_n_0 ;
- wire \FSM_sequential_c_state[1]_i_1_n_0 ;
- wire \FSM_sequential_c_state[1]_i_2_n_0 ;
- wire \FSM_sequential_c_state[1]_i_3_n_0 ;
- wire \FSM_sequential_c_state[2]_i_1_n_0 ;
- wire \FSM_sequential_c_state[2]_i_2_n_0 ;
- wire \FSM_sequential_c_state[3]_i_1_n_0 ;
- wire \FSM_sequential_c_state[3]_i_2_n_0 ;
- wire \FSM_sequential_c_state[3]_i_3_n_0 ;
- wire \FSM_sequential_c_state[4]_i_1_n_0 ;
- wire \FSM_sequential_c_state[4]_i_2_n_0 ;
- wire \FSM_sequential_c_state[4]_i_3_n_0 ;
- wire \FSM_sequential_statemachine.c_state[2]_i_3_n_0 ;
- wire \FSM_sequential_statemachine.c_state_reg[1] ;
- wire \FSM_sequential_statemachine.c_state_reg[1]_0 ;
- wire \FSM_sequential_statemachine.c_state_reg[1]_1 ;
- wire \FSM_sequential_statemachine.c_state_reg[1]_2 ;
- wire [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
- wire [15:0]Q;
- wire ack_in;
- wire ack_out;
- wire al;
- wire \bus_status_ctrl.cSCL[0]_i_1_n_0 ;
- wire \bus_status_ctrl.cSCL[1]_i_1_n_0 ;
- wire \bus_status_ctrl.cSDA[0]_i_1_n_0 ;
- wire \bus_status_ctrl.cSDA[1]_i_1_n_0 ;
- wire \bus_status_ctrl.cSDA_reg_n_0_[1] ;
- wire \bus_status_ctrl.cmd_stop_i_1_n_0 ;
- wire \bus_status_ctrl.cmd_stop_i_2_n_0 ;
- wire \bus_status_ctrl.cmd_stop_reg_n_0 ;
- wire \bus_status_ctrl.dSCL_i_1_n_0 ;
- wire \bus_status_ctrl.dSDA_i_1_n_0 ;
- wire \bus_status_ctrl.dout_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL[0]_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL[1]_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL[2]_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL_reg_n_0_[2] ;
- wire \bus_status_ctrl.fSDA[0]_i_1_n_0 ;
- wire \bus_status_ctrl.fSDA[1]_i_1_n_0 ;
- wire \bus_status_ctrl.fSDA[2]_i_1_n_0 ;
- wire \bus_status_ctrl.fSDA[2]_i_2_n_0 ;
- wire \bus_status_ctrl.fSDA_reg_n_0_[0] ;
- wire \bus_status_ctrl.fSDA_reg_n_0_[1] ;
- wire \bus_status_ctrl.fSDA_reg_n_0_[2] ;
- wire \bus_status_ctrl.filter_cnt[0]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[10]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[11]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[12]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_2_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_3_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_4_n_0 ;
- wire \bus_status_ctrl.filter_cnt[1]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[2]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[3]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[4]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[5]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[6]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[7]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[8]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[9]_i_1_n_0 ;
- wire \bus_status_ctrl.ial_i_2_n_0 ;
- wire \bus_status_ctrl.ial_i_3_n_0 ;
- wire \bus_status_ctrl.sSCL_i_1_n_0 ;
- wire \bus_status_ctrl.sSDA_i_1_n_0 ;
- wire \bus_status_ctrl.sta_condition_reg_n_0 ;
- wire \bus_status_ctrl.sto_condition_reg_n_0 ;
- (* RTL_KEEP = "yes" *) wire [4:0]c_state;
- wire clk_en;
- wire clk_en_i_2_n_0;
- wire clk_en_i_3_n_0;
- wire clk_en_i_4_n_0;
- wire clk_en_i_5_n_0;
- wire clk_en_i_6_n_0;
- wire cmd_ack;
- wire cmd_ack3_out;
- wire cmd_ack_i_2_n_0;
- wire cnt1;
- wire \cnt[0]_i_10_n_0 ;
- wire \cnt[0]_i_1_n_0 ;
- wire \cnt[0]_i_3_n_0 ;
- wire \cnt[0]_i_4_n_0 ;
- wire \cnt[0]_i_5_n_0 ;
- wire \cnt[0]_i_6_n_0 ;
- wire \cnt[0]_i_7_n_0 ;
- wire \cnt[0]_i_8_n_0 ;
- wire \cnt[0]_i_9_n_0 ;
- wire \cnt[12]_i_2_n_0 ;
- wire \cnt[12]_i_3_n_0 ;
- wire \cnt[12]_i_4_n_0 ;
- wire \cnt[12]_i_5_n_0 ;
- wire \cnt[12]_i_6_n_0 ;
- wire \cnt[12]_i_7_n_0 ;
- wire \cnt[12]_i_8_n_0 ;
- wire \cnt[4]_i_2_n_0 ;
- wire \cnt[4]_i_3_n_0 ;
- wire \cnt[4]_i_4_n_0 ;
- wire \cnt[4]_i_5_n_0 ;
- wire \cnt[4]_i_6_n_0 ;
- wire \cnt[4]_i_7_n_0 ;
- wire \cnt[4]_i_8_n_0 ;
- wire \cnt[4]_i_9_n_0 ;
- wire \cnt[8]_i_2_n_0 ;
- wire \cnt[8]_i_3_n_0 ;
- wire \cnt[8]_i_4_n_0 ;
- wire \cnt[8]_i_5_n_0 ;
- wire \cnt[8]_i_6_n_0 ;
- wire \cnt[8]_i_7_n_0 ;
- wire \cnt[8]_i_8_n_0 ;
- wire \cnt[8]_i_9_n_0 ;
- wire cnt_done;
- wire [15:0]cnt_reg;
- wire \cnt_reg[0]_i_2_n_0 ;
- wire \cnt_reg[0]_i_2_n_1 ;
- wire \cnt_reg[0]_i_2_n_2 ;
- wire \cnt_reg[0]_i_2_n_3 ;
- wire \cnt_reg[0]_i_2_n_4 ;
- wire \cnt_reg[0]_i_2_n_5 ;
- wire \cnt_reg[0]_i_2_n_6 ;
- wire \cnt_reg[0]_i_2_n_7 ;
- wire \cnt_reg[12]_i_1_n_1 ;
- wire \cnt_reg[12]_i_1_n_2 ;
- wire \cnt_reg[12]_i_1_n_3 ;
- wire \cnt_reg[12]_i_1_n_4 ;
- wire \cnt_reg[12]_i_1_n_5 ;
- wire \cnt_reg[12]_i_1_n_6 ;
- wire \cnt_reg[12]_i_1_n_7 ;
- wire \cnt_reg[4]_i_1_n_0 ;
- wire \cnt_reg[4]_i_1_n_1 ;
- wire \cnt_reg[4]_i_1_n_2 ;
- wire \cnt_reg[4]_i_1_n_3 ;
- wire \cnt_reg[4]_i_1_n_4 ;
- wire \cnt_reg[4]_i_1_n_5 ;
- wire \cnt_reg[4]_i_1_n_6 ;
- wire \cnt_reg[4]_i_1_n_7 ;
- wire \cnt_reg[8]_i_1_n_0 ;
- wire \cnt_reg[8]_i_1_n_1 ;
- wire \cnt_reg[8]_i_1_n_2 ;
- wire \cnt_reg[8]_i_1_n_3 ;
- wire \cnt_reg[8]_i_1_n_4 ;
- wire \cnt_reg[8]_i_1_n_5 ;
- wire \cnt_reg[8]_i_1_n_6 ;
- wire \cnt_reg[8]_i_1_n_7 ;
- wire core_ack;
- wire [0:0]core_cmd;
- wire core_rxd;
- wire core_txd;
- wire \cr_reg[0] ;
- wire [0:0]\cr_reg[4] ;
- wire [3:0]\cr_reg[7] ;
- wire \cr_reg[7]_0 ;
- wire [0:0]\ctr_reg[7] ;
- wire dSCL;
- wire dSDA;
- wire dscl_oen;
- wire [13:0]filter_cnt;
- wire i2c_al;
- wire i2c_busy;
- wire i2c_scl_io;
- wire i2c_scl_io_INST_0_i_1_n_0;
- wire i2c_sda_io;
- wire i2c_sda_io_INST_0_i_1_n_0;
- wire iack_o_reg;
- wire iack_o_reg_0;
- wire ial;
- wire ibusy;
- wire irq_flag;
- wire irq_flag1_out;
- wire iscl_oen;
- wire iscl_oen9_out__0;
- wire iscl_oen_i_1_n_0;
- wire iscl_oen_reg_0;
- wire isda_oen;
- wire isda_oen7_out__0;
- wire isda_oen_i_1_n_0;
- wire minusOp_carry__0_i_1_n_0;
- wire minusOp_carry__0_i_2_n_0;
- wire minusOp_carry__0_i_3_n_0;
- wire minusOp_carry__0_i_4_n_0;
- wire minusOp_carry__0_n_0;
- wire minusOp_carry__0_n_1;
- wire minusOp_carry__0_n_2;
- wire minusOp_carry__0_n_3;
- wire minusOp_carry__0_n_4;
- wire minusOp_carry__0_n_5;
- wire minusOp_carry__0_n_6;
- wire minusOp_carry__0_n_7;
- wire minusOp_carry__1_i_1_n_0;
- wire minusOp_carry__1_i_2_n_0;
- wire minusOp_carry__1_i_3_n_0;
- wire minusOp_carry__1_i_4_n_0;
- wire minusOp_carry__1_n_0;
- wire minusOp_carry__1_n_1;
- wire minusOp_carry__1_n_2;
- wire minusOp_carry__1_n_3;
- wire minusOp_carry__1_n_4;
- wire minusOp_carry__1_n_5;
- wire minusOp_carry__1_n_6;
- wire minusOp_carry__1_n_7;
- wire minusOp_carry__2_i_1_n_0;
- wire minusOp_carry__2_n_7;
- wire minusOp_carry_i_1_n_0;
- wire minusOp_carry_i_2_n_0;
- wire minusOp_carry_i_3_n_0;
- wire minusOp_carry_i_4_n_0;
- wire minusOp_carry_n_0;
- wire minusOp_carry_n_1;
- wire minusOp_carry_n_2;
- wire minusOp_carry_n_3;
- wire minusOp_carry_n_4;
- wire minusOp_carry_n_5;
- wire minusOp_carry_n_6;
- wire minusOp_carry_n_7;
- wire [2:0]out;
- wire [1:1]p_0_in;
- wire [1:1]p_0_in__0;
- wire [2:0]p_0_in__1;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire sSCL;
- wire sSDA;
- wire scl_padoen_o;
- wire sda_chk_i_1_n_0;
- wire sda_chk_reg_n_0;
- wire sda_padoen_o;
- wire slave_wait;
- wire slave_wait0;
- wire [0:0]\sr_reg[0] ;
- wire \sr_reg[6] ;
- wire [0:0]\sr_reg[7] ;
- wire \st_irq_block.al_reg ;
- wire sta_condition;
- wire \statemachine.ack_out_i_2_n_0 ;
- wire \statemachine.ack_out_reg ;
- wire [3:0]\statemachine.core_cmd_reg[3] ;
- wire [3:0]\statemachine.core_cmd_reg[3]_0 ;
- wire \statemachine.core_txd_reg ;
- wire \statemachine.core_txd_reg_0 ;
- wire \statemachine.host_ack_reg ;
- wire \statemachine.ld_reg ;
- wire \statemachine.ld_reg_0 ;
- wire \statemachine.shift_reg ;
- wire sto_condition;
- wire [1:0]\txr_reg[6] ;
- wire [2:0]wb_adr_o;
- wire \wb_dat_o[6]_i_3_n_0 ;
- wire wb_we_o;
- wire [3:3]\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED ;
- wire [3:0]NLW_minusOp_carry__2_CO_UNCONNECTED;
- wire [3:1]NLW_minusOp_carry__2_O_UNCONNECTED;
-
- LUT6 #(
- .INIT(64'h1111111111111110))
- \FSM_sequential_c_state[0]_i_1
- (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .I1(c_state[0]),
- .I2(c_state[2]),
- .I3(c_state[3]),
- .I4(\FSM_sequential_c_state[0]_i_2_n_0 ),
- .I5(c_state[4]),
- .O(\FSM_sequential_c_state[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hAAAAAABA))
- \FSM_sequential_c_state[0]_i_2
- (.I0(c_state[1]),
- .I1(\statemachine.core_cmd_reg[3]_0 [1]),
- .I2(\statemachine.core_cmd_reg[3]_0 [0]),
- .I3(\statemachine.core_cmd_reg[3]_0 [3]),
- .I4(\statemachine.core_cmd_reg[3]_0 [2]),
- .O(\FSM_sequential_c_state[0]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h0400))
- \FSM_sequential_c_state[1]_i_1
- (.I0(i2c_al),
- .I1(s00_axi_aresetn),
- .I2(c_state[4]),
- .I3(\FSM_sequential_c_state[1]_i_2_n_0 ),
- .O(\FSM_sequential_c_state[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hEEEFEFFE44444444))
- \FSM_sequential_c_state[1]_i_2
- (.I0(c_state[0]),
- .I1(c_state[1]),
- .I2(\statemachine.core_cmd_reg[3]_0 [1]),
- .I3(\statemachine.core_cmd_reg[3]_0 [2]),
- .I4(\statemachine.core_cmd_reg[3]_0 [3]),
- .I5(\FSM_sequential_c_state[1]_i_3_n_0 ),
- .O(\FSM_sequential_c_state[1]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'h00001101))
- \FSM_sequential_c_state[1]_i_3
- (.I0(c_state[2]),
- .I1(c_state[1]),
- .I2(\statemachine.core_cmd_reg[3]_0 [0]),
- .I3(c_state[0]),
- .I4(c_state[3]),
- .O(\FSM_sequential_c_state[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0002A0A2AAAA0002))
- \FSM_sequential_c_state[2]_i_1
- (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
- .I1(c_state[3]),
- .I2(c_state[1]),
- .I3(\FSM_sequential_c_state[2]_i_2_n_0 ),
- .I4(c_state[2]),
- .I5(c_state[0]),
- .O(\FSM_sequential_c_state[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFEEF))
- \FSM_sequential_c_state[2]_i_2
- (.I0(c_state[0]),
- .I1(\statemachine.core_cmd_reg[3]_0 [3]),
- .I2(\statemachine.core_cmd_reg[3]_0 [1]),
- .I3(\statemachine.core_cmd_reg[3]_0 [2]),
- .I4(\statemachine.core_cmd_reg[3]_0 [0]),
- .O(\FSM_sequential_c_state[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0AA8A0A800A800A8))
- \FSM_sequential_c_state[3]_i_1
- (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
- .I1(\FSM_sequential_c_state[3]_i_3_n_0 ),
- .I2(c_state[3]),
- .I3(c_state[0]),
- .I4(c_state[2]),
- .I5(c_state[1]),
- .O(\FSM_sequential_c_state[3]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h04))
- \FSM_sequential_c_state[3]_i_2
- (.I0(c_state[4]),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .O(\FSM_sequential_c_state[3]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000006))
- \FSM_sequential_c_state[3]_i_3
- (.I0(\statemachine.core_cmd_reg[3]_0 [3]),
- .I1(\statemachine.core_cmd_reg[3]_0 [2]),
- .I2(\statemachine.core_cmd_reg[3]_0 [0]),
- .I3(\statemachine.core_cmd_reg[3]_0 [1]),
- .I4(c_state[1]),
- .I5(c_state[2]),
- .O(\FSM_sequential_c_state[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hBBBBBBBFAAAAAAAA))
- \FSM_sequential_c_state[4]_i_1
- (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .I1(c_state[4]),
- .I2(c_state[3]),
- .I3(c_state[1]),
- .I4(c_state[2]),
- .I5(clk_en),
- .O(\FSM_sequential_c_state[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000080FF8000))
- \FSM_sequential_c_state[4]_i_2
- (.I0(c_state[3]),
- .I1(c_state[1]),
- .I2(c_state[2]),
- .I3(c_state[0]),
- .I4(c_state[4]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\FSM_sequential_c_state[4]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT2 #(
- .INIT(4'hB))
- \FSM_sequential_c_state[4]_i_3
- (.I0(i2c_al),
- .I1(s00_axi_aresetn),
- .O(\FSM_sequential_c_state[4]_i_3_n_0 ));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[0]_i_1_n_0 ),
- .Q(c_state[0]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[1]_i_1_n_0 ),
- .Q(c_state[1]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[2]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[2]_i_1_n_0 ),
- .Q(c_state[2]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[3]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[3]_i_1_n_0 ),
- .Q(c_state[3]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[4]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[4]_i_2_n_0 ),
- .Q(c_state[4]));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \FSM_sequential_statemachine.c_state[0]_i_1
- (.I0(\FSM_sequential_statemachine.c_state_reg[1]_1 ),
- .I1(out[2]),
- .I2(out[1]),
- .I3(\cr_reg[7] [2]),
- .I4(out[0]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\FSM_sequential_statemachine.c_state_reg[2] [0]));
- LUT6 #(
- .INIT(64'h0000000015100000))
- \FSM_sequential_statemachine.c_state[1]_i_1
- (.I0(out[2]),
- .I1(cnt_done),
- .I2(out[1]),
- .I3(\cr_reg[7]_0 ),
- .I4(s00_axi_aresetn),
- .I5(i2c_al),
- .O(\FSM_sequential_statemachine.c_state_reg[2] [1]));
- LUT6 #(
- .INIT(64'hDDFFDDDDFFFDDDFD))
- \FSM_sequential_statemachine.c_state[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_al),
- .I2(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
- .I3(out[1]),
- .I4(core_ack),
- .I5(out[2]),
- .O(E));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \FSM_sequential_statemachine.c_state[2]_i_2
- (.I0(\FSM_sequential_statemachine.c_state_reg[1]_2 ),
- .I1(out[2]),
- .I2(out[1]),
- .I3(\cr_reg[7] [2]),
- .I4(out[0]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\FSM_sequential_statemachine.c_state_reg[2] [2]));
- LUT6 #(
- .INIT(64'h8B8B8B8B8B8B8B88))
- \FSM_sequential_statemachine.c_state[2]_i_3
- (.I0(core_ack),
- .I1(out[0]),
- .I2(cmd_ack),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [1]),
- .I5(\cr_reg[7] [2]),
- .O(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSCL[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_scl_io),
- .O(\bus_status_ctrl.cSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSCL[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(p_0_in__0),
- .O(\bus_status_ctrl.cSCL[1]_i_1_n_0 ));
- FDCE \bus_status_ctrl.cSCL_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSCL[0]_i_1_n_0 ),
- .Q(p_0_in__0));
- FDCE \bus_status_ctrl.cSCL_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSCL[1]_i_1_n_0 ),
- .Q(p_0_in__1[0]));
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSDA[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_sda_io),
- .O(\bus_status_ctrl.cSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSDA[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(p_0_in),
- .O(\bus_status_ctrl.cSDA[1]_i_1_n_0 ));
- FDCE \bus_status_ctrl.cSDA_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSDA[0]_i_1_n_0 ),
- .Q(p_0_in));
- FDCE \bus_status_ctrl.cSDA_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSDA[1]_i_1_n_0 ),
- .Q(\bus_status_ctrl.cSDA_reg_n_0_[1] ));
- LUT6 #(
- .INIT(64'h04FF000004000000))
- \bus_status_ctrl.cmd_stop_i_1
- (.I0(\statemachine.core_cmd_reg[3]_0 [0]),
- .I1(\statemachine.core_cmd_reg[3]_0 [1]),
- .I2(\bus_status_ctrl.cmd_stop_i_2_n_0 ),
- .I3(clk_en),
- .I4(s00_axi_aresetn),
- .I5(\bus_status_ctrl.cmd_stop_reg_n_0 ),
- .O(\bus_status_ctrl.cmd_stop_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \bus_status_ctrl.cmd_stop_i_2
- (.I0(\statemachine.core_cmd_reg[3]_0 [2]),
- .I1(\statemachine.core_cmd_reg[3]_0 [3]),
- .O(\bus_status_ctrl.cmd_stop_i_2_n_0 ));
- FDCE \bus_status_ctrl.cmd_stop_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cmd_stop_i_1_n_0 ),
- .Q(\bus_status_ctrl.cmd_stop_reg_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.dSCL_i_1
- (.I0(sSCL),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.dSCL_i_1_n_0 ));
- FDPE \bus_status_ctrl.dSCL_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.dSCL_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(dSCL));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.dSDA_i_1
- (.I0(sSDA),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.dSDA_i_1_n_0 ));
- FDPE \bus_status_ctrl.dSDA_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.dSDA_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(dSDA));
- LUT4 #(
- .INIT(16'hFB08))
- \bus_status_ctrl.dout_i_1
- (.I0(sSDA),
- .I1(sSCL),
- .I2(dSCL),
- .I3(core_rxd),
- .O(\bus_status_ctrl.dout_i_1_n_0 ));
- FDCE \bus_status_ctrl.dout_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.dout_i_1_n_0 ),
- .Q(core_rxd));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSCL[0]_i_1
- (.I0(p_0_in__1[0]),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSCL[1]_i_1
- (.I0(p_0_in__1[1]),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSCL[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSCL[2]_i_1
- (.I0(p_0_in__1[2]),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSCL[2]_i_1_n_0 ));
- FDPE \bus_status_ctrl.fSCL_reg[0]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSCL[0]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(p_0_in__1[1]));
- FDPE \bus_status_ctrl.fSCL_reg[1]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSCL[1]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(p_0_in__1[2]));
- FDPE \bus_status_ctrl.fSCL_reg[2]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSCL[2]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSCL_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[0]_i_1
- (.I0(\bus_status_ctrl.cSDA_reg_n_0_[1] ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[1]_i_1
- (.I0(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[1]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[2]_i_1
- (.I0(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[2]_i_2
- (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[2]_i_2_n_0 ));
- FDPE \bus_status_ctrl.fSDA_reg[0]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSDA[0]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSDA_reg_n_0_[0] ));
- FDPE \bus_status_ctrl.fSDA_reg[1]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSDA[1]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSDA_reg_n_0_[1] ));
- FDPE \bus_status_ctrl.fSDA_reg[2]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSDA[2]_i_2_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSDA_reg_n_0_[2] ));
- LUT5 #(
- .INIT(32'hD1000000))
- \bus_status_ctrl.filter_cnt[0]_i_1
- (.I0(filter_cnt[0]),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[2]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[10]_i_1
- (.I0(minusOp_carry__1_n_6),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[12]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[11]_i_1
- (.I0(minusOp_carry__1_n_5),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[13]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[12]_i_1
- (.I0(minusOp_carry__1_n_4),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[14]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[13]_i_1
- (.I0(minusOp_carry__2_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[15]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \bus_status_ctrl.filter_cnt[13]_i_2
- (.I0(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ),
- .I2(filter_cnt[6]),
- .I3(filter_cnt[7]),
- .I4(filter_cnt[4]),
- .I5(filter_cnt[5]),
- .O(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \bus_status_ctrl.filter_cnt[13]_i_3
- (.I0(filter_cnt[13]),
- .I1(filter_cnt[12]),
- .I2(filter_cnt[9]),
- .I3(filter_cnt[8]),
- .I4(filter_cnt[11]),
- .I5(filter_cnt[10]),
- .O(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \bus_status_ctrl.filter_cnt[13]_i_4
- (.I0(filter_cnt[2]),
- .I1(filter_cnt[3]),
- .I2(filter_cnt[0]),
- .I3(filter_cnt[1]),
- .O(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[1]_i_1
- (.I0(minusOp_carry_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[3]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[2]_i_1
- (.I0(minusOp_carry_n_6),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[4]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[3]_i_1
- (.I0(minusOp_carry_n_5),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[5]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[4]_i_1
- (.I0(minusOp_carry_n_4),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[6]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[5]_i_1
- (.I0(minusOp_carry__0_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[7]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[6]_i_1
- (.I0(minusOp_carry__0_n_6),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[8]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[7]_i_1
- (.I0(minusOp_carry__0_n_5),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[9]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[8]_i_1
- (.I0(minusOp_carry__0_n_4),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[10]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[9]_i_1
- (.I0(minusOp_carry__1_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[11]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ));
- FDCE \bus_status_ctrl.filter_cnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ),
- .Q(filter_cnt[0]));
- FDCE \bus_status_ctrl.filter_cnt_reg[10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ),
- .Q(filter_cnt[10]));
- FDCE \bus_status_ctrl.filter_cnt_reg[11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ),
- .Q(filter_cnt[11]));
- FDCE \bus_status_ctrl.filter_cnt_reg[12]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ),
- .Q(filter_cnt[12]));
- FDCE \bus_status_ctrl.filter_cnt_reg[13]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ),
- .Q(filter_cnt[13]));
- FDCE \bus_status_ctrl.filter_cnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ),
- .Q(filter_cnt[1]));
- FDCE \bus_status_ctrl.filter_cnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ),
- .Q(filter_cnt[2]));
- FDCE \bus_status_ctrl.filter_cnt_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ),
- .Q(filter_cnt[3]));
- FDCE \bus_status_ctrl.filter_cnt_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ),
- .Q(filter_cnt[4]));
- FDCE \bus_status_ctrl.filter_cnt_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ),
- .Q(filter_cnt[5]));
- FDCE \bus_status_ctrl.filter_cnt_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ),
- .Q(filter_cnt[6]));
- FDCE \bus_status_ctrl.filter_cnt_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ),
- .Q(filter_cnt[7]));
- FDCE \bus_status_ctrl.filter_cnt_reg[8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ),
- .Q(filter_cnt[8]));
- FDCE \bus_status_ctrl.filter_cnt_reg[9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ),
- .Q(filter_cnt[9]));
- LUT6 #(
- .INIT(64'h08000800AAAA0800))
- \bus_status_ctrl.ial_i_1
- (.I0(s00_axi_aresetn),
- .I1(sda_chk_reg_n_0),
- .I2(sSDA),
- .I3(sda_padoen_o),
- .I4(\bus_status_ctrl.ial_i_2_n_0 ),
- .I5(\bus_status_ctrl.ial_i_3_n_0 ),
- .O(ial));
- LUT2 #(
- .INIT(4'h1))
- \bus_status_ctrl.ial_i_2
- (.I0(c_state[0]),
- .I1(c_state[4]),
- .O(\bus_status_ctrl.ial_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFEF))
- \bus_status_ctrl.ial_i_3
- (.I0(c_state[2]),
- .I1(c_state[3]),
- .I2(\bus_status_ctrl.sto_condition_reg_n_0 ),
- .I3(\bus_status_ctrl.cmd_stop_reg_n_0 ),
- .I4(c_state[1]),
- .O(\bus_status_ctrl.ial_i_3_n_0 ));
- FDCE \bus_status_ctrl.ial_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(ial),
- .Q(i2c_al));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h5400))
- \bus_status_ctrl.ibusy_i_1
- (.I0(\bus_status_ctrl.sto_condition_reg_n_0 ),
- .I1(\bus_status_ctrl.sta_condition_reg_n_0 ),
- .I2(i2c_busy),
- .I3(s00_axi_aresetn),
- .O(ibusy));
- FDCE \bus_status_ctrl.ibusy_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(ibusy),
- .Q(i2c_busy));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'hE8FF))
- \bus_status_ctrl.sSCL_i_1
- (.I0(p_0_in__1[2]),
- .I1(\bus_status_ctrl.fSCL_reg_n_0_[2] ),
- .I2(p_0_in__1[1]),
- .I3(s00_axi_aresetn),
- .O(\bus_status_ctrl.sSCL_i_1_n_0 ));
- FDPE \bus_status_ctrl.sSCL_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.sSCL_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(sSCL));
- LUT4 #(
- .INIT(16'hE8FF))
- \bus_status_ctrl.sSDA_i_1
- (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
- .I1(\bus_status_ctrl.fSDA_reg_n_0_[2] ),
- .I2(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
- .I3(s00_axi_aresetn),
- .O(\bus_status_ctrl.sSDA_i_1_n_0 ));
- FDPE \bus_status_ctrl.sSDA_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.sSDA_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(sSDA));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h2000))
- \bus_status_ctrl.sta_condition_i_1
- (.I0(dSDA),
- .I1(sSDA),
- .I2(s00_axi_aresetn),
- .I3(sSCL),
- .O(sta_condition));
- FDCE \bus_status_ctrl.sta_condition_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(sta_condition),
- .Q(\bus_status_ctrl.sta_condition_reg_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h4000))
- \bus_status_ctrl.sto_condition_i_1
- (.I0(dSDA),
- .I1(s00_axi_aresetn),
- .I2(sSCL),
- .I3(sSDA),
- .O(sto_condition));
- FDCE \bus_status_ctrl.sto_condition_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(sto_condition),
- .Q(\bus_status_ctrl.sto_condition_reg_n_0 ));
- LUT5 #(
- .INIT(32'hAAAAAAAB))
- clk_en_i_1
- (.I0(clk_en_i_2_n_0),
- .I1(clk_en_i_3_n_0),
- .I2(clk_en_i_4_n_0),
- .I3(clk_en_i_5_n_0),
- .I4(clk_en_i_6_n_0),
- .O(cnt1));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT5 #(
- .INIT(32'h7555FFFF))
- clk_en_i_2
- (.I0(\ctr_reg[7] ),
- .I1(sSCL),
- .I2(scl_padoen_o),
- .I3(dSCL),
- .I4(s00_axi_aresetn),
- .O(clk_en_i_2_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_3
- (.I0(cnt_reg[6]),
- .I1(cnt_reg[7]),
- .I2(cnt_reg[4]),
- .I3(cnt_reg[5]),
- .O(clk_en_i_3_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_4
- (.I0(cnt_reg[2]),
- .I1(cnt_reg[3]),
- .I2(cnt_reg[0]),
- .I3(cnt_reg[1]),
- .O(clk_en_i_4_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_5
- (.I0(cnt_reg[15]),
- .I1(cnt_reg[14]),
- .I2(cnt_reg[12]),
- .I3(cnt_reg[13]),
- .O(clk_en_i_5_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_6
- (.I0(cnt_reg[10]),
- .I1(cnt_reg[11]),
- .I2(cnt_reg[8]),
- .I3(cnt_reg[9]),
- .O(clk_en_i_6_n_0));
- FDPE clk_en_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cnt1),
- .PRE(iscl_oen_reg_0),
- .Q(clk_en));
- LUT6 #(
- .INIT(64'h0008000000000000))
- cmd_ack_i_1
- (.I0(cmd_ack_i_2_n_0),
- .I1(c_state[0]),
- .I2(c_state[1]),
- .I3(i2c_al),
- .I4(s00_axi_aresetn),
- .I5(clk_en),
- .O(cmd_ack3_out));
- LUT3 #(
- .INIT(8'h1E))
- cmd_ack_i_2
- (.I0(c_state[2]),
- .I1(c_state[3]),
- .I2(c_state[4]),
- .O(cmd_ack_i_2_n_0));
- FDCE cmd_ack_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(cmd_ack3_out),
- .Q(core_ack));
- LUT2 #(
- .INIT(4'hB))
- \cnt[0]_i_1
- (.I0(cnt1),
- .I1(slave_wait),
- .O(\cnt[0]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_10
- (.I0(cnt_reg[0]),
- .I1(Q[0]),
- .I2(cnt1),
- .O(\cnt[0]_i_10_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_3
- (.I0(Q[3]),
- .I1(cnt1),
- .I2(cnt_reg[3]),
- .O(\cnt[0]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_4
- (.I0(Q[2]),
- .I1(cnt1),
- .I2(cnt_reg[2]),
- .O(\cnt[0]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_5
- (.I0(Q[1]),
- .I1(cnt1),
- .I2(cnt_reg[1]),
- .O(\cnt[0]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_6
- (.I0(Q[0]),
- .I1(cnt1),
- .I2(cnt_reg[0]),
- .O(\cnt[0]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_7
- (.I0(cnt_reg[3]),
- .I1(Q[3]),
- .I2(cnt1),
- .O(\cnt[0]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_8
- (.I0(cnt_reg[2]),
- .I1(Q[2]),
- .I2(cnt1),
- .O(\cnt[0]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_9
- (.I0(cnt_reg[1]),
- .I1(Q[1]),
- .I2(cnt1),
- .O(\cnt[0]_i_9_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[12]_i_2
- (.I0(Q[14]),
- .I1(cnt1),
- .I2(cnt_reg[14]),
- .O(\cnt[12]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[12]_i_3
- (.I0(Q[13]),
- .I1(cnt1),
- .I2(cnt_reg[13]),
- .O(\cnt[12]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[12]_i_4
- (.I0(Q[12]),
- .I1(cnt1),
- .I2(cnt_reg[12]),
- .O(\cnt[12]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_5
- (.I0(cnt_reg[15]),
- .I1(Q[15]),
- .I2(cnt1),
- .O(\cnt[12]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_6
- (.I0(cnt_reg[14]),
- .I1(Q[14]),
- .I2(cnt1),
- .O(\cnt[12]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_7
- (.I0(cnt_reg[13]),
- .I1(Q[13]),
- .I2(cnt1),
- .O(\cnt[12]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_8
- (.I0(cnt_reg[12]),
- .I1(Q[12]),
- .I2(cnt1),
- .O(\cnt[12]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_2
- (.I0(Q[7]),
- .I1(cnt1),
- .I2(cnt_reg[7]),
- .O(\cnt[4]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_3
- (.I0(Q[6]),
- .I1(cnt1),
- .I2(cnt_reg[6]),
- .O(\cnt[4]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_4
- (.I0(Q[5]),
- .I1(cnt1),
- .I2(cnt_reg[5]),
- .O(\cnt[4]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_5
- (.I0(Q[4]),
- .I1(cnt1),
- .I2(cnt_reg[4]),
- .O(\cnt[4]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_6
- (.I0(cnt_reg[7]),
- .I1(Q[7]),
- .I2(cnt1),
- .O(\cnt[4]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_7
- (.I0(cnt_reg[6]),
- .I1(Q[6]),
- .I2(cnt1),
- .O(\cnt[4]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_8
- (.I0(cnt_reg[5]),
- .I1(Q[5]),
- .I2(cnt1),
- .O(\cnt[4]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_9
- (.I0(cnt_reg[4]),
- .I1(Q[4]),
- .I2(cnt1),
- .O(\cnt[4]_i_9_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_2
- (.I0(Q[11]),
- .I1(cnt1),
- .I2(cnt_reg[11]),
- .O(\cnt[8]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_3
- (.I0(Q[10]),
- .I1(cnt1),
- .I2(cnt_reg[10]),
- .O(\cnt[8]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_4
- (.I0(Q[9]),
- .I1(cnt1),
- .I2(cnt_reg[9]),
- .O(\cnt[8]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_5
- (.I0(Q[8]),
- .I1(cnt1),
- .I2(cnt_reg[8]),
- .O(\cnt[8]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_6
- (.I0(cnt_reg[11]),
- .I1(Q[11]),
- .I2(cnt1),
- .O(\cnt[8]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_7
- (.I0(cnt_reg[10]),
- .I1(Q[10]),
- .I2(cnt1),
- .O(\cnt[8]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_8
- (.I0(cnt_reg[9]),
- .I1(Q[9]),
- .I2(cnt1),
- .O(\cnt[8]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_9
- (.I0(cnt_reg[8]),
- .I1(Q[8]),
- .I2(cnt1),
- .O(\cnt[8]_i_9_n_0 ));
- FDCE \cnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_7 ),
- .Q(cnt_reg[0]));
- CARRY4 \cnt_reg[0]_i_2
- (.CI(1'b0),
- .CO({\cnt_reg[0]_i_2_n_0 ,\cnt_reg[0]_i_2_n_1 ,\cnt_reg[0]_i_2_n_2 ,\cnt_reg[0]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({\cnt[0]_i_3_n_0 ,\cnt[0]_i_4_n_0 ,\cnt[0]_i_5_n_0 ,\cnt[0]_i_6_n_0 }),
- .O({\cnt_reg[0]_i_2_n_4 ,\cnt_reg[0]_i_2_n_5 ,\cnt_reg[0]_i_2_n_6 ,\cnt_reg[0]_i_2_n_7 }),
- .S({\cnt[0]_i_7_n_0 ,\cnt[0]_i_8_n_0 ,\cnt[0]_i_9_n_0 ,\cnt[0]_i_10_n_0 }));
- FDCE \cnt_reg[10]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_5 ),
- .Q(cnt_reg[10]));
- FDCE \cnt_reg[11]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_4 ),
- .Q(cnt_reg[11]));
- FDCE \cnt_reg[12]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_7 ),
- .Q(cnt_reg[12]));
- CARRY4 \cnt_reg[12]_i_1
- (.CI(\cnt_reg[8]_i_1_n_0 ),
- .CO({\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED [3],\cnt_reg[12]_i_1_n_1 ,\cnt_reg[12]_i_1_n_2 ,\cnt_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,\cnt[12]_i_2_n_0 ,\cnt[12]_i_3_n_0 ,\cnt[12]_i_4_n_0 }),
- .O({\cnt_reg[12]_i_1_n_4 ,\cnt_reg[12]_i_1_n_5 ,\cnt_reg[12]_i_1_n_6 ,\cnt_reg[12]_i_1_n_7 }),
- .S({\cnt[12]_i_5_n_0 ,\cnt[12]_i_6_n_0 ,\cnt[12]_i_7_n_0 ,\cnt[12]_i_8_n_0 }));
- FDCE \cnt_reg[13]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_6 ),
- .Q(cnt_reg[13]));
- FDCE \cnt_reg[14]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_5 ),
- .Q(cnt_reg[14]));
- FDCE \cnt_reg[15]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_4 ),
- .Q(cnt_reg[15]));
- FDCE \cnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_6 ),
- .Q(cnt_reg[1]));
- FDCE \cnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_5 ),
- .Q(cnt_reg[2]));
- FDCE \cnt_reg[3]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_4 ),
- .Q(cnt_reg[3]));
- FDCE \cnt_reg[4]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_7 ),
- .Q(cnt_reg[4]));
- CARRY4 \cnt_reg[4]_i_1
- (.CI(\cnt_reg[0]_i_2_n_0 ),
- .CO({\cnt_reg[4]_i_1_n_0 ,\cnt_reg[4]_i_1_n_1 ,\cnt_reg[4]_i_1_n_2 ,\cnt_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({\cnt[4]_i_2_n_0 ,\cnt[4]_i_3_n_0 ,\cnt[4]_i_4_n_0 ,\cnt[4]_i_5_n_0 }),
- .O({\cnt_reg[4]_i_1_n_4 ,\cnt_reg[4]_i_1_n_5 ,\cnt_reg[4]_i_1_n_6 ,\cnt_reg[4]_i_1_n_7 }),
- .S({\cnt[4]_i_6_n_0 ,\cnt[4]_i_7_n_0 ,\cnt[4]_i_8_n_0 ,\cnt[4]_i_9_n_0 }));
- FDCE \cnt_reg[5]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_6 ),
- .Q(cnt_reg[5]));
- FDCE \cnt_reg[6]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_5 ),
- .Q(cnt_reg[6]));
- FDCE \cnt_reg[7]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_4 ),
- .Q(cnt_reg[7]));
- FDCE \cnt_reg[8]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_7 ),
- .Q(cnt_reg[8]));
- CARRY4 \cnt_reg[8]_i_1
- (.CI(\cnt_reg[4]_i_1_n_0 ),
- .CO({\cnt_reg[8]_i_1_n_0 ,\cnt_reg[8]_i_1_n_1 ,\cnt_reg[8]_i_1_n_2 ,\cnt_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({\cnt[8]_i_2_n_0 ,\cnt[8]_i_3_n_0 ,\cnt[8]_i_4_n_0 ,\cnt[8]_i_5_n_0 }),
- .O({\cnt_reg[8]_i_1_n_4 ,\cnt_reg[8]_i_1_n_5 ,\cnt_reg[8]_i_1_n_6 ,\cnt_reg[8]_i_1_n_7 }),
- .S({\cnt[8]_i_6_n_0 ,\cnt[8]_i_7_n_0 ,\cnt[8]_i_8_n_0 ,\cnt[8]_i_9_n_0 }));
- FDCE \cnt_reg[9]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_6 ),
- .Q(cnt_reg[9]));
- LUT6 #(
- .INIT(64'h55FDFDFDFFFFFFFF))
- \cr[7]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_al),
- .I2(cmd_ack),
- .I3(iack_o_reg),
- .I4(wb_we_o),
- .I5(iack_o_reg_0),
- .O(\cr_reg[4] ));
- FDCE dscl_oen_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(scl_padoen_o),
- .Q(dscl_oen));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_scl_io_INST_0
- (.I0(1'b0),
- .I1(i2c_scl_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_scl_io));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_scl_io_INST_0_i_1
- (.I0(scl_padoen_o),
- .O(i2c_scl_io_INST_0_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_sda_io_INST_0
- (.I0(1'b0),
- .I1(i2c_sda_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_sda_io));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_sda_io_INST_0_i_1
- (.I0(sda_padoen_o),
- .O(i2c_sda_io_INST_0_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT5 #(
- .INIT(32'hFBFFFBF3))
- iscl_oen_i_1
- (.I0(iscl_oen),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .I3(iscl_oen9_out__0),
- .I4(scl_padoen_o),
- .O(iscl_oen_i_1_n_0));
- LUT5 #(
- .INIT(32'h00F3011F))
- iscl_oen_i_2
- (.I0(c_state[3]),
- .I1(c_state[2]),
- .I2(c_state[1]),
- .I3(c_state[4]),
- .I4(c_state[0]),
- .O(iscl_oen));
- LUT5 #(
- .INIT(32'h55560000))
- iscl_oen_i_3
- (.I0(c_state[4]),
- .I1(c_state[3]),
- .I2(c_state[2]),
- .I3(c_state[1]),
- .I4(clk_en),
- .O(iscl_oen9_out__0));
- FDPE iscl_oen_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(iscl_oen_i_1_n_0),
- .PRE(iscl_oen_reg_0),
- .Q(scl_padoen_o));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT5 #(
- .INIT(32'hFBFFFBF3))
- isda_oen_i_1
- (.I0(isda_oen),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .I3(isda_oen7_out__0),
- .I4(sda_padoen_o),
- .O(isda_oen_i_1_n_0));
- LUT6 #(
- .INIT(64'h0000C8CB03038F83))
- isda_oen_i_2
- (.I0(\statemachine.core_txd_reg_0 ),
- .I1(c_state[3]),
- .I2(c_state[2]),
- .I3(c_state[0]),
- .I4(c_state[4]),
- .I5(c_state[1]),
- .O(isda_oen));
- LUT6 #(
- .INIT(64'h0F0F1F1E00000000))
- isda_oen_i_3
- (.I0(c_state[1]),
- .I1(c_state[2]),
- .I2(c_state[4]),
- .I3(c_state[0]),
- .I4(c_state[3]),
- .I5(clk_en),
- .O(isda_oen7_out__0));
- FDPE isda_oen_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(isda_oen_i_1_n_0),
- .PRE(iscl_oen_reg_0),
- .Q(sda_padoen_o));
- CARRY4 minusOp_carry
- (.CI(1'b0),
- .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
- .CYINIT(filter_cnt[0]),
- .DI(filter_cnt[4:1]),
- .O({minusOp_carry_n_4,minusOp_carry_n_5,minusOp_carry_n_6,minusOp_carry_n_7}),
- .S({minusOp_carry_i_1_n_0,minusOp_carry_i_2_n_0,minusOp_carry_i_3_n_0,minusOp_carry_i_4_n_0}));
- CARRY4 minusOp_carry__0
- (.CI(minusOp_carry_n_0),
- .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI(filter_cnt[8:5]),
- .O({minusOp_carry__0_n_4,minusOp_carry__0_n_5,minusOp_carry__0_n_6,minusOp_carry__0_n_7}),
- .S({minusOp_carry__0_i_1_n_0,minusOp_carry__0_i_2_n_0,minusOp_carry__0_i_3_n_0,minusOp_carry__0_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_1
- (.I0(filter_cnt[8]),
- .O(minusOp_carry__0_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_2
- (.I0(filter_cnt[7]),
- .O(minusOp_carry__0_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_3
- (.I0(filter_cnt[6]),
- .O(minusOp_carry__0_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_4
- (.I0(filter_cnt[5]),
- .O(minusOp_carry__0_i_4_n_0));
- CARRY4 minusOp_carry__1
- (.CI(minusOp_carry__0_n_0),
- .CO({minusOp_carry__1_n_0,minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI(filter_cnt[12:9]),
- .O({minusOp_carry__1_n_4,minusOp_carry__1_n_5,minusOp_carry__1_n_6,minusOp_carry__1_n_7}),
- .S({minusOp_carry__1_i_1_n_0,minusOp_carry__1_i_2_n_0,minusOp_carry__1_i_3_n_0,minusOp_carry__1_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_1
- (.I0(filter_cnt[12]),
- .O(minusOp_carry__1_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_2
- (.I0(filter_cnt[11]),
- .O(minusOp_carry__1_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_3
- (.I0(filter_cnt[10]),
- .O(minusOp_carry__1_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_4
- (.I0(filter_cnt[9]),
- .O(minusOp_carry__1_i_4_n_0));
- CARRY4 minusOp_carry__2
- (.CI(minusOp_carry__1_n_0),
- .CO(NLW_minusOp_carry__2_CO_UNCONNECTED[3:0]),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({NLW_minusOp_carry__2_O_UNCONNECTED[3:1],minusOp_carry__2_n_7}),
- .S({1'b0,1'b0,1'b0,minusOp_carry__2_i_1_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__2_i_1
- (.I0(filter_cnt[13]),
- .O(minusOp_carry__2_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_1
- (.I0(filter_cnt[4]),
- .O(minusOp_carry_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_2
- (.I0(filter_cnt[3]),
- .O(minusOp_carry_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_3
- (.I0(filter_cnt[2]),
- .O(minusOp_carry_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_4
- (.I0(filter_cnt[1]),
- .O(minusOp_carry_i_4_n_0));
- LUT6 #(
- .INIT(64'h0000000000100000))
- sda_chk_i_1
- (.I0(c_state[4]),
- .I1(c_state[1]),
- .I2(c_state[3]),
- .I3(c_state[0]),
- .I4(c_state[2]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(sda_chk_i_1_n_0));
- FDCE sda_chk_reg
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(sda_chk_i_1_n_0),
- .Q(sda_chk_reg_n_0));
- LUT4 #(
- .INIT(16'h0F04))
- slave_wait_i_1
- (.I0(dscl_oen),
- .I1(scl_padoen_o),
- .I2(sSCL),
- .I3(slave_wait),
- .O(slave_wait0));
- FDCE slave_wait_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(slave_wait0),
- .Q(slave_wait));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT4 #(
- .INIT(16'hE400))
- \sr[0]_i_1
- (.I0(\statemachine.ld_reg_0 ),
- .I1(core_rxd),
- .I2(\txr_reg[6] [0]),
- .I3(s00_axi_aresetn),
- .O(\sr_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'hAA08))
- \st_irq_block.al_i_1
- (.I0(s00_axi_aresetn),
- .I1(\st_irq_block.al_reg ),
- .I2(\cr_reg[7] [3]),
- .I3(i2c_al),
- .O(al));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT5 #(
- .INIT(32'h55540000))
- \st_irq_block.irq_flag_i_1
- (.I0(\cr_reg[0] ),
- .I1(i2c_al),
- .I2(cmd_ack),
- .I3(irq_flag),
- .I4(s00_axi_aresetn),
- .O(irq_flag1_out));
- LUT1 #(
- .INIT(2'h1))
- \st_irq_block.wb_inta_o_i_2
- (.I0(s00_axi_aresetn),
- .O(iscl_oen_reg_0));
- LUT5 #(
- .INIT(32'h08FF0800))
- \statemachine.ack_out_i_1
- (.I0(core_rxd),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .I3(\statemachine.ack_out_i_2_n_0 ),
- .I4(ack_out),
- .O(\statemachine.ack_out_reg ));
- LUT6 #(
- .INIT(64'hDDDDDDDDDDFDDDDD))
- \statemachine.ack_out_i_2
- (.I0(s00_axi_aresetn),
- .I1(i2c_al),
- .I2(out[2]),
- .I3(out[0]),
- .I4(core_ack),
- .I5(out[1]),
- .O(\statemachine.ack_out_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000100000))
- \statemachine.core_cmd[0]_i_1
- (.I0(out[2]),
- .I1(out[0]),
- .I2(\cr_reg[7] [3]),
- .I3(out[1]),
- .I4(s00_axi_aresetn),
- .I5(i2c_al),
- .O(\statemachine.core_cmd_reg[3] [0]));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \statemachine.core_cmd[1]_i_1
- (.I0(\FSM_sequential_statemachine.c_state_reg[1]_0 ),
- .I1(out[2]),
- .I2(out[1]),
- .I3(\cr_reg[7] [2]),
- .I4(out[0]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\statemachine.core_cmd_reg[3] [1]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT3 #(
- .INIT(8'h08))
- \statemachine.core_cmd[2]_i_1
- (.I0(core_cmd),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .O(\statemachine.core_cmd_reg[3] [2]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0040))
- \statemachine.core_cmd[3]_i_1
- (.I0(out[2]),
- .I1(\FSM_sequential_statemachine.c_state_reg[1] ),
- .I2(s00_axi_aresetn),
- .I3(i2c_al),
- .O(\statemachine.core_cmd_reg[3] [3]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT3 #(
- .INIT(8'h08))
- \statemachine.core_txd_i_1
- (.I0(core_txd),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .O(\statemachine.core_txd_reg ));
- LUT6 #(
- .INIT(64'h5455FFFD10002220))
- \statemachine.core_txd_i_2
- (.I0(out[2]),
- .I1(out[0]),
- .I2(ack_in),
- .I3(core_ack),
- .I4(out[1]),
- .I5(\sr_reg[7] ),
- .O(core_txd));
- LUT6 #(
- .INIT(64'h000000000000A020))
- \statemachine.host_ack_i_1
- (.I0(out[2]),
- .I1(\cr_reg[7] [2]),
- .I2(core_ack),
- .I3(out[0]),
- .I4(out[1]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\statemachine.host_ack_reg ));
- LUT5 #(
- .INIT(32'h00000400))
- \statemachine.ld_i_1
- (.I0(out[2]),
- .I1(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
- .I2(out[1]),
- .I3(s00_axi_aresetn),
- .I4(i2c_al),
- .O(\statemachine.ld_reg ));
- LUT6 #(
- .INIT(64'h0000000004440000))
- \statemachine.shift_i_1
- (.I0(out[2]),
- .I1(core_ack),
- .I2(out[0]),
- .I3(cnt_done),
- .I4(out[1]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\statemachine.shift_reg ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[6]_i_3
- (.I0(\cr_reg[7] [2]),
- .I1(wb_adr_o[1]),
- .I2(\txr_reg[6] [1]),
- .I3(wb_adr_o[0]),
- .I4(i2c_busy),
- .O(\wb_dat_o[6]_i_3_n_0 ));
- MUXF7 \wb_dat_o_reg[6]_i_1
- (.I0(\sr_reg[6] ),
- .I1(\wb_dat_o[6]_i_3_n_0 ),
- .O(D),
- .S(wb_adr_o[2]));
-endmodule
-
-(* ORIG_REF_NAME = "i2c_master_byte_ctrl" *)
-module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
- (iscl_oen_reg,
- irq_flag1_out,
- rxack_0,
- al,
- D,
- E,
- i2c_sda_io,
- i2c_scl_io,
- s00_axi_aclk,
- s00_axi_aresetn,
- \cr_reg[0] ,
- irq_flag,
- Q,
- \ctr_reg[7] ,
- \st_irq_block.al_reg ,
- \cr_reg[7] ,
- wb_adr_o,
- \cr_reg[0]_0 ,
- \cr_reg[1] ,
- \cr_reg[2] ,
- \txr_reg[7] ,
- ack_in,
- \cr_reg[5] ,
- \cr_reg[7]_0 ,
- iack_o_reg,
- wb_we_o,
- iack_o_reg_0);
- output iscl_oen_reg;
- output irq_flag1_out;
- output rxack_0;
- output al;
- output [7:0]D;
- output [0:0]E;
- inout i2c_sda_io;
- inout i2c_scl_io;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input \cr_reg[0] ;
- input irq_flag;
- input [15:0]Q;
- input [7:0]\ctr_reg[7] ;
- input \st_irq_block.al_reg ;
- input [3:0]\cr_reg[7] ;
- input [2:0]wb_adr_o;
- input \cr_reg[0]_0 ;
- input \cr_reg[1] ;
- input \cr_reg[2] ;
- input [7:0]\txr_reg[7] ;
- input ack_in;
- input \cr_reg[5] ;
- input \cr_reg[7]_0 ;
- input iack_o_reg;
- input wb_we_o;
- input iack_o_reg_0;
-
- wire [7:0]D;
- wire [0:0]E;
- wire \FSM_sequential_statemachine.c_state[0]_i_2_n_0 ;
- wire \FSM_sequential_statemachine.c_state[1]_i_3_n_0 ;
- wire \FSM_sequential_statemachine.c_state[2]_i_4_n_0 ;
- wire [15:0]Q;
- wire ack_in;
- wire ack_out;
- wire al;
- wire bit_ctrl_n_10;
- wire bit_ctrl_n_11;
- wire bit_ctrl_n_12;
- wire bit_ctrl_n_13;
- wire bit_ctrl_n_15;
- wire bit_ctrl_n_16;
- wire bit_ctrl_n_17;
- wire bit_ctrl_n_18;
- wire bit_ctrl_n_5;
- wire bit_ctrl_n_6;
- wire bit_ctrl_n_7;
- wire bit_ctrl_n_8;
- wire bit_ctrl_n_9;
- wire c_state;
- (* RTL_KEEP = "yes" *) wire [2:0]c_state__0;
- wire [3:0]cmd;
- wire cmd_ack;
- wire cnt_done;
- wire [2:2]core_cmd;
- wire \cr_reg[0] ;
- wire \cr_reg[0]_0 ;
- wire \cr_reg[1] ;
- wire \cr_reg[2] ;
- wire \cr_reg[5] ;
- wire [3:0]\cr_reg[7] ;
- wire \cr_reg[7]_0 ;
- wire [7:0]\ctr_reg[7] ;
- wire dcnt;
- wire \dcnt[0]_i_1_n_0 ;
- wire \dcnt[1]_i_1_n_0 ;
- wire \dcnt[2]_i_1_n_0 ;
- wire \dcnt_reg_n_0_[0] ;
- wire \dcnt_reg_n_0_[1] ;
- wire \dcnt_reg_n_0_[2] ;
- wire [7:7]dout;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire iack_o_reg;
- wire iack_o_reg_0;
- wire irq_flag;
- wire irq_flag1_out;
- wire iscl_oen_reg;
- wire rxack_0;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire \sr[1]_i_1_n_0 ;
- wire \sr[2]_i_1_n_0 ;
- wire \sr[3]_i_1_n_0 ;
- wire \sr[4]_i_1_n_0 ;
- wire \sr[5]_i_1_n_0 ;
- wire \sr[6]_i_1_n_0 ;
- wire \sr[7]_i_2_n_0 ;
- wire \sr_reg_n_0_[0] ;
- wire \sr_reg_n_0_[1] ;
- wire \sr_reg_n_0_[2] ;
- wire \sr_reg_n_0_[3] ;
- wire \sr_reg_n_0_[4] ;
- wire \sr_reg_n_0_[5] ;
- wire \sr_reg_n_0_[6] ;
- wire \st_irq_block.al_reg ;
- wire \statemachine.core_cmd[1]_i_2_n_0 ;
- wire \statemachine.core_cmd[3]_i_2_n_0 ;
- wire \statemachine.core_txd_reg_n_0 ;
- wire \statemachine.ld_reg_n_0 ;
- wire \statemachine.shift_reg_n_0 ;
- wire [7:0]\txr_reg[7] ;
- wire [2:0]wb_adr_o;
- wire \wb_dat_o[0]_i_2_n_0 ;
- wire \wb_dat_o[1]_i_2_n_0 ;
- wire \wb_dat_o[2]_i_2_n_0 ;
- wire \wb_dat_o[3]_i_2_n_0 ;
- wire \wb_dat_o[4]_i_2_n_0 ;
- wire \wb_dat_o[5]_i_2_n_0 ;
- wire \wb_dat_o[6]_i_2_n_0 ;
- wire \wb_dat_o[7]_i_2_n_0 ;
- wire wb_we_o;
-
- LUT5 #(
- .INIT(32'h43407373))
- \FSM_sequential_statemachine.c_state[0]_i_2
- (.I0(cnt_done),
- .I1(c_state__0[1]),
- .I2(c_state__0[0]),
- .I3(\cr_reg[7] [3]),
- .I4(\cr_reg[7] [1]),
- .O(\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h01))
- \FSM_sequential_statemachine.c_state[1]_i_2
- (.I0(\dcnt_reg_n_0_[1] ),
- .I1(\dcnt_reg_n_0_[0] ),
- .I2(\dcnt_reg_n_0_[2] ),
- .O(cnt_done));
- LUT4 #(
- .INIT(16'hFF54))
- \FSM_sequential_statemachine.c_state[1]_i_3
- (.I0(\cr_reg[7] [3]),
- .I1(\cr_reg[7] [1]),
- .I2(\cr_reg[7] [0]),
- .I3(c_state__0[0]),
- .O(\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888888888888888B))
- \FSM_sequential_statemachine.c_state[2]_i_4
- (.I0(cnt_done),
- .I1(c_state__0[1]),
- .I2(\cr_reg[7] [3]),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [1]),
- .I5(c_state__0[0]),
- .O(\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_statemachine.c_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_18),
- .Q(c_state__0[0]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_statemachine.c_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_17),
- .Q(c_state__0[1]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_statemachine.c_state_reg[2]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_16),
- .Q(c_state__0[2]));
- system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl bit_ctrl
- (.D(D[6]),
- .E(c_state),
- .\FSM_sequential_statemachine.c_state_reg[1] (\statemachine.core_cmd[3]_i_2_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[1]_0 (\statemachine.core_cmd[1]_i_2_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[1]_1 (\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[1]_2 (\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_16,bit_ctrl_n_17,bit_ctrl_n_18}),
- .Q(Q),
- .ack_in(ack_in),
- .ack_out(ack_out),
- .al(al),
- .cmd_ack(cmd_ack),
- .cnt_done(cnt_done),
- .core_cmd(core_cmd),
- .\cr_reg[0] (\cr_reg[0] ),
- .\cr_reg[4] (E),
- .\cr_reg[7] (\cr_reg[7] ),
- .\cr_reg[7]_0 (\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ),
- .\ctr_reg[7] (\ctr_reg[7] [7]),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .iack_o_reg(iack_o_reg),
- .iack_o_reg_0(iack_o_reg_0),
- .irq_flag(irq_flag),
- .irq_flag1_out(irq_flag1_out),
- .iscl_oen_reg_0(iscl_oen_reg),
- .out(c_state__0),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .\sr_reg[0] (bit_ctrl_n_15),
- .\sr_reg[6] (\wb_dat_o[6]_i_2_n_0 ),
- .\sr_reg[7] (dout),
- .\st_irq_block.al_reg (\st_irq_block.al_reg ),
- .\statemachine.ack_out_reg (bit_ctrl_n_13),
- .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_5,bit_ctrl_n_6,bit_ctrl_n_7,bit_ctrl_n_8}),
- .\statemachine.core_cmd_reg[3]_0 (cmd),
- .\statemachine.core_txd_reg (bit_ctrl_n_10),
- .\statemachine.core_txd_reg_0 (\statemachine.core_txd_reg_n_0 ),
- .\statemachine.host_ack_reg (bit_ctrl_n_12),
- .\statemachine.ld_reg (bit_ctrl_n_9),
- .\statemachine.ld_reg_0 (\statemachine.ld_reg_n_0 ),
- .\statemachine.shift_reg (bit_ctrl_n_11),
- .\txr_reg[6] ({\txr_reg[7] [6],\txr_reg[7] [0]}),
- .wb_adr_o(wb_adr_o),
- .wb_we_o(wb_we_o));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT3 #(
- .INIT(8'h8A))
- \dcnt[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(\statemachine.ld_reg_n_0 ),
- .I2(\dcnt_reg_n_0_[0] ),
- .O(\dcnt[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT4 #(
- .INIT(16'hA88A))
- \dcnt[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(\statemachine.ld_reg_n_0 ),
- .I2(\dcnt_reg_n_0_[0] ),
- .I3(\dcnt_reg_n_0_[1] ),
- .O(\dcnt[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT5 #(
- .INIT(32'hAAA8888A))
- \dcnt[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(\statemachine.ld_reg_n_0 ),
- .I2(\dcnt_reg_n_0_[1] ),
- .I3(\dcnt_reg_n_0_[0] ),
- .I4(\dcnt_reg_n_0_[2] ),
- .O(\dcnt[2]_i_1_n_0 ));
- FDCE \dcnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\dcnt[0]_i_1_n_0 ),
- .Q(\dcnt_reg_n_0_[0] ));
- FDCE \dcnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\dcnt[1]_i_1_n_0 ),
- .Q(\dcnt_reg_n_0_[1] ));
- FDCE \dcnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\dcnt[2]_i_1_n_0 ),
- .Q(\dcnt_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT4 #(
- .INIT(16'hE400))
- \sr[1]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[0] ),
- .I2(\txr_reg[7] [1]),
- .I3(s00_axi_aresetn),
- .O(\sr[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT4 #(
- .INIT(16'hE400))
- \sr[2]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[1] ),
- .I2(\txr_reg[7] [2]),
- .I3(s00_axi_aresetn),
- .O(\sr[2]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[3]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[2] ),
- .I2(\txr_reg[7] [3]),
- .I3(s00_axi_aresetn),
- .O(\sr[3]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[4]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[3] ),
- .I2(\txr_reg[7] [4]),
- .I3(s00_axi_aresetn),
- .O(\sr[4]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[5]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[4] ),
- .I2(\txr_reg[7] [5]),
- .I3(s00_axi_aresetn),
- .O(\sr[5]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[6]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[5] ),
- .I2(\txr_reg[7] [6]),
- .I3(s00_axi_aresetn),
- .O(\sr[6]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'hFB))
- \sr[7]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(s00_axi_aresetn),
- .I2(\statemachine.shift_reg_n_0 ),
- .O(dcnt));
- LUT4 #(
- .INIT(16'hE400))
- \sr[7]_i_2
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[6] ),
- .I2(\txr_reg[7] [7]),
- .I3(s00_axi_aresetn),
- .O(\sr[7]_i_2_n_0 ));
- FDCE \sr_reg[0]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_15),
- .Q(\sr_reg_n_0_[0] ));
- FDCE \sr_reg[1]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[1]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[1] ));
- FDCE \sr_reg[2]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[2]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[2] ));
- FDCE \sr_reg[3]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[3]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[3] ));
- FDCE \sr_reg[4]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[4]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[4] ));
- FDCE \sr_reg[5]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[5]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[5] ));
- FDCE \sr_reg[6]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[6]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[6] ));
- FDCE \sr_reg[7]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[7]_i_2_n_0 ),
- .Q(dout));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT2 #(
- .INIT(4'h8))
- \st_irq_block.rxack_i_1
- (.I0(s00_axi_aresetn),
- .I1(ack_out),
- .O(rxack_0));
- FDCE \statemachine.ack_out_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_13),
- .Q(ack_out));
- LUT5 #(
- .INIT(32'h00000001))
- \statemachine.core_cmd[1]_i_2
- (.I0(c_state__0[1]),
- .I1(c_state__0[0]),
- .I2(\cr_reg[7] [3]),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [1]),
- .O(\statemachine.core_cmd[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h00000000F0C40FC4))
- \statemachine.core_cmd[2]_i_2
- (.I0(\cr_reg[7] [3]),
- .I1(\cr_reg[7] [1]),
- .I2(c_state__0[0]),
- .I3(c_state__0[1]),
- .I4(cnt_done),
- .I5(c_state__0[2]),
- .O(core_cmd));
- LUT6 #(
- .INIT(64'h4848484878787B78))
- \statemachine.core_cmd[3]_i_2
- (.I0(cnt_done),
- .I1(c_state__0[1]),
- .I2(c_state__0[0]),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [3]),
- .I5(\cr_reg[7] [1]),
- .O(\statemachine.core_cmd[3]_i_2_n_0 ));
- FDCE \statemachine.core_cmd_reg[0]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_8),
- .Q(cmd[0]));
- FDCE \statemachine.core_cmd_reg[1]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_7),
- .Q(cmd[1]));
- FDCE \statemachine.core_cmd_reg[2]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_6),
- .Q(cmd[2]));
- FDCE \statemachine.core_cmd_reg[3]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_5),
- .Q(cmd[3]));
- FDCE \statemachine.core_txd_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_10),
- .Q(\statemachine.core_txd_reg_n_0 ));
- FDCE \statemachine.host_ack_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_12),
- .Q(cmd_ack));
- FDCE \statemachine.ld_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_9),
- .Q(\statemachine.ld_reg_n_0 ));
- FDCE \statemachine.shift_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_11),
- .Q(\statemachine.shift_reg_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[0]_i_2
- (.I0(\sr_reg_n_0_[0] ),
- .I1(\ctr_reg[7] [0]),
- .I2(wb_adr_o[1]),
- .I3(Q[8]),
- .I4(wb_adr_o[0]),
- .I5(Q[0]),
- .O(\wb_dat_o[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[1]_i_2
- (.I0(\sr_reg_n_0_[1] ),
- .I1(\ctr_reg[7] [1]),
- .I2(wb_adr_o[1]),
- .I3(Q[9]),
- .I4(wb_adr_o[0]),
- .I5(Q[1]),
- .O(\wb_dat_o[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h3808FFFF38080000))
- \wb_dat_o[2]_i_1
- (.I0(\cr_reg[2] ),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[0]),
- .I3(\txr_reg[7] [2]),
- .I4(wb_adr_o[2]),
- .I5(\wb_dat_o[2]_i_2_n_0 ),
- .O(D[2]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[2]_i_2
- (.I0(\sr_reg_n_0_[2] ),
- .I1(\ctr_reg[7] [2]),
- .I2(wb_adr_o[1]),
- .I3(Q[10]),
- .I4(wb_adr_o[0]),
- .I5(Q[2]),
- .O(\wb_dat_o[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h3808FFFF38080000))
- \wb_dat_o[3]_i_1
- (.I0(ack_in),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[0]),
- .I3(\txr_reg[7] [3]),
- .I4(wb_adr_o[2]),
- .I5(\wb_dat_o[3]_i_2_n_0 ),
- .O(D[3]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[3]_i_2
- (.I0(\sr_reg_n_0_[3] ),
- .I1(\ctr_reg[7] [3]),
- .I2(wb_adr_o[1]),
- .I3(Q[11]),
- .I4(wb_adr_o[0]),
- .I5(Q[3]),
- .O(\wb_dat_o[3]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h3808FFFF38080000))
- \wb_dat_o[4]_i_1
- (.I0(\cr_reg[7] [0]),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[0]),
- .I3(\txr_reg[7] [4]),
- .I4(wb_adr_o[2]),
- .I5(\wb_dat_o[4]_i_2_n_0 ),
- .O(D[4]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[4]_i_2
- (.I0(\sr_reg_n_0_[4] ),
- .I1(\ctr_reg[7] [4]),
- .I2(wb_adr_o[1]),
- .I3(Q[12]),
- .I4(wb_adr_o[0]),
- .I5(Q[4]),
- .O(\wb_dat_o[4]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[5]_i_2
- (.I0(\sr_reg_n_0_[5] ),
- .I1(\ctr_reg[7] [5]),
- .I2(wb_adr_o[1]),
- .I3(Q[13]),
- .I4(wb_adr_o[0]),
- .I5(Q[5]),
- .O(\wb_dat_o[5]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[6]_i_2
- (.I0(\sr_reg_n_0_[6] ),
- .I1(\ctr_reg[7] [6]),
- .I2(wb_adr_o[1]),
- .I3(Q[14]),
- .I4(wb_adr_o[0]),
- .I5(Q[6]),
- .O(\wb_dat_o[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[7]_i_2
- (.I0(dout),
- .I1(\ctr_reg[7] [7]),
- .I2(wb_adr_o[1]),
- .I3(Q[15]),
- .I4(wb_adr_o[0]),
- .I5(Q[7]),
- .O(\wb_dat_o[7]_i_2_n_0 ));
- MUXF7 \wb_dat_o_reg[0]_i_1
- (.I0(\wb_dat_o[0]_i_2_n_0 ),
- .I1(\cr_reg[0]_0 ),
- .O(D[0]),
- .S(wb_adr_o[2]));
- MUXF7 \wb_dat_o_reg[1]_i_1
- (.I0(\wb_dat_o[1]_i_2_n_0 ),
- .I1(\cr_reg[1] ),
- .O(D[1]),
- .S(wb_adr_o[2]));
- MUXF7 \wb_dat_o_reg[5]_i_1
- (.I0(\wb_dat_o[5]_i_2_n_0 ),
- .I1(\cr_reg[5] ),
- .O(D[5]),
- .S(wb_adr_o[2]));
- MUXF7 \wb_dat_o_reg[7]_i_1
- (.I0(\wb_dat_o[7]_i_2_n_0 ),
- .I1(\cr_reg[7]_0 ),
- .O(D[7]),
- .S(wb_adr_o[2]));
-endmodule
-
-(* ORIG_REF_NAME = "i2c_master_top" *)
-module system_design_axi_wb_i2c_master_0_1_i2c_master_top
- (wb_ack_i,
- wb_rst_o,
- axi_int_o,
- Q,
- s_stb_r_reg,
- \s_rdata_reg[0] ,
- \s_rdata_reg[7] ,
- i2c_sda_io,
- i2c_scl_io,
- s_stb_r_reg_0,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_wdata,
- wb_adr_o,
- s00_axi_awvalid,
- s00_axi_arvalid,
- wb_cyc_o,
- wb_we_o,
- iack_o_reg_0,
- E,
- s_we_r_reg,
- s_we_r_reg_0,
- D,
- \s_addr_reg[4] );
- output wb_ack_i;
- output wb_rst_o;
- output axi_int_o;
- output [0:0]Q;
- output s_stb_r_reg;
- output [0:0]\s_rdata_reg[0] ;
- output [7:0]\s_rdata_reg[7] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
- input s_stb_r_reg_0;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [7:0]s00_axi_wdata;
- input [2:0]wb_adr_o;
- input s00_axi_awvalid;
- input s00_axi_arvalid;
- input wb_cyc_o;
- input wb_we_o;
- input iack_o_reg_0;
- input [1:0]E;
- input [0:0]s_we_r_reg;
- input [0:0]s_we_r_reg_0;
- input [3:0]D;
- input \s_addr_reg[4] ;
-
- wire [3:0]D;
- wire [1:0]E;
- wire [0:0]Q;
- wire ack_in;
- wire al;
- wire axi_int_o;
- wire byte_ctrl_n_12;
- wire \cr[0]_i_1_n_0 ;
- wire \cr[1]_i_1_n_0 ;
- wire \cr[2]_i_1_n_0 ;
- wire \cr[3]_i_1_n_0 ;
- wire \cr_reg_n_0_[0] ;
- wire \cr_reg_n_0_[1] ;
- wire \cr_reg_n_0_[2] ;
- wire [7:0]ctr;
- wire \ctr_reg_n_0_[0] ;
- wire \ctr_reg_n_0_[1] ;
- wire \ctr_reg_n_0_[2] ;
- wire \ctr_reg_n_0_[3] ;
- wire \ctr_reg_n_0_[4] ;
- wire \ctr_reg_n_0_[5] ;
- wire [13:0]data0;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire iack_o_reg_0;
- wire ien;
- wire irq_flag;
- wire irq_flag1_out;
- wire \prer[10]_i_1_n_0 ;
- wire \prer[11]_i_1_n_0 ;
- wire \prer[12]_i_1_n_0 ;
- wire \prer[13]_i_1_n_0 ;
- wire \prer[14]_i_1_n_0 ;
- wire \prer[15]_i_2_n_0 ;
- wire \prer[8]_i_1_n_0 ;
- wire \prer[9]_i_1_n_0 ;
- wire \prer_reg_n_0_[0] ;
- wire \prer_reg_n_0_[1] ;
- wire read;
- wire rxack;
- wire rxack_0;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s00_axi_arvalid;
- wire s00_axi_awvalid;
- wire [7:0]s00_axi_wdata;
- wire \s_addr_reg[4] ;
- wire [0:0]\s_rdata_reg[0] ;
- wire [7:0]\s_rdata_reg[7] ;
- wire s_stb_r_reg;
- wire s_stb_r_reg_0;
- wire [0:0]s_we_r_reg;
- wire [0:0]s_we_r_reg_0;
- wire \st_irq_block.al_reg_n_0 ;
- wire \st_irq_block.wb_inta_o_i_1_n_0 ;
- wire start;
- wire stop;
- wire tip;
- wire tip_1;
- wire [7:0]txr;
- wire wb_ack_i;
- wire [2:0]wb_adr_o;
- wire wb_cyc_o;
- wire [7:0]wb_dat_o;
- wire \wb_dat_o[0]_i_3_n_0 ;
- wire \wb_dat_o[1]_i_3_n_0 ;
- wire \wb_dat_o[5]_i_3_n_0 ;
- wire \wb_dat_o[7]_i_3_n_0 ;
- wire wb_rst_o;
- wire wb_we_o;
- wire write;
-
- system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl byte_ctrl
- (.D(wb_dat_o),
- .E(byte_ctrl_n_12),
- .Q({data0,\prer_reg_n_0_[1] ,\prer_reg_n_0_[0] }),
- .ack_in(ack_in),
- .al(al),
- .\cr_reg[0] (\cr_reg_n_0_[0] ),
- .\cr_reg[0]_0 (\wb_dat_o[0]_i_3_n_0 ),
- .\cr_reg[1] (\wb_dat_o[1]_i_3_n_0 ),
- .\cr_reg[2] (\cr_reg_n_0_[2] ),
- .\cr_reg[5] (\wb_dat_o[5]_i_3_n_0 ),
- .\cr_reg[7] ({start,stop,read,write}),
- .\cr_reg[7]_0 (\wb_dat_o[7]_i_3_n_0 ),
- .\ctr_reg[7] ({Q,ien,\ctr_reg_n_0_[5] ,\ctr_reg_n_0_[4] ,\ctr_reg_n_0_[3] ,\ctr_reg_n_0_[2] ,\ctr_reg_n_0_[1] ,\ctr_reg_n_0_[0] }),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .iack_o_reg(wb_ack_i),
- .iack_o_reg_0(iack_o_reg_0),
- .irq_flag(irq_flag),
- .irq_flag1_out(irq_flag1_out),
- .iscl_oen_reg(wb_rst_o),
- .rxack_0(rxack_0),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .\st_irq_block.al_reg (\st_irq_block.al_reg_n_0 ),
- .\txr_reg[7] (txr),
- .wb_adr_o(wb_adr_o),
- .wb_we_o(wb_we_o));
- LUT6 #(
- .INIT(64'h8000FFFF80000000))
- \cr[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[0]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .I4(\s_addr_reg[4] ),
- .I5(\cr_reg_n_0_[0] ),
- .O(\cr[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8000FFFF80000000))
- \cr[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[1]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .I4(\s_addr_reg[4] ),
- .I5(\cr_reg_n_0_[1] ),
- .O(\cr[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8000FFFF80000000))
- \cr[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[2]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .I4(\s_addr_reg[4] ),
- .I5(\cr_reg_n_0_[2] ),
- .O(\cr[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT4 #(
- .INIT(16'hC808))
- \cr[3]_i_1
- (.I0(s00_axi_wdata[3]),
- .I1(s00_axi_aresetn),
- .I2(iack_o_reg_0),
- .I3(ack_in),
- .O(\cr[3]_i_1_n_0 ));
- FDCE \cr_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[0]_i_1_n_0 ),
- .Q(\cr_reg_n_0_[0] ));
- FDCE \cr_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[1]_i_1_n_0 ),
- .Q(\cr_reg_n_0_[1] ));
- FDCE \cr_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[2]_i_1_n_0 ),
- .Q(\cr_reg_n_0_[2] ));
- FDCE \cr_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[3]_i_1_n_0 ),
- .Q(ack_in));
- FDCE \cr_reg[4]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[0]),
- .Q(write));
- FDCE \cr_reg[5]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[1]),
- .Q(read));
- FDCE \cr_reg[6]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[2]),
- .Q(stop));
- FDCE \cr_reg[7]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[3]),
- .Q(start));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[0]),
- .O(ctr[0]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[1]),
- .O(ctr[1]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[2]),
- .O(ctr[2]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[3]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[3]),
- .O(ctr[3]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[4]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[4]),
- .O(ctr[4]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[5]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[5]),
- .O(ctr[5]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[6]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[6]),
- .O(ctr[6]));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[7]_i_2
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[7]),
- .O(ctr[7]));
- FDCE \ctr_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[0]),
- .Q(\ctr_reg_n_0_[0] ));
- FDCE \ctr_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[1]),
- .Q(\ctr_reg_n_0_[1] ));
- FDCE \ctr_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[2]),
- .Q(\ctr_reg_n_0_[2] ));
- FDCE \ctr_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[3]),
- .Q(\ctr_reg_n_0_[3] ));
- FDCE \ctr_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[4]),
- .Q(\ctr_reg_n_0_[4] ));
- FDCE \ctr_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[5]),
- .Q(\ctr_reg_n_0_[5] ));
- FDCE \ctr_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[6]),
- .Q(ien));
- FDCE \ctr_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[7]),
- .Q(Q));
- FDRE iack_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_stb_r_reg_0),
- .Q(wb_ack_i),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[10]_i_1
- (.I0(s00_axi_wdata[2]),
- .I1(s00_axi_aresetn),
- .O(\prer[10]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hB))
- \prer[11]_i_1
- (.I0(s00_axi_wdata[3]),
- .I1(s00_axi_aresetn),
- .O(\prer[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[12]_i_1
- (.I0(s00_axi_wdata[4]),
- .I1(s00_axi_aresetn),
- .O(\prer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[13]_i_1
- (.I0(s00_axi_wdata[5]),
- .I1(s00_axi_aresetn),
- .O(\prer[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[14]_i_1
- (.I0(s00_axi_wdata[6]),
- .I1(s00_axi_aresetn),
- .O(\prer[14]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[15]_i_2
- (.I0(s00_axi_wdata[7]),
- .I1(s00_axi_aresetn),
- .O(\prer[15]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[8]_i_1
- (.I0(s00_axi_wdata[0]),
- .I1(s00_axi_aresetn),
- .O(\prer[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[9]_i_1
- (.I0(s00_axi_wdata[1]),
- .I1(s00_axi_aresetn),
- .O(\prer[9]_i_1_n_0 ));
- FDPE \prer_reg[0]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[8]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(\prer_reg_n_0_[0] ));
- FDPE \prer_reg[10]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[10]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[8]));
- FDPE \prer_reg[11]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[11]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[9]));
- FDPE \prer_reg[12]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[12]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[10]));
- FDPE \prer_reg[13]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[13]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[11]));
- FDPE \prer_reg[14]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[14]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[12]));
- FDPE \prer_reg[15]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[15]_i_2_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[13]));
- FDPE \prer_reg[1]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[9]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(\prer_reg_n_0_[1] ));
- FDPE \prer_reg[2]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[10]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[0]));
- FDPE \prer_reg[3]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[11]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[1]));
- FDPE \prer_reg[4]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[12]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[2]));
- FDPE \prer_reg[5]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[13]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[3]));
- FDPE \prer_reg[6]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[14]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[4]));
- FDPE \prer_reg[7]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[15]_i_2_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[5]));
- FDPE \prer_reg[8]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[8]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[6]));
- FDPE \prer_reg[9]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[9]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[7]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT2 #(
- .INIT(4'h2))
- \s_rdata[7]_i_1
- (.I0(wb_ack_i),
- .I1(wb_we_o),
- .O(\s_rdata_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT4 #(
- .INIT(16'hEFEE))
- s_stb_r_i_1
- (.I0(s00_axi_awvalid),
- .I1(s00_axi_arvalid),
- .I2(wb_ack_i),
- .I3(wb_cyc_o),
- .O(s_stb_r_reg));
- FDCE \st_irq_block.al_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(al),
- .Q(\st_irq_block.al_reg_n_0 ));
- FDCE \st_irq_block.irq_flag_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(irq_flag1_out),
- .Q(irq_flag));
- FDCE \st_irq_block.rxack_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(rxack_0),
- .Q(rxack));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT3 #(
- .INIT(8'hA8))
- \st_irq_block.tip_i_1
- (.I0(s00_axi_aresetn),
- .I1(write),
- .I2(read),
- .O(tip_1));
- FDCE \st_irq_block.tip_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(tip_1),
- .Q(tip));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT3 #(
- .INIT(8'h80))
- \st_irq_block.wb_inta_o_i_1
- (.I0(irq_flag),
- .I1(s00_axi_aresetn),
- .I2(ien),
- .O(\st_irq_block.wb_inta_o_i_1_n_0 ));
- FDCE \st_irq_block.wb_inta_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\st_irq_block.wb_inta_o_i_1_n_0 ),
- .Q(axi_int_o));
- FDCE \txr_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[0]),
- .Q(txr[0]));
- FDCE \txr_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[1]),
- .Q(txr[1]));
- FDCE \txr_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[2]),
- .Q(txr[2]));
- FDCE \txr_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[3]),
- .Q(txr[3]));
- FDCE \txr_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[4]),
- .Q(txr[4]));
- FDCE \txr_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[5]),
- .Q(txr[5]));
- FDCE \txr_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[6]),
- .Q(txr[6]));
- FDCE \txr_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[7]),
- .Q(txr[7]));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[0]_i_3
- (.I0(\cr_reg_n_0_[0] ),
- .I1(wb_adr_o[1]),
- .I2(txr[0]),
- .I3(wb_adr_o[0]),
- .I4(irq_flag),
- .O(\wb_dat_o[0]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[1]_i_3
- (.I0(\cr_reg_n_0_[1] ),
- .I1(wb_adr_o[1]),
- .I2(txr[1]),
- .I3(wb_adr_o[0]),
- .I4(tip),
- .O(\wb_dat_o[1]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[5]_i_3
- (.I0(read),
- .I1(wb_adr_o[1]),
- .I2(txr[5]),
- .I3(wb_adr_o[0]),
- .I4(\st_irq_block.al_reg_n_0 ),
- .O(\wb_dat_o[5]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[7]_i_3
- (.I0(start),
- .I1(wb_adr_o[1]),
- .I2(txr[7]),
- .I3(wb_adr_o[0]),
- .I4(rxack),
- .O(\wb_dat_o[7]_i_3_n_0 ));
- FDRE \wb_dat_o_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[0]),
- .Q(\s_rdata_reg[7] [0]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[1]),
- .Q(\s_rdata_reg[7] [1]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[2]),
- .Q(\s_rdata_reg[7] [2]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[3]),
- .Q(\s_rdata_reg[7] [3]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[4]),
- .Q(\s_rdata_reg[7] [4]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[5]),
- .Q(\s_rdata_reg[7] [5]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[6]),
- .Q(\s_rdata_reg[7] [6]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[7]),
- .Q(\s_rdata_reg[7] [7]),
- .R(1'b0));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (weak1, weak0) GSR = GSR_int;
- assign (weak1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
deleted file mode 100644
index 89015508238a9ae65448042936e326d3b85917ea..0000000000000000000000000000000000000000
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
+++ /dev/null
@@ -1,4880 +0,0 @@
--- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Tue Jun 20 20:06:19 2017
--- Host : lapte24154 running 64-bit openSUSE Leap 42.2
--- Command : write_vhdl -force -mode funcsim
--- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
--- Design : system_design_axi_wb_i2c_master_0_1
--- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--- synthesized. This netlist cannot be used for SDF annotated simulation.
--- Device : xc7z030ffg676-2
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge is
- port (
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- wb_we_o : out STD_LOGIC;
- wb_cyc_o : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_bvalid : out STD_LOGIC;
- \cr_reg[2]\ : out STD_LOGIC;
- wb_adr_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 3 downto 0 );
- \cr_reg[4]\ : out STD_LOGIC;
- \prer_reg[8]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
- \ctr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_rvalid : out STD_LOGIC;
- iack_o_reg : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
- wb_rst_o : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC;
- wb_ack_i : in STD_LOGIC;
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_rready : in STD_LOGIC;
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
- iack_o_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \wb_dat_o_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge : entity is "axis_wbm_bridge";
-end system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge is
- signal \cr[2]_i_3_n_0\ : STD_LOGIC;
- signal \^s00_axi_arready\ : STD_LOGIC;
- signal \^s00_axi_awready\ : STD_LOGIC;
- signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s00_axi_wready\ : STD_LOGIC;
- signal \s_addr[2]_i_1_n_0\ : STD_LOGIC;
- signal \s_addr[3]_i_1_n_0\ : STD_LOGIC;
- signal \s_addr[4]_i_1_n_0\ : STD_LOGIC;
- signal s_arready_i_1_n_0 : STD_LOGIC;
- signal s_awready_i_1_n_0 : STD_LOGIC;
- signal \s_bresp[1]_i_1_n_0\ : STD_LOGIC;
- signal s_bvalid : STD_LOGIC;
- signal s_bvalid_i_1_n_0 : STD_LOGIC;
- signal s_rvalid : STD_LOGIC;
- signal s_rvalid_i_1_n_0 : STD_LOGIC;
- signal s_we_r_i_1_n_0 : STD_LOGIC;
- signal s_wready_i_1_n_0 : STD_LOGIC;
- signal \^wb_adr_o\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^wb_cyc_o\ : STD_LOGIC;
- signal \^wb_we_o\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \cr[2]_i_3\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \ctr[7]_i_1\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of iack_o_i_1 : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of \prer[15]_i_1\ : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of s00_axi_bvalid_INST_0 : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of s00_axi_rvalid_INST_0 : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of s_awready_i_1 : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \s_bresp[1]_i_1\ : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of s_rvalid_i_1 : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of s_we_r_i_1 : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of s_wready_i_1 : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \txr[7]_i_1\ : label is "soft_lutpair0";
-begin
- s00_axi_arready <= \^s00_axi_arready\;
- s00_axi_awready <= \^s00_axi_awready\;
- s00_axi_bresp(0) <= \^s00_axi_bresp\(0);
- s00_axi_wready <= \^s00_axi_wready\;
- wb_adr_o(2 downto 0) <= \^wb_adr_o\(2 downto 0);
- wb_cyc_o <= \^wb_cyc_o\;
- wb_we_o <= \^wb_we_o\;
-\cr[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFF0008FFFFFFFF"
- )
- port map (
- I0 => \^wb_adr_o\(2),
- I1 => Q(0),
- I2 => \^wb_adr_o\(1),
- I3 => \^wb_adr_o\(0),
- I4 => \cr[2]_i_3_n_0\,
- I5 => s00_axi_aresetn,
- O => \cr_reg[2]\
- );
-\cr[2]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- O => \cr[2]_i_3_n_0\
- );
-\cr[4]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(0),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(0)
- );
-\cr[5]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(1),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(1)
- );
-\cr[6]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(2),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(2)
- );
-\cr[7]_i_2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(3),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(3)
- );
-\cr[7]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFF7FFF"
- )
- port map (
- I0 => wb_ack_i,
- I1 => \^wb_we_o\,
- I2 => \^wb_adr_o\(2),
- I3 => Q(0),
- I4 => \^wb_adr_o\(1),
- I5 => \^wb_adr_o\(0),
- O => \cr_reg[4]\
- );
-\ctr[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0080FFFF"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- I2 => \^wb_adr_o\(1),
- I3 => \^wb_adr_o\(0),
- I4 => s00_axi_aresetn,
- O => \ctr_reg[0]\(0)
- );
-iack_o_i_1: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \^wb_cyc_o\,
- I1 => wb_ack_i,
- O => iack_o_reg
- );
-\prer[15]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"75555555"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \^wb_adr_o\(1),
- I2 => wb_ack_i,
- I3 => \^wb_we_o\,
- I4 => \^wb_adr_o\(0),
- O => \prer_reg[8]\(1)
- );
-\prer[7]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"5555555557555555"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \^wb_adr_o\(1),
- I2 => \^wb_adr_o\(2),
- I3 => wb_ack_i,
- I4 => \^wb_we_o\,
- I5 => \^wb_adr_o\(0),
- O => \prer_reg[8]\(0)
- );
-s00_axi_bvalid_INST_0: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s_bvalid,
- I1 => \^wb_we_o\,
- O => s00_axi_bvalid
- );
-s00_axi_rvalid_INST_0: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => s_rvalid,
- I1 => \^wb_we_o\,
- O => s00_axi_rvalid
- );
-\s_addr[2]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AACFAAC0"
- )
- port map (
- I0 => s00_axi_araddr(0),
- I1 => s00_axi_awaddr(0),
- I2 => s00_axi_awvalid,
- I3 => s00_axi_arvalid,
- I4 => \^wb_adr_o\(0),
- O => \s_addr[2]_i_1_n_0\
- );
-\s_addr[3]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AACFAAC0"
- )
- port map (
- I0 => s00_axi_araddr(1),
- I1 => s00_axi_awaddr(1),
- I2 => s00_axi_awvalid,
- I3 => s00_axi_arvalid,
- I4 => \^wb_adr_o\(1),
- O => \s_addr[3]_i_1_n_0\
- );
-\s_addr[4]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AACFAAC0"
- )
- port map (
- I0 => s00_axi_araddr(2),
- I1 => s00_axi_awaddr(2),
- I2 => s00_axi_awvalid,
- I3 => s00_axi_arvalid,
- I4 => \^wb_adr_o\(2),
- O => \s_addr[4]_i_1_n_0\
- );
-\s_addr_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_addr[2]_i_1_n_0\,
- Q => \^wb_adr_o\(0),
- R => wb_rst_o
- );
-\s_addr_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_addr[3]_i_1_n_0\,
- Q => \^wb_adr_o\(1),
- R => wb_rst_o
- );
-\s_addr_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_addr[4]_i_1_n_0\,
- Q => \^wb_adr_o\(2),
- R => wb_rst_o
- );
-s_arready_i_1: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => s00_axi_arvalid,
- I1 => \^s00_axi_arready\,
- O => s_arready_i_1_n_0
- );
-s_arready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_arready_i_1_n_0,
- Q => \^s00_axi_arready\,
- R => wb_rst_o
- );
-s_awready_i_1: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s00_axi_wvalid,
- I1 => s00_axi_awvalid,
- I2 => \^s00_axi_awready\,
- O => s_awready_i_1_n_0
- );
-s_awready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_awready_i_1_n_0,
- Q => \^s00_axi_awready\,
- R => wb_rst_o
- );
-\s_bresp[1]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FF7F0000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \^wb_we_o\,
- I2 => wb_ack_i,
- I3 => s_bvalid,
- I4 => \^s00_axi_bresp\(0),
- O => \s_bresp[1]_i_1_n_0\
- );
-\s_bresp_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_bresp[1]_i_1_n_0\,
- Q => \^s00_axi_bresp\(0),
- R => '0'
- );
-s_bvalid_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0F88"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- I2 => s00_axi_bready,
- I3 => s_bvalid,
- O => s_bvalid_i_1_n_0
- );
-s_bvalid_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_bvalid_i_1_n_0,
- Q => s_bvalid,
- R => wb_rst_o
- );
-\s_rdata_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(0),
- Q => s00_axi_rdata(0),
- R => wb_rst_o
- );
-\s_rdata_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(1),
- Q => s00_axi_rdata(1),
- R => wb_rst_o
- );
-\s_rdata_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(2),
- Q => s00_axi_rdata(2),
- R => wb_rst_o
- );
-\s_rdata_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(3),
- Q => s00_axi_rdata(3),
- R => wb_rst_o
- );
-\s_rdata_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(4),
- Q => s00_axi_rdata(4),
- R => wb_rst_o
- );
-\s_rdata_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(5),
- Q => s00_axi_rdata(5),
- R => wb_rst_o
- );
-\s_rdata_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(6),
- Q => s00_axi_rdata(6),
- R => wb_rst_o
- );
-\s_rdata_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(7),
- Q => s00_axi_rdata(7),
- R => wb_rst_o
- );
-s_rvalid_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4F44"
- )
- port map (
- I0 => s00_axi_rready,
- I1 => s_rvalid,
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => s_rvalid_i_1_n_0
- );
-s_rvalid_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_rvalid_i_1_n_0,
- Q => s_rvalid,
- R => wb_rst_o
- );
-s_stb_r_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => iack_o_reg_0,
- Q => \^wb_cyc_o\,
- R => wb_rst_o
- );
-s_we_r_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00E0"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => s00_axi_awvalid,
- I2 => s00_axi_aresetn,
- I3 => s00_axi_arvalid,
- O => s_we_r_i_1_n_0
- );
-s_we_r_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_we_r_i_1_n_0,
- Q => \^wb_we_o\,
- R => '0'
- );
-s_wready_i_1: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s00_axi_wvalid,
- I1 => s00_axi_awvalid,
- I2 => \^s00_axi_wready\,
- O => s_wready_i_1_n_0
- );
-s_wready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_wready_i_1_n_0,
- Q => \^s00_axi_wready\,
- R => wb_rst_o
- );
-\txr[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"8000FFFF"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- I2 => \^wb_adr_o\(0),
- I3 => \^wb_adr_o\(1),
- I4 => s00_axi_aresetn,
- O => E(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl is
- port (
- iscl_oen_reg_0 : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- irq_flag1_out : out STD_LOGIC;
- al : out STD_LOGIC;
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- \statemachine.core_cmd_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
- \statemachine.ld_reg\ : out STD_LOGIC;
- \statemachine.core_txd_reg\ : out STD_LOGIC;
- \statemachine.shift_reg\ : out STD_LOGIC;
- \statemachine.host_ack_reg\ : out STD_LOGIC;
- \statemachine.ack_out_reg\ : out STD_LOGIC;
- \cr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \sr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \FSM_sequential_statemachine.c_state_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \cr_reg[0]\ : in STD_LOGIC;
- cmd_ack : in STD_LOGIC;
- irq_flag : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
- \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \statemachine.core_cmd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \st_irq_block.al_reg\ : in STD_LOGIC;
- \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \sr_reg[6]\ : in STD_LOGIC;
- \txr_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \FSM_sequential_statemachine.c_state_reg[1]\ : in STD_LOGIC;
- core_cmd : in STD_LOGIC_VECTOR ( 0 to 0 );
- \FSM_sequential_statemachine.c_state_reg[1]_0\ : in STD_LOGIC;
- cnt_done : in STD_LOGIC;
- ack_out : in STD_LOGIC;
- iack_o_reg : in STD_LOGIC;
- wb_we_o : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC;
- \statemachine.ld_reg_0\ : in STD_LOGIC;
- \FSM_sequential_statemachine.c_state_reg[1]_1\ : in STD_LOGIC;
- \FSM_sequential_statemachine.c_state_reg[1]_2\ : in STD_LOGIC;
- ack_in : in STD_LOGIC;
- \sr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \cr_reg[7]_0\ : in STD_LOGIC;
- \statemachine.core_txd_reg_0\ : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl : entity is "i2c_master_bit_ctrl";
-end system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl is
- signal \FSM_sequential_c_state[0]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[0]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[1]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[1]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[1]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[2]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[2]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[3]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[3]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[3]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[4]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[4]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[4]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_statemachine.c_state[2]_i_3_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSCL[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSCL[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSDA[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSDA[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSDA_reg_n_0_[1]\ : STD_LOGIC;
- signal \bus_status_ctrl.cmd_stop_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cmd_stop_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cmd_stop_reg_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.dSCL_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.dSDA_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.dout_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL[2]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL_reg_n_0_[2]\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[2]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[2]_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA_reg_n_0_[0]\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA_reg_n_0_[1]\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA_reg_n_0_[2]\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[10]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[11]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[12]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_3_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_4_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[2]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[3]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[4]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[5]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[6]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[7]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[8]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[9]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.ial_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.ial_i_3_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sSCL_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sSDA_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sta_condition_reg_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sto_condition_reg_n_0\ : STD_LOGIC;
- signal c_state : STD_LOGIC_VECTOR ( 4 downto 0 );
- attribute RTL_KEEP : string;
- attribute RTL_KEEP of c_state : signal is "yes";
- signal clk_en : STD_LOGIC;
- signal clk_en_i_2_n_0 : STD_LOGIC;
- signal clk_en_i_3_n_0 : STD_LOGIC;
- signal clk_en_i_4_n_0 : STD_LOGIC;
- signal clk_en_i_5_n_0 : STD_LOGIC;
- signal clk_en_i_6_n_0 : STD_LOGIC;
- signal cmd_ack3_out : STD_LOGIC;
- signal cmd_ack_i_2_n_0 : STD_LOGIC;
- signal cnt1 : STD_LOGIC;
- signal \cnt[0]_i_10_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_1_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_9_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_2_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_2_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_9_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_2_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_9_n_0\ : STD_LOGIC;
- signal cnt_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal \cnt_reg[0]_i_2_n_0\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_1\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_2\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_3\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_4\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_5\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_6\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_7\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_1\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_2\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_3\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_4\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_5\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_6\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
- signal core_ack : STD_LOGIC;
- signal core_rxd : STD_LOGIC;
- signal core_txd : STD_LOGIC;
- signal dSCL : STD_LOGIC;
- signal dSDA : STD_LOGIC;
- signal dscl_oen : STD_LOGIC;
- signal filter_cnt : STD_LOGIC_VECTOR ( 13 downto 0 );
- signal i2c_al : STD_LOGIC;
- signal i2c_busy : STD_LOGIC;
- signal i2c_scl_io_INST_0_i_1_n_0 : STD_LOGIC;
- signal i2c_sda_io_INST_0_i_1_n_0 : STD_LOGIC;
- signal ial : STD_LOGIC;
- signal ibusy : STD_LOGIC;
- signal iscl_oen : STD_LOGIC;
- signal \iscl_oen9_out__0\ : STD_LOGIC;
- signal iscl_oen_i_1_n_0 : STD_LOGIC;
- signal \^iscl_oen_reg_0\ : STD_LOGIC;
- signal isda_oen : STD_LOGIC;
- signal \isda_oen7_out__0\ : STD_LOGIC;
- signal isda_oen_i_1_n_0 : STD_LOGIC;
- signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_n_1\ : STD_LOGIC;
- signal \minusOp_carry__0_n_2\ : STD_LOGIC;
- signal \minusOp_carry__0_n_3\ : STD_LOGIC;
- signal \minusOp_carry__0_n_4\ : STD_LOGIC;
- signal \minusOp_carry__0_n_5\ : STD_LOGIC;
- signal \minusOp_carry__0_n_6\ : STD_LOGIC;
- signal \minusOp_carry__0_n_7\ : STD_LOGIC;
- signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_n_1\ : STD_LOGIC;
- signal \minusOp_carry__1_n_2\ : STD_LOGIC;
- signal \minusOp_carry__1_n_3\ : STD_LOGIC;
- signal \minusOp_carry__1_n_4\ : STD_LOGIC;
- signal \minusOp_carry__1_n_5\ : STD_LOGIC;
- signal \minusOp_carry__1_n_6\ : STD_LOGIC;
- signal \minusOp_carry__1_n_7\ : STD_LOGIC;
- signal \minusOp_carry__2_i_1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__2_n_7\ : STD_LOGIC;
- signal minusOp_carry_i_1_n_0 : STD_LOGIC;
- signal minusOp_carry_i_2_n_0 : STD_LOGIC;
- signal minusOp_carry_i_3_n_0 : STD_LOGIC;
- signal minusOp_carry_i_4_n_0 : STD_LOGIC;
- signal minusOp_carry_n_0 : STD_LOGIC;
- signal minusOp_carry_n_1 : STD_LOGIC;
- signal minusOp_carry_n_2 : STD_LOGIC;
- signal minusOp_carry_n_3 : STD_LOGIC;
- signal minusOp_carry_n_4 : STD_LOGIC;
- signal minusOp_carry_n_5 : STD_LOGIC;
- signal minusOp_carry_n_6 : STD_LOGIC;
- signal minusOp_carry_n_7 : STD_LOGIC;
- signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal sSCL : STD_LOGIC;
- signal sSDA : STD_LOGIC;
- signal scl_padoen_o : STD_LOGIC;
- signal sda_chk_i_1_n_0 : STD_LOGIC;
- signal sda_chk_reg_n_0 : STD_LOGIC;
- signal sda_padoen_o : STD_LOGIC;
- signal slave_wait : STD_LOGIC;
- signal slave_wait0 : STD_LOGIC;
- signal sta_condition : STD_LOGIC;
- signal \statemachine.ack_out_i_2_n_0\ : STD_LOGIC;
- signal sto_condition : STD_LOGIC;
- signal \wb_dat_o[6]_i_3_n_0\ : STD_LOGIC;
- signal \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
- signal \NLW_minusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_minusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \FSM_sequential_c_state[4]_i_3\ : label is "soft_lutpair9";
- attribute KEEP : string;
- attribute KEEP of \FSM_sequential_c_state_reg[0]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[1]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[2]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[3]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[4]\ : label is "yes";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \bus_status_ctrl.dSCL_i_1\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of clk_en_i_2 : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of i2c_scl_io_INST_0_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of i2c_sda_io_INST_0_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of iscl_oen_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of isda_oen_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair16";
- attribute SOFT_HLUTNM of \st_irq_block.irq_flag_i_1\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair16";
-begin
- iscl_oen_reg_0 <= \^iscl_oen_reg_0\;
-\FSM_sequential_c_state[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"1111111111111110"
- )
- port map (
- I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
- I1 => c_state(0),
- I2 => c_state(2),
- I3 => c_state(3),
- I4 => \FSM_sequential_c_state[0]_i_2_n_0\,
- I5 => c_state(4),
- O => \FSM_sequential_c_state[0]_i_1_n_0\
- );
-\FSM_sequential_c_state[0]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AAAAAABA"
- )
- port map (
- I0 => c_state(1),
- I1 => \statemachine.core_cmd_reg[3]_0\(1),
- I2 => \statemachine.core_cmd_reg[3]_0\(0),
- I3 => \statemachine.core_cmd_reg[3]_0\(3),
- I4 => \statemachine.core_cmd_reg[3]_0\(2),
- O => \FSM_sequential_c_state[0]_i_2_n_0\
- );
-\FSM_sequential_c_state[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0400"
- )
- port map (
- I0 => i2c_al,
- I1 => s00_axi_aresetn,
- I2 => c_state(4),
- I3 => \FSM_sequential_c_state[1]_i_2_n_0\,
- O => \FSM_sequential_c_state[1]_i_1_n_0\
- );
-\FSM_sequential_c_state[1]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"EEEFEFFE44444444"
- )
- port map (
- I0 => c_state(0),
- I1 => c_state(1),
- I2 => \statemachine.core_cmd_reg[3]_0\(1),
- I3 => \statemachine.core_cmd_reg[3]_0\(2),
- I4 => \statemachine.core_cmd_reg[3]_0\(3),
- I5 => \FSM_sequential_c_state[1]_i_3_n_0\,
- O => \FSM_sequential_c_state[1]_i_2_n_0\
- );
-\FSM_sequential_c_state[1]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00001101"
- )
- port map (
- I0 => c_state(2),
- I1 => c_state(1),
- I2 => \statemachine.core_cmd_reg[3]_0\(0),
- I3 => c_state(0),
- I4 => c_state(3),
- O => \FSM_sequential_c_state[1]_i_3_n_0\
- );
-\FSM_sequential_c_state[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0002A0A2AAAA0002"
- )
- port map (
- I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
- I1 => c_state(3),
- I2 => c_state(1),
- I3 => \FSM_sequential_c_state[2]_i_2_n_0\,
- I4 => c_state(2),
- I5 => c_state(0),
- O => \FSM_sequential_c_state[2]_i_1_n_0\
- );
-\FSM_sequential_c_state[2]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFEEF"
- )
- port map (
- I0 => c_state(0),
- I1 => \statemachine.core_cmd_reg[3]_0\(3),
- I2 => \statemachine.core_cmd_reg[3]_0\(1),
- I3 => \statemachine.core_cmd_reg[3]_0\(2),
- I4 => \statemachine.core_cmd_reg[3]_0\(0),
- O => \FSM_sequential_c_state[2]_i_2_n_0\
- );
-\FSM_sequential_c_state[3]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0AA8A0A800A800A8"
- )
- port map (
- I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
- I1 => \FSM_sequential_c_state[3]_i_3_n_0\,
- I2 => c_state(3),
- I3 => c_state(0),
- I4 => c_state(2),
- I5 => c_state(1),
- O => \FSM_sequential_c_state[3]_i_1_n_0\
- );
-\FSM_sequential_c_state[3]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"04"
- )
- port map (
- I0 => c_state(4),
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- O => \FSM_sequential_c_state[3]_i_2_n_0\
- );
-\FSM_sequential_c_state[3]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000000006"
- )
- port map (
- I0 => \statemachine.core_cmd_reg[3]_0\(3),
- I1 => \statemachine.core_cmd_reg[3]_0\(2),
- I2 => \statemachine.core_cmd_reg[3]_0\(0),
- I3 => \statemachine.core_cmd_reg[3]_0\(1),
- I4 => c_state(1),
- I5 => c_state(2),
- O => \FSM_sequential_c_state[3]_i_3_n_0\
- );
-\FSM_sequential_c_state[4]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"BBBBBBBFAAAAAAAA"
- )
- port map (
- I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
- I1 => c_state(4),
- I2 => c_state(3),
- I3 => c_state(1),
- I4 => c_state(2),
- I5 => clk_en,
- O => \FSM_sequential_c_state[4]_i_1_n_0\
- );
-\FSM_sequential_c_state[4]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000080FF8000"
- )
- port map (
- I0 => c_state(3),
- I1 => c_state(1),
- I2 => c_state(2),
- I3 => c_state(0),
- I4 => c_state(4),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \FSM_sequential_c_state[4]_i_2_n_0\
- );
-\FSM_sequential_c_state[4]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => i2c_al,
- I1 => s00_axi_aresetn,
- O => \FSM_sequential_c_state[4]_i_3_n_0\
- );
-\FSM_sequential_c_state_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[0]_i_1_n_0\,
- Q => c_state(0)
- );
-\FSM_sequential_c_state_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[1]_i_1_n_0\,
- Q => c_state(1)
- );
-\FSM_sequential_c_state_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[2]_i_1_n_0\,
- Q => c_state(2)
- );
-\FSM_sequential_c_state_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[3]_i_1_n_0\,
- Q => c_state(3)
- );
-\FSM_sequential_c_state_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[4]_i_2_n_0\,
- Q => c_state(4)
- );
-\FSM_sequential_statemachine.c_state[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \FSM_sequential_statemachine.c_state_reg[1]_1\,
- I1 => \out\(2),
- I2 => \out\(1),
- I3 => \cr_reg[7]\(2),
- I4 => \out\(0),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \FSM_sequential_statemachine.c_state_reg[2]\(0)
- );
-\FSM_sequential_statemachine.c_state[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000015100000"
- )
- port map (
- I0 => \out\(2),
- I1 => cnt_done,
- I2 => \out\(1),
- I3 => \cr_reg[7]_0\,
- I4 => s00_axi_aresetn,
- I5 => i2c_al,
- O => \FSM_sequential_statemachine.c_state_reg[2]\(1)
- );
-\FSM_sequential_statemachine.c_state[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"DDFFDDDDFFFDDDFD"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_al,
- I2 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
- I3 => \out\(1),
- I4 => core_ack,
- I5 => \out\(2),
- O => E(0)
- );
-\FSM_sequential_statemachine.c_state[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \FSM_sequential_statemachine.c_state_reg[1]_2\,
- I1 => \out\(2),
- I2 => \out\(1),
- I3 => \cr_reg[7]\(2),
- I4 => \out\(0),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \FSM_sequential_statemachine.c_state_reg[2]\(2)
- );
-\FSM_sequential_statemachine.c_state[2]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8B8B8B8B8B8B8B88"
- )
- port map (
- I0 => core_ack,
- I1 => \out\(0),
- I2 => cmd_ack,
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(1),
- I5 => \cr_reg[7]\(2),
- O => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\
- );
-\bus_status_ctrl.cSCL[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_scl_io,
- O => \bus_status_ctrl.cSCL[0]_i_1_n_0\
- );
-\bus_status_ctrl.cSCL[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \p_0_in__0\(1),
- O => \bus_status_ctrl.cSCL[1]_i_1_n_0\
- );
-\bus_status_ctrl.cSCL_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSCL[0]_i_1_n_0\,
- Q => \p_0_in__0\(1)
- );
-\bus_status_ctrl.cSCL_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSCL[1]_i_1_n_0\,
- Q => \p_0_in__1\(0)
- );
-\bus_status_ctrl.cSDA[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_sda_io,
- O => \bus_status_ctrl.cSDA[0]_i_1_n_0\
- );
-\bus_status_ctrl.cSDA[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => p_0_in(1),
- O => \bus_status_ctrl.cSDA[1]_i_1_n_0\
- );
-\bus_status_ctrl.cSDA_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSDA[0]_i_1_n_0\,
- Q => p_0_in(1)
- );
-\bus_status_ctrl.cSDA_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSDA[1]_i_1_n_0\,
- Q => \bus_status_ctrl.cSDA_reg_n_0_[1]\
- );
-\bus_status_ctrl.cmd_stop_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"04FF000004000000"
- )
- port map (
- I0 => \statemachine.core_cmd_reg[3]_0\(0),
- I1 => \statemachine.core_cmd_reg[3]_0\(1),
- I2 => \bus_status_ctrl.cmd_stop_i_2_n_0\,
- I3 => clk_en,
- I4 => s00_axi_aresetn,
- I5 => \bus_status_ctrl.cmd_stop_reg_n_0\,
- O => \bus_status_ctrl.cmd_stop_i_1_n_0\
- );
-\bus_status_ctrl.cmd_stop_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => \statemachine.core_cmd_reg[3]_0\(2),
- I1 => \statemachine.core_cmd_reg[3]_0\(3),
- O => \bus_status_ctrl.cmd_stop_i_2_n_0\
- );
-\bus_status_ctrl.cmd_stop_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cmd_stop_i_1_n_0\,
- Q => \bus_status_ctrl.cmd_stop_reg_n_0\
- );
-\bus_status_ctrl.dSCL_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => sSCL,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.dSCL_i_1_n_0\
- );
-\bus_status_ctrl.dSCL_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.dSCL_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => dSCL
- );
-\bus_status_ctrl.dSDA_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => sSDA,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.dSDA_i_1_n_0\
- );
-\bus_status_ctrl.dSDA_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.dSDA_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => dSDA
- );
-\bus_status_ctrl.dout_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FB08"
- )
- port map (
- I0 => sSDA,
- I1 => sSCL,
- I2 => dSCL,
- I3 => core_rxd,
- O => \bus_status_ctrl.dout_i_1_n_0\
- );
-\bus_status_ctrl.dout_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.dout_i_1_n_0\,
- Q => core_rxd
- );
-\bus_status_ctrl.fSCL[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \p_0_in__1\(0),
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSCL[0]_i_1_n_0\
- );
-\bus_status_ctrl.fSCL[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \p_0_in__1\(1),
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSCL[1]_i_1_n_0\
- );
-\bus_status_ctrl.fSCL[2]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \p_0_in__1\(2),
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSCL[2]_i_1_n_0\
- );
-\bus_status_ctrl.fSCL_reg[0]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSCL[0]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \p_0_in__1\(1)
- );
-\bus_status_ctrl.fSCL_reg[1]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSCL[1]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \p_0_in__1\(2)
- );
-\bus_status_ctrl.fSCL_reg[2]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSCL[2]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSCL_reg_n_0_[2]\
- );
-\bus_status_ctrl.fSDA[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.cSDA_reg_n_0_[1]\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[0]_i_1_n_0\
- );
-\bus_status_ctrl.fSDA[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[1]_i_1_n_0\
- );
-\bus_status_ctrl.fSDA[2]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[2]_i_1_n_0\
- );
-\bus_status_ctrl.fSDA[2]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[2]_i_2_n_0\
- );
-\bus_status_ctrl.fSDA_reg[0]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSDA[0]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSDA_reg_n_0_[0]\
- );
-\bus_status_ctrl.fSDA_reg[1]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSDA[1]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSDA_reg_n_0_[1]\
- );
-\bus_status_ctrl.fSDA_reg[2]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSDA[2]_i_2_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSDA_reg_n_0_[2]\
- );
-\bus_status_ctrl.filter_cnt[0]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"D1000000"
- )
- port map (
- I0 => filter_cnt(0),
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(2),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[10]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_6\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(12),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[11]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_5\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(13),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[12]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_4\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(14),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__2_n_7\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(15),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000000001"
- )
- port map (
- I0 => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\,
- I2 => filter_cnt(6),
- I3 => filter_cnt(7),
- I4 => filter_cnt(4),
- I5 => filter_cnt(5),
- O => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFE"
- )
- port map (
- I0 => filter_cnt(13),
- I1 => filter_cnt(12),
- I2 => filter_cnt(9),
- I3 => filter_cnt(8),
- I4 => filter_cnt(11),
- I5 => filter_cnt(10),
- O => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_4\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => filter_cnt(2),
- I1 => filter_cnt(3),
- I2 => filter_cnt(0),
- I3 => filter_cnt(1),
- O => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\
- );
-\bus_status_ctrl.filter_cnt[1]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_7,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(3),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[2]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_6,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(4),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[3]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_5,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(5),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[4]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_4,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(6),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[5]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_7\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(7),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[6]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_6\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(8),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_5\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(9),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[8]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_4\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(10),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[9]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_7\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(11),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\,
- Q => filter_cnt(0)
- );
-\bus_status_ctrl.filter_cnt_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\,
- Q => filter_cnt(10)
- );
-\bus_status_ctrl.filter_cnt_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\,
- Q => filter_cnt(11)
- );
-\bus_status_ctrl.filter_cnt_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\,
- Q => filter_cnt(12)
- );
-\bus_status_ctrl.filter_cnt_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\,
- Q => filter_cnt(13)
- );
-\bus_status_ctrl.filter_cnt_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\,
- Q => filter_cnt(1)
- );
-\bus_status_ctrl.filter_cnt_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\,
- Q => filter_cnt(2)
- );
-\bus_status_ctrl.filter_cnt_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\,
- Q => filter_cnt(3)
- );
-\bus_status_ctrl.filter_cnt_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\,
- Q => filter_cnt(4)
- );
-\bus_status_ctrl.filter_cnt_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\,
- Q => filter_cnt(5)
- );
-\bus_status_ctrl.filter_cnt_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\,
- Q => filter_cnt(6)
- );
-\bus_status_ctrl.filter_cnt_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\,
- Q => filter_cnt(7)
- );
-\bus_status_ctrl.filter_cnt_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\,
- Q => filter_cnt(8)
- );
-\bus_status_ctrl.filter_cnt_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\,
- Q => filter_cnt(9)
- );
-\bus_status_ctrl.ial_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"08000800AAAA0800"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => sda_chk_reg_n_0,
- I2 => sSDA,
- I3 => sda_padoen_o,
- I4 => \bus_status_ctrl.ial_i_2_n_0\,
- I5 => \bus_status_ctrl.ial_i_3_n_0\,
- O => ial
- );
-\bus_status_ctrl.ial_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => c_state(0),
- I1 => c_state(4),
- O => \bus_status_ctrl.ial_i_2_n_0\
- );
-\bus_status_ctrl.ial_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFEF"
- )
- port map (
- I0 => c_state(2),
- I1 => c_state(3),
- I2 => \bus_status_ctrl.sto_condition_reg_n_0\,
- I3 => \bus_status_ctrl.cmd_stop_reg_n_0\,
- I4 => c_state(1),
- O => \bus_status_ctrl.ial_i_3_n_0\
- );
-\bus_status_ctrl.ial_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => ial,
- Q => i2c_al
- );
-\bus_status_ctrl.ibusy_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"5400"
- )
- port map (
- I0 => \bus_status_ctrl.sto_condition_reg_n_0\,
- I1 => \bus_status_ctrl.sta_condition_reg_n_0\,
- I2 => i2c_busy,
- I3 => s00_axi_aresetn,
- O => ibusy
- );
-\bus_status_ctrl.ibusy_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => ibusy,
- Q => i2c_busy
- );
-\bus_status_ctrl.sSCL_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E8FF"
- )
- port map (
- I0 => \p_0_in__1\(2),
- I1 => \bus_status_ctrl.fSCL_reg_n_0_[2]\,
- I2 => \p_0_in__1\(1),
- I3 => s00_axi_aresetn,
- O => \bus_status_ctrl.sSCL_i_1_n_0\
- );
-\bus_status_ctrl.sSCL_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.sSCL_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => sSCL
- );
-\bus_status_ctrl.sSDA_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E8FF"
- )
- port map (
- I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
- I1 => \bus_status_ctrl.fSDA_reg_n_0_[2]\,
- I2 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
- I3 => s00_axi_aresetn,
- O => \bus_status_ctrl.sSDA_i_1_n_0\
- );
-\bus_status_ctrl.sSDA_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.sSDA_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => sSDA
- );
-\bus_status_ctrl.sta_condition_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"2000"
- )
- port map (
- I0 => dSDA,
- I1 => sSDA,
- I2 => s00_axi_aresetn,
- I3 => sSCL,
- O => sta_condition
- );
-\bus_status_ctrl.sta_condition_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => sta_condition,
- Q => \bus_status_ctrl.sta_condition_reg_n_0\
- );
-\bus_status_ctrl.sto_condition_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4000"
- )
- port map (
- I0 => dSDA,
- I1 => s00_axi_aresetn,
- I2 => sSCL,
- I3 => sSDA,
- O => sto_condition
- );
-\bus_status_ctrl.sto_condition_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => sto_condition,
- Q => \bus_status_ctrl.sto_condition_reg_n_0\
- );
-clk_en_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AAAAAAAB"
- )
- port map (
- I0 => clk_en_i_2_n_0,
- I1 => clk_en_i_3_n_0,
- I2 => clk_en_i_4_n_0,
- I3 => clk_en_i_5_n_0,
- I4 => clk_en_i_6_n_0,
- O => cnt1
- );
-clk_en_i_2: unisim.vcomponents.LUT5
- generic map(
- INIT => X"7555FFFF"
- )
- port map (
- I0 => \ctr_reg[7]\(0),
- I1 => sSCL,
- I2 => scl_padoen_o,
- I3 => dSCL,
- I4 => s00_axi_aresetn,
- O => clk_en_i_2_n_0
- );
-clk_en_i_3: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(6),
- I1 => cnt_reg(7),
- I2 => cnt_reg(4),
- I3 => cnt_reg(5),
- O => clk_en_i_3_n_0
- );
-clk_en_i_4: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(2),
- I1 => cnt_reg(3),
- I2 => cnt_reg(0),
- I3 => cnt_reg(1),
- O => clk_en_i_4_n_0
- );
-clk_en_i_5: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(15),
- I1 => cnt_reg(14),
- I2 => cnt_reg(12),
- I3 => cnt_reg(13),
- O => clk_en_i_5_n_0
- );
-clk_en_i_6: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(10),
- I1 => cnt_reg(11),
- I2 => cnt_reg(8),
- I3 => cnt_reg(9),
- O => clk_en_i_6_n_0
- );
-clk_en_reg: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cnt1,
- PRE => \^iscl_oen_reg_0\,
- Q => clk_en
- );
-cmd_ack_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0008000000000000"
- )
- port map (
- I0 => cmd_ack_i_2_n_0,
- I1 => c_state(0),
- I2 => c_state(1),
- I3 => i2c_al,
- I4 => s00_axi_aresetn,
- I5 => clk_en,
- O => cmd_ack3_out
- );
-cmd_ack_i_2: unisim.vcomponents.LUT3
- generic map(
- INIT => X"1E"
- )
- port map (
- I0 => c_state(2),
- I1 => c_state(3),
- I2 => c_state(4),
- O => cmd_ack_i_2_n_0
- );
-cmd_ack_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => cmd_ack3_out,
- Q => core_ack
- );
-\cnt[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => cnt1,
- I1 => slave_wait,
- O => \cnt[0]_i_1_n_0\
- );
-\cnt[0]_i_10\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(0),
- I1 => Q(0),
- I2 => cnt1,
- O => \cnt[0]_i_10_n_0\
- );
-\cnt[0]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(3),
- I1 => cnt1,
- I2 => cnt_reg(3),
- O => \cnt[0]_i_3_n_0\
- );
-\cnt[0]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(2),
- I1 => cnt1,
- I2 => cnt_reg(2),
- O => \cnt[0]_i_4_n_0\
- );
-\cnt[0]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(1),
- I1 => cnt1,
- I2 => cnt_reg(1),
- O => \cnt[0]_i_5_n_0\
- );
-\cnt[0]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(0),
- I1 => cnt1,
- I2 => cnt_reg(0),
- O => \cnt[0]_i_6_n_0\
- );
-\cnt[0]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(3),
- I1 => Q(3),
- I2 => cnt1,
- O => \cnt[0]_i_7_n_0\
- );
-\cnt[0]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(2),
- I1 => Q(2),
- I2 => cnt1,
- O => \cnt[0]_i_8_n_0\
- );
-\cnt[0]_i_9\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(1),
- I1 => Q(1),
- I2 => cnt1,
- O => \cnt[0]_i_9_n_0\
- );
-\cnt[12]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(14),
- I1 => cnt1,
- I2 => cnt_reg(14),
- O => \cnt[12]_i_2_n_0\
- );
-\cnt[12]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(13),
- I1 => cnt1,
- I2 => cnt_reg(13),
- O => \cnt[12]_i_3_n_0\
- );
-\cnt[12]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(12),
- I1 => cnt1,
- I2 => cnt_reg(12),
- O => \cnt[12]_i_4_n_0\
- );
-\cnt[12]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(15),
- I1 => Q(15),
- I2 => cnt1,
- O => \cnt[12]_i_5_n_0\
- );
-\cnt[12]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(14),
- I1 => Q(14),
- I2 => cnt1,
- O => \cnt[12]_i_6_n_0\
- );
-\cnt[12]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(13),
- I1 => Q(13),
- I2 => cnt1,
- O => \cnt[12]_i_7_n_0\
- );
-\cnt[12]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(12),
- I1 => Q(12),
- I2 => cnt1,
- O => \cnt[12]_i_8_n_0\
- );
-\cnt[4]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(7),
- I1 => cnt1,
- I2 => cnt_reg(7),
- O => \cnt[4]_i_2_n_0\
- );
-\cnt[4]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(6),
- I1 => cnt1,
- I2 => cnt_reg(6),
- O => \cnt[4]_i_3_n_0\
- );
-\cnt[4]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(5),
- I1 => cnt1,
- I2 => cnt_reg(5),
- O => \cnt[4]_i_4_n_0\
- );
-\cnt[4]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(4),
- I1 => cnt1,
- I2 => cnt_reg(4),
- O => \cnt[4]_i_5_n_0\
- );
-\cnt[4]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(7),
- I1 => Q(7),
- I2 => cnt1,
- O => \cnt[4]_i_6_n_0\
- );
-\cnt[4]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(6),
- I1 => Q(6),
- I2 => cnt1,
- O => \cnt[4]_i_7_n_0\
- );
-\cnt[4]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(5),
- I1 => Q(5),
- I2 => cnt1,
- O => \cnt[4]_i_8_n_0\
- );
-\cnt[4]_i_9\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(4),
- I1 => Q(4),
- I2 => cnt1,
- O => \cnt[4]_i_9_n_0\
- );
-\cnt[8]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(11),
- I1 => cnt1,
- I2 => cnt_reg(11),
- O => \cnt[8]_i_2_n_0\
- );
-\cnt[8]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(10),
- I1 => cnt1,
- I2 => cnt_reg(10),
- O => \cnt[8]_i_3_n_0\
- );
-\cnt[8]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(9),
- I1 => cnt1,
- I2 => cnt_reg(9),
- O => \cnt[8]_i_4_n_0\
- );
-\cnt[8]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(8),
- I1 => cnt1,
- I2 => cnt_reg(8),
- O => \cnt[8]_i_5_n_0\
- );
-\cnt[8]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(11),
- I1 => Q(11),
- I2 => cnt1,
- O => \cnt[8]_i_6_n_0\
- );
-\cnt[8]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(10),
- I1 => Q(10),
- I2 => cnt1,
- O => \cnt[8]_i_7_n_0\
- );
-\cnt[8]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(9),
- I1 => Q(9),
- I2 => cnt1,
- O => \cnt[8]_i_8_n_0\
- );
-\cnt[8]_i_9\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(8),
- I1 => Q(8),
- I2 => cnt1,
- O => \cnt[8]_i_9_n_0\
- );
-\cnt_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_7\,
- Q => cnt_reg(0)
- );
-\cnt_reg[0]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \cnt_reg[0]_i_2_n_0\,
- CO(2) => \cnt_reg[0]_i_2_n_1\,
- CO(1) => \cnt_reg[0]_i_2_n_2\,
- CO(0) => \cnt_reg[0]_i_2_n_3\,
- CYINIT => '0',
- DI(3) => \cnt[0]_i_3_n_0\,
- DI(2) => \cnt[0]_i_4_n_0\,
- DI(1) => \cnt[0]_i_5_n_0\,
- DI(0) => \cnt[0]_i_6_n_0\,
- O(3) => \cnt_reg[0]_i_2_n_4\,
- O(2) => \cnt_reg[0]_i_2_n_5\,
- O(1) => \cnt_reg[0]_i_2_n_6\,
- O(0) => \cnt_reg[0]_i_2_n_7\,
- S(3) => \cnt[0]_i_7_n_0\,
- S(2) => \cnt[0]_i_8_n_0\,
- S(1) => \cnt[0]_i_9_n_0\,
- S(0) => \cnt[0]_i_10_n_0\
- );
-\cnt_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_5\,
- Q => cnt_reg(10)
- );
-\cnt_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_4\,
- Q => cnt_reg(11)
- );
-\cnt_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_7\,
- Q => cnt_reg(12)
- );
-\cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \cnt_reg[8]_i_1_n_0\,
- CO(3) => \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\(3),
- CO(2) => \cnt_reg[12]_i_1_n_1\,
- CO(1) => \cnt_reg[12]_i_1_n_2\,
- CO(0) => \cnt_reg[12]_i_1_n_3\,
- CYINIT => '0',
- DI(3) => '0',
- DI(2) => \cnt[12]_i_2_n_0\,
- DI(1) => \cnt[12]_i_3_n_0\,
- DI(0) => \cnt[12]_i_4_n_0\,
- O(3) => \cnt_reg[12]_i_1_n_4\,
- O(2) => \cnt_reg[12]_i_1_n_5\,
- O(1) => \cnt_reg[12]_i_1_n_6\,
- O(0) => \cnt_reg[12]_i_1_n_7\,
- S(3) => \cnt[12]_i_5_n_0\,
- S(2) => \cnt[12]_i_6_n_0\,
- S(1) => \cnt[12]_i_7_n_0\,
- S(0) => \cnt[12]_i_8_n_0\
- );
-\cnt_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_6\,
- Q => cnt_reg(13)
- );
-\cnt_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_5\,
- Q => cnt_reg(14)
- );
-\cnt_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_4\,
- Q => cnt_reg(15)
- );
-\cnt_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_6\,
- Q => cnt_reg(1)
- );
-\cnt_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_5\,
- Q => cnt_reg(2)
- );
-\cnt_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_4\,
- Q => cnt_reg(3)
- );
-\cnt_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_7\,
- Q => cnt_reg(4)
- );
-\cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \cnt_reg[0]_i_2_n_0\,
- CO(3) => \cnt_reg[4]_i_1_n_0\,
- CO(2) => \cnt_reg[4]_i_1_n_1\,
- CO(1) => \cnt_reg[4]_i_1_n_2\,
- CO(0) => \cnt_reg[4]_i_1_n_3\,
- CYINIT => '0',
- DI(3) => \cnt[4]_i_2_n_0\,
- DI(2) => \cnt[4]_i_3_n_0\,
- DI(1) => \cnt[4]_i_4_n_0\,
- DI(0) => \cnt[4]_i_5_n_0\,
- O(3) => \cnt_reg[4]_i_1_n_4\,
- O(2) => \cnt_reg[4]_i_1_n_5\,
- O(1) => \cnt_reg[4]_i_1_n_6\,
- O(0) => \cnt_reg[4]_i_1_n_7\,
- S(3) => \cnt[4]_i_6_n_0\,
- S(2) => \cnt[4]_i_7_n_0\,
- S(1) => \cnt[4]_i_8_n_0\,
- S(0) => \cnt[4]_i_9_n_0\
- );
-\cnt_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_6\,
- Q => cnt_reg(5)
- );
-\cnt_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_5\,
- Q => cnt_reg(6)
- );
-\cnt_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_4\,
- Q => cnt_reg(7)
- );
-\cnt_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_7\,
- Q => cnt_reg(8)
- );
-\cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \cnt_reg[4]_i_1_n_0\,
- CO(3) => \cnt_reg[8]_i_1_n_0\,
- CO(2) => \cnt_reg[8]_i_1_n_1\,
- CO(1) => \cnt_reg[8]_i_1_n_2\,
- CO(0) => \cnt_reg[8]_i_1_n_3\,
- CYINIT => '0',
- DI(3) => \cnt[8]_i_2_n_0\,
- DI(2) => \cnt[8]_i_3_n_0\,
- DI(1) => \cnt[8]_i_4_n_0\,
- DI(0) => \cnt[8]_i_5_n_0\,
- O(3) => \cnt_reg[8]_i_1_n_4\,
- O(2) => \cnt_reg[8]_i_1_n_5\,
- O(1) => \cnt_reg[8]_i_1_n_6\,
- O(0) => \cnt_reg[8]_i_1_n_7\,
- S(3) => \cnt[8]_i_6_n_0\,
- S(2) => \cnt[8]_i_7_n_0\,
- S(1) => \cnt[8]_i_8_n_0\,
- S(0) => \cnt[8]_i_9_n_0\
- );
-\cnt_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_6\,
- Q => cnt_reg(9)
- );
-\cr[7]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"55FDFDFDFFFFFFFF"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_al,
- I2 => cmd_ack,
- I3 => iack_o_reg,
- I4 => wb_we_o,
- I5 => iack_o_reg_0,
- O => \cr_reg[4]\(0)
- );
-dscl_oen_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => scl_padoen_o,
- Q => dscl_oen
- );
-i2c_scl_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_scl_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_scl_io
- );
-i2c_scl_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => scl_padoen_o,
- O => i2c_scl_io_INST_0_i_1_n_0
- );
-i2c_sda_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_sda_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_sda_io
- );
-i2c_sda_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => sda_padoen_o,
- O => i2c_sda_io_INST_0_i_1_n_0
- );
-iscl_oen_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FBFFFBF3"
- )
- port map (
- I0 => iscl_oen,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- I3 => \iscl_oen9_out__0\,
- I4 => scl_padoen_o,
- O => iscl_oen_i_1_n_0
- );
-iscl_oen_i_2: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00F3011F"
- )
- port map (
- I0 => c_state(3),
- I1 => c_state(2),
- I2 => c_state(1),
- I3 => c_state(4),
- I4 => c_state(0),
- O => iscl_oen
- );
-iscl_oen_i_3: unisim.vcomponents.LUT5
- generic map(
- INIT => X"55560000"
- )
- port map (
- I0 => c_state(4),
- I1 => c_state(3),
- I2 => c_state(2),
- I3 => c_state(1),
- I4 => clk_en,
- O => \iscl_oen9_out__0\
- );
-iscl_oen_reg: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => iscl_oen_i_1_n_0,
- PRE => \^iscl_oen_reg_0\,
- Q => scl_padoen_o
- );
-isda_oen_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FBFFFBF3"
- )
- port map (
- I0 => isda_oen,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- I3 => \isda_oen7_out__0\,
- I4 => sda_padoen_o,
- O => isda_oen_i_1_n_0
- );
-isda_oen_i_2: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000C8CB03038F83"
- )
- port map (
- I0 => \statemachine.core_txd_reg_0\,
- I1 => c_state(3),
- I2 => c_state(2),
- I3 => c_state(0),
- I4 => c_state(4),
- I5 => c_state(1),
- O => isda_oen
- );
-isda_oen_i_3: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0F0F1F1E00000000"
- )
- port map (
- I0 => c_state(1),
- I1 => c_state(2),
- I2 => c_state(4),
- I3 => c_state(0),
- I4 => c_state(3),
- I5 => clk_en,
- O => \isda_oen7_out__0\
- );
-isda_oen_reg: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => isda_oen_i_1_n_0,
- PRE => \^iscl_oen_reg_0\,
- Q => sda_padoen_o
- );
-minusOp_carry: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => minusOp_carry_n_0,
- CO(2) => minusOp_carry_n_1,
- CO(1) => minusOp_carry_n_2,
- CO(0) => minusOp_carry_n_3,
- CYINIT => filter_cnt(0),
- DI(3 downto 0) => filter_cnt(4 downto 1),
- O(3) => minusOp_carry_n_4,
- O(2) => minusOp_carry_n_5,
- O(1) => minusOp_carry_n_6,
- O(0) => minusOp_carry_n_7,
- S(3) => minusOp_carry_i_1_n_0,
- S(2) => minusOp_carry_i_2_n_0,
- S(1) => minusOp_carry_i_3_n_0,
- S(0) => minusOp_carry_i_4_n_0
- );
-\minusOp_carry__0\: unisim.vcomponents.CARRY4
- port map (
- CI => minusOp_carry_n_0,
- CO(3) => \minusOp_carry__0_n_0\,
- CO(2) => \minusOp_carry__0_n_1\,
- CO(1) => \minusOp_carry__0_n_2\,
- CO(0) => \minusOp_carry__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => filter_cnt(8 downto 5),
- O(3) => \minusOp_carry__0_n_4\,
- O(2) => \minusOp_carry__0_n_5\,
- O(1) => \minusOp_carry__0_n_6\,
- O(0) => \minusOp_carry__0_n_7\,
- S(3) => \minusOp_carry__0_i_1_n_0\,
- S(2) => \minusOp_carry__0_i_2_n_0\,
- S(1) => \minusOp_carry__0_i_3_n_0\,
- S(0) => \minusOp_carry__0_i_4_n_0\
- );
-\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(8),
- O => \minusOp_carry__0_i_1_n_0\
- );
-\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(7),
- O => \minusOp_carry__0_i_2_n_0\
- );
-\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(6),
- O => \minusOp_carry__0_i_3_n_0\
- );
-\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(5),
- O => \minusOp_carry__0_i_4_n_0\
- );
-\minusOp_carry__1\: unisim.vcomponents.CARRY4
- port map (
- CI => \minusOp_carry__0_n_0\,
- CO(3) => \minusOp_carry__1_n_0\,
- CO(2) => \minusOp_carry__1_n_1\,
- CO(1) => \minusOp_carry__1_n_2\,
- CO(0) => \minusOp_carry__1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => filter_cnt(12 downto 9),
- O(3) => \minusOp_carry__1_n_4\,
- O(2) => \minusOp_carry__1_n_5\,
- O(1) => \minusOp_carry__1_n_6\,
- O(0) => \minusOp_carry__1_n_7\,
- S(3) => \minusOp_carry__1_i_1_n_0\,
- S(2) => \minusOp_carry__1_i_2_n_0\,
- S(1) => \minusOp_carry__1_i_3_n_0\,
- S(0) => \minusOp_carry__1_i_4_n_0\
- );
-\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(12),
- O => \minusOp_carry__1_i_1_n_0\
- );
-\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(11),
- O => \minusOp_carry__1_i_2_n_0\
- );
-\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(10),
- O => \minusOp_carry__1_i_3_n_0\
- );
-\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(9),
- O => \minusOp_carry__1_i_4_n_0\
- );
-\minusOp_carry__2\: unisim.vcomponents.CARRY4
- port map (
- CI => \minusOp_carry__1_n_0\,
- CO(3 downto 0) => \NLW_minusOp_carry__2_CO_UNCONNECTED\(3 downto 0),
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 1) => \NLW_minusOp_carry__2_O_UNCONNECTED\(3 downto 1),
- O(0) => \minusOp_carry__2_n_7\,
- S(3 downto 1) => B"000",
- S(0) => \minusOp_carry__2_i_1_n_0\
- );
-\minusOp_carry__2_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(13),
- O => \minusOp_carry__2_i_1_n_0\
- );
-minusOp_carry_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(4),
- O => minusOp_carry_i_1_n_0
- );
-minusOp_carry_i_2: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(3),
- O => minusOp_carry_i_2_n_0
- );
-minusOp_carry_i_3: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(2),
- O => minusOp_carry_i_3_n_0
- );
-minusOp_carry_i_4: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(1),
- O => minusOp_carry_i_4_n_0
- );
-sda_chk_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000100000"
- )
- port map (
- I0 => c_state(4),
- I1 => c_state(1),
- I2 => c_state(3),
- I3 => c_state(0),
- I4 => c_state(2),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => sda_chk_i_1_n_0
- );
-sda_chk_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => sda_chk_i_1_n_0,
- Q => sda_chk_reg_n_0
- );
-slave_wait_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0F04"
- )
- port map (
- I0 => dscl_oen,
- I1 => scl_padoen_o,
- I2 => sSCL,
- I3 => slave_wait,
- O => slave_wait0
- );
-slave_wait_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => slave_wait0,
- Q => slave_wait
- );
-\sr[0]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_0\,
- I1 => core_rxd,
- I2 => \txr_reg[6]\(0),
- I3 => s00_axi_aresetn,
- O => \sr_reg[0]\(0)
- );
-\st_irq_block.al_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"AA08"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \st_irq_block.al_reg\,
- I2 => \cr_reg[7]\(3),
- I3 => i2c_al,
- O => al
- );
-\st_irq_block.irq_flag_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"55540000"
- )
- port map (
- I0 => \cr_reg[0]\,
- I1 => i2c_al,
- I2 => cmd_ack,
- I3 => irq_flag,
- I4 => s00_axi_aresetn,
- O => irq_flag1_out
- );
-\st_irq_block.wb_inta_o_i_2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s00_axi_aresetn,
- O => \^iscl_oen_reg_0\
- );
-\statemachine.ack_out_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"08FF0800"
- )
- port map (
- I0 => core_rxd,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- I3 => \statemachine.ack_out_i_2_n_0\,
- I4 => ack_out,
- O => \statemachine.ack_out_reg\
- );
-\statemachine.ack_out_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"DDDDDDDDDDFDDDDD"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_al,
- I2 => \out\(2),
- I3 => \out\(0),
- I4 => core_ack,
- I5 => \out\(1),
- O => \statemachine.ack_out_i_2_n_0\
- );
-\statemachine.core_cmd[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000100000"
- )
- port map (
- I0 => \out\(2),
- I1 => \out\(0),
- I2 => \cr_reg[7]\(3),
- I3 => \out\(1),
- I4 => s00_axi_aresetn,
- I5 => i2c_al,
- O => \statemachine.core_cmd_reg[3]\(0)
- );
-\statemachine.core_cmd[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \FSM_sequential_statemachine.c_state_reg[1]_0\,
- I1 => \out\(2),
- I2 => \out\(1),
- I3 => \cr_reg[7]\(2),
- I4 => \out\(0),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \statemachine.core_cmd_reg[3]\(1)
- );
-\statemachine.core_cmd[2]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => core_cmd(0),
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- O => \statemachine.core_cmd_reg[3]\(2)
- );
-\statemachine.core_cmd[3]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0040"
- )
- port map (
- I0 => \out\(2),
- I1 => \FSM_sequential_statemachine.c_state_reg[1]\,
- I2 => s00_axi_aresetn,
- I3 => i2c_al,
- O => \statemachine.core_cmd_reg[3]\(3)
- );
-\statemachine.core_txd_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => core_txd,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- O => \statemachine.core_txd_reg\
- );
-\statemachine.core_txd_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"5455FFFD10002220"
- )
- port map (
- I0 => \out\(2),
- I1 => \out\(0),
- I2 => ack_in,
- I3 => core_ack,
- I4 => \out\(1),
- I5 => \sr_reg[7]\(0),
- O => core_txd
- );
-\statemachine.host_ack_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000000000A020"
- )
- port map (
- I0 => \out\(2),
- I1 => \cr_reg[7]\(2),
- I2 => core_ack,
- I3 => \out\(0),
- I4 => \out\(1),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \statemachine.host_ack_reg\
- );
-\statemachine.ld_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00000400"
- )
- port map (
- I0 => \out\(2),
- I1 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
- I2 => \out\(1),
- I3 => s00_axi_aresetn,
- I4 => i2c_al,
- O => \statemachine.ld_reg\
- );
-\statemachine.shift_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000004440000"
- )
- port map (
- I0 => \out\(2),
- I1 => core_ack,
- I2 => \out\(0),
- I3 => cnt_done,
- I4 => \out\(1),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \statemachine.shift_reg\
- );
-\wb_dat_o[6]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \cr_reg[7]\(2),
- I1 => wb_adr_o(1),
- I2 => \txr_reg[6]\(1),
- I3 => wb_adr_o(0),
- I4 => i2c_busy,
- O => \wb_dat_o[6]_i_3_n_0\
- );
-\wb_dat_o_reg[6]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \sr_reg[6]\,
- I1 => \wb_dat_o[6]_i_3_n_0\,
- O => D(0),
- S => wb_adr_o(2)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl is
- port (
- iscl_oen_reg : out STD_LOGIC;
- irq_flag1_out : out STD_LOGIC;
- rxack_0 : out STD_LOGIC;
- al : out STD_LOGIC;
- D : out STD_LOGIC_VECTOR ( 7 downto 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \cr_reg[0]\ : in STD_LOGIC;
- irq_flag : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
- \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
- \st_irq_block.al_reg\ : in STD_LOGIC;
- \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \cr_reg[0]_0\ : in STD_LOGIC;
- \cr_reg[1]\ : in STD_LOGIC;
- \cr_reg[2]\ : in STD_LOGIC;
- \txr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
- ack_in : in STD_LOGIC;
- \cr_reg[5]\ : in STD_LOGIC;
- \cr_reg[7]_0\ : in STD_LOGIC;
- iack_o_reg : in STD_LOGIC;
- wb_we_o : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl : entity is "i2c_master_byte_ctrl";
-end system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl is
- signal \FSM_sequential_statemachine.c_state[0]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_statemachine.c_state[1]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_statemachine.c_state[2]_i_4_n_0\ : STD_LOGIC;
- signal ack_out : STD_LOGIC;
- signal bit_ctrl_n_10 : STD_LOGIC;
- signal bit_ctrl_n_11 : STD_LOGIC;
- signal bit_ctrl_n_12 : STD_LOGIC;
- signal bit_ctrl_n_13 : STD_LOGIC;
- signal bit_ctrl_n_15 : STD_LOGIC;
- signal bit_ctrl_n_16 : STD_LOGIC;
- signal bit_ctrl_n_17 : STD_LOGIC;
- signal bit_ctrl_n_18 : STD_LOGIC;
- signal bit_ctrl_n_5 : STD_LOGIC;
- signal bit_ctrl_n_6 : STD_LOGIC;
- signal bit_ctrl_n_7 : STD_LOGIC;
- signal bit_ctrl_n_8 : STD_LOGIC;
- signal bit_ctrl_n_9 : STD_LOGIC;
- signal c_state : STD_LOGIC;
- signal \c_state__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute RTL_KEEP : string;
- attribute RTL_KEEP of \c_state__0\ : signal is "yes";
- signal cmd : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal cmd_ack : STD_LOGIC;
- signal cnt_done : STD_LOGIC;
- signal core_cmd : STD_LOGIC_VECTOR ( 2 to 2 );
- signal dcnt : STD_LOGIC;
- signal \dcnt[0]_i_1_n_0\ : STD_LOGIC;
- signal \dcnt[1]_i_1_n_0\ : STD_LOGIC;
- signal \dcnt[2]_i_1_n_0\ : STD_LOGIC;
- signal \dcnt_reg_n_0_[0]\ : STD_LOGIC;
- signal \dcnt_reg_n_0_[1]\ : STD_LOGIC;
- signal \dcnt_reg_n_0_[2]\ : STD_LOGIC;
- signal dout : STD_LOGIC_VECTOR ( 7 to 7 );
- signal \^iscl_oen_reg\ : STD_LOGIC;
- signal \sr[1]_i_1_n_0\ : STD_LOGIC;
- signal \sr[2]_i_1_n_0\ : STD_LOGIC;
- signal \sr[3]_i_1_n_0\ : STD_LOGIC;
- signal \sr[4]_i_1_n_0\ : STD_LOGIC;
- signal \sr[5]_i_1_n_0\ : STD_LOGIC;
- signal \sr[6]_i_1_n_0\ : STD_LOGIC;
- signal \sr[7]_i_2_n_0\ : STD_LOGIC;
- signal \sr_reg_n_0_[0]\ : STD_LOGIC;
- signal \sr_reg_n_0_[1]\ : STD_LOGIC;
- signal \sr_reg_n_0_[2]\ : STD_LOGIC;
- signal \sr_reg_n_0_[3]\ : STD_LOGIC;
- signal \sr_reg_n_0_[4]\ : STD_LOGIC;
- signal \sr_reg_n_0_[5]\ : STD_LOGIC;
- signal \sr_reg_n_0_[6]\ : STD_LOGIC;
- signal \statemachine.core_cmd[1]_i_2_n_0\ : STD_LOGIC;
- signal \statemachine.core_cmd[3]_i_2_n_0\ : STD_LOGIC;
- signal \statemachine.core_txd_reg_n_0\ : STD_LOGIC;
- signal \statemachine.ld_reg_n_0\ : STD_LOGIC;
- signal \statemachine.shift_reg_n_0\ : STD_LOGIC;
- signal \wb_dat_o[0]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[1]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[2]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[3]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[4]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[5]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[6]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[7]_i_2_n_0\ : STD_LOGIC;
- attribute KEEP : string;
- attribute KEEP of \FSM_sequential_statemachine.c_state_reg[0]\ : label is "yes";
- attribute KEEP of \FSM_sequential_statemachine.c_state_reg[1]\ : label is "yes";
- attribute KEEP of \FSM_sequential_statemachine.c_state_reg[2]\ : label is "yes";
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair23";
-begin
- iscl_oen_reg <= \^iscl_oen_reg\;
-\FSM_sequential_statemachine.c_state[0]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"43407373"
- )
- port map (
- I0 => cnt_done,
- I1 => \c_state__0\(1),
- I2 => \c_state__0\(0),
- I3 => \cr_reg[7]\(3),
- I4 => \cr_reg[7]\(1),
- O => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\
- );
-\FSM_sequential_statemachine.c_state[1]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"01"
- )
- port map (
- I0 => \dcnt_reg_n_0_[1]\,
- I1 => \dcnt_reg_n_0_[0]\,
- I2 => \dcnt_reg_n_0_[2]\,
- O => cnt_done
- );
-\FSM_sequential_statemachine.c_state[1]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FF54"
- )
- port map (
- I0 => \cr_reg[7]\(3),
- I1 => \cr_reg[7]\(1),
- I2 => \cr_reg[7]\(0),
- I3 => \c_state__0\(0),
- O => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\
- );
-\FSM_sequential_statemachine.c_state[2]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"888888888888888B"
- )
- port map (
- I0 => cnt_done,
- I1 => \c_state__0\(1),
- I2 => \cr_reg[7]\(3),
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(1),
- I5 => \c_state__0\(0),
- O => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\
- );
-\FSM_sequential_statemachine.c_state_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_18,
- Q => \c_state__0\(0)
- );
-\FSM_sequential_statemachine.c_state_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_17,
- Q => \c_state__0\(1)
- );
-\FSM_sequential_statemachine.c_state_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_16,
- Q => \c_state__0\(2)
- );
-bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
- port map (
- D(0) => D(6),
- E(0) => c_state,
- \FSM_sequential_statemachine.c_state_reg[1]\ => \statemachine.core_cmd[3]_i_2_n_0\,
- \FSM_sequential_statemachine.c_state_reg[1]_0\ => \statemachine.core_cmd[1]_i_2_n_0\,
- \FSM_sequential_statemachine.c_state_reg[1]_1\ => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\,
- \FSM_sequential_statemachine.c_state_reg[1]_2\ => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\,
- \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_16,
- \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_17,
- \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_18,
- Q(15 downto 0) => Q(15 downto 0),
- ack_in => ack_in,
- ack_out => ack_out,
- al => al,
- cmd_ack => cmd_ack,
- cnt_done => cnt_done,
- core_cmd(0) => core_cmd(2),
- \cr_reg[0]\ => \cr_reg[0]\,
- \cr_reg[4]\(0) => E(0),
- \cr_reg[7]\(3 downto 0) => \cr_reg[7]\(3 downto 0),
- \cr_reg[7]_0\ => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\,
- \ctr_reg[7]\(0) => \ctr_reg[7]\(7),
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- iack_o_reg => iack_o_reg,
- iack_o_reg_0 => iack_o_reg_0,
- irq_flag => irq_flag,
- irq_flag1_out => irq_flag1_out,
- iscl_oen_reg_0 => \^iscl_oen_reg\,
- \out\(2 downto 0) => \c_state__0\(2 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- \sr_reg[0]\(0) => bit_ctrl_n_15,
- \sr_reg[6]\ => \wb_dat_o[6]_i_2_n_0\,
- \sr_reg[7]\(0) => dout(7),
- \st_irq_block.al_reg\ => \st_irq_block.al_reg\,
- \statemachine.ack_out_reg\ => bit_ctrl_n_13,
- \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_5,
- \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_6,
- \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_7,
- \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_8,
- \statemachine.core_cmd_reg[3]_0\(3 downto 0) => cmd(3 downto 0),
- \statemachine.core_txd_reg\ => bit_ctrl_n_10,
- \statemachine.core_txd_reg_0\ => \statemachine.core_txd_reg_n_0\,
- \statemachine.host_ack_reg\ => bit_ctrl_n_12,
- \statemachine.ld_reg\ => bit_ctrl_n_9,
- \statemachine.ld_reg_0\ => \statemachine.ld_reg_n_0\,
- \statemachine.shift_reg\ => bit_ctrl_n_11,
- \txr_reg[6]\(1) => \txr_reg[7]\(6),
- \txr_reg[6]\(0) => \txr_reg[7]\(0),
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_we_o => wb_we_o
- );
-\dcnt[0]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"8A"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \statemachine.ld_reg_n_0\,
- I2 => \dcnt_reg_n_0_[0]\,
- O => \dcnt[0]_i_1_n_0\
- );
-\dcnt[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"A88A"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \statemachine.ld_reg_n_0\,
- I2 => \dcnt_reg_n_0_[0]\,
- I3 => \dcnt_reg_n_0_[1]\,
- O => \dcnt[1]_i_1_n_0\
- );
-\dcnt[2]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AAA8888A"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \statemachine.ld_reg_n_0\,
- I2 => \dcnt_reg_n_0_[1]\,
- I3 => \dcnt_reg_n_0_[0]\,
- I4 => \dcnt_reg_n_0_[2]\,
- O => \dcnt[2]_i_1_n_0\
- );
-\dcnt_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \dcnt[0]_i_1_n_0\,
- Q => \dcnt_reg_n_0_[0]\
- );
-\dcnt_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \dcnt[1]_i_1_n_0\,
- Q => \dcnt_reg_n_0_[1]\
- );
-\dcnt_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \dcnt[2]_i_1_n_0\,
- Q => \dcnt_reg_n_0_[2]\
- );
-\sr[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[0]\,
- I2 => \txr_reg[7]\(1),
- I3 => s00_axi_aresetn,
- O => \sr[1]_i_1_n_0\
- );
-\sr[2]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[1]\,
- I2 => \txr_reg[7]\(2),
- I3 => s00_axi_aresetn,
- O => \sr[2]_i_1_n_0\
- );
-\sr[3]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[2]\,
- I2 => \txr_reg[7]\(3),
- I3 => s00_axi_aresetn,
- O => \sr[3]_i_1_n_0\
- );
-\sr[4]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[3]\,
- I2 => \txr_reg[7]\(4),
- I3 => s00_axi_aresetn,
- O => \sr[4]_i_1_n_0\
- );
-\sr[5]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[4]\,
- I2 => \txr_reg[7]\(5),
- I3 => s00_axi_aresetn,
- O => \sr[5]_i_1_n_0\
- );
-\sr[6]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[5]\,
- I2 => \txr_reg[7]\(6),
- I3 => s00_axi_aresetn,
- O => \sr[6]_i_1_n_0\
- );
-\sr[7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"FB"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => s00_axi_aresetn,
- I2 => \statemachine.shift_reg_n_0\,
- O => dcnt
- );
-\sr[7]_i_2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[6]\,
- I2 => \txr_reg[7]\(7),
- I3 => s00_axi_aresetn,
- O => \sr[7]_i_2_n_0\
- );
-\sr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_15,
- Q => \sr_reg_n_0_[0]\
- );
-\sr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[1]_i_1_n_0\,
- Q => \sr_reg_n_0_[1]\
- );
-\sr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[2]_i_1_n_0\,
- Q => \sr_reg_n_0_[2]\
- );
-\sr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[3]_i_1_n_0\,
- Q => \sr_reg_n_0_[3]\
- );
-\sr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[4]_i_1_n_0\,
- Q => \sr_reg_n_0_[4]\
- );
-\sr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[5]_i_1_n_0\,
- Q => \sr_reg_n_0_[5]\
- );
-\sr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[6]_i_1_n_0\,
- Q => \sr_reg_n_0_[6]\
- );
-\sr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[7]_i_2_n_0\,
- Q => dout(7)
- );
-\st_irq_block.rxack_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => ack_out,
- O => rxack_0
- );
-\statemachine.ack_out_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_13,
- Q => ack_out
- );
-\statemachine.core_cmd[1]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00000001"
- )
- port map (
- I0 => \c_state__0\(1),
- I1 => \c_state__0\(0),
- I2 => \cr_reg[7]\(3),
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(1),
- O => \statemachine.core_cmd[1]_i_2_n_0\
- );
-\statemachine.core_cmd[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"00000000F0C40FC4"
- )
- port map (
- I0 => \cr_reg[7]\(3),
- I1 => \cr_reg[7]\(1),
- I2 => \c_state__0\(0),
- I3 => \c_state__0\(1),
- I4 => cnt_done,
- I5 => \c_state__0\(2),
- O => core_cmd(2)
- );
-\statemachine.core_cmd[3]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"4848484878787B78"
- )
- port map (
- I0 => cnt_done,
- I1 => \c_state__0\(1),
- I2 => \c_state__0\(0),
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(3),
- I5 => \cr_reg[7]\(1),
- O => \statemachine.core_cmd[3]_i_2_n_0\
- );
-\statemachine.core_cmd_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_8,
- Q => cmd(0)
- );
-\statemachine.core_cmd_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_7,
- Q => cmd(1)
- );
-\statemachine.core_cmd_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_6,
- Q => cmd(2)
- );
-\statemachine.core_cmd_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_5,
- Q => cmd(3)
- );
-\statemachine.core_txd_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_10,
- Q => \statemachine.core_txd_reg_n_0\
- );
-\statemachine.host_ack_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_12,
- Q => cmd_ack
- );
-\statemachine.ld_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_9,
- Q => \statemachine.ld_reg_n_0\
- );
-\statemachine.shift_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_11,
- Q => \statemachine.shift_reg_n_0\
- );
-\wb_dat_o[0]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[0]\,
- I1 => \ctr_reg[7]\(0),
- I2 => wb_adr_o(1),
- I3 => Q(8),
- I4 => wb_adr_o(0),
- I5 => Q(0),
- O => \wb_dat_o[0]_i_2_n_0\
- );
-\wb_dat_o[1]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[1]\,
- I1 => \ctr_reg[7]\(1),
- I2 => wb_adr_o(1),
- I3 => Q(9),
- I4 => wb_adr_o(0),
- I5 => Q(1),
- O => \wb_dat_o[1]_i_2_n_0\
- );
-\wb_dat_o[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"3808FFFF38080000"
- )
- port map (
- I0 => \cr_reg[2]\,
- I1 => wb_adr_o(1),
- I2 => wb_adr_o(0),
- I3 => \txr_reg[7]\(2),
- I4 => wb_adr_o(2),
- I5 => \wb_dat_o[2]_i_2_n_0\,
- O => D(2)
- );
-\wb_dat_o[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[2]\,
- I1 => \ctr_reg[7]\(2),
- I2 => wb_adr_o(1),
- I3 => Q(10),
- I4 => wb_adr_o(0),
- I5 => Q(2),
- O => \wb_dat_o[2]_i_2_n_0\
- );
-\wb_dat_o[3]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"3808FFFF38080000"
- )
- port map (
- I0 => ack_in,
- I1 => wb_adr_o(1),
- I2 => wb_adr_o(0),
- I3 => \txr_reg[7]\(3),
- I4 => wb_adr_o(2),
- I5 => \wb_dat_o[3]_i_2_n_0\,
- O => D(3)
- );
-\wb_dat_o[3]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[3]\,
- I1 => \ctr_reg[7]\(3),
- I2 => wb_adr_o(1),
- I3 => Q(11),
- I4 => wb_adr_o(0),
- I5 => Q(3),
- O => \wb_dat_o[3]_i_2_n_0\
- );
-\wb_dat_o[4]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"3808FFFF38080000"
- )
- port map (
- I0 => \cr_reg[7]\(0),
- I1 => wb_adr_o(1),
- I2 => wb_adr_o(0),
- I3 => \txr_reg[7]\(4),
- I4 => wb_adr_o(2),
- I5 => \wb_dat_o[4]_i_2_n_0\,
- O => D(4)
- );
-\wb_dat_o[4]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[4]\,
- I1 => \ctr_reg[7]\(4),
- I2 => wb_adr_o(1),
- I3 => Q(12),
- I4 => wb_adr_o(0),
- I5 => Q(4),
- O => \wb_dat_o[4]_i_2_n_0\
- );
-\wb_dat_o[5]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[5]\,
- I1 => \ctr_reg[7]\(5),
- I2 => wb_adr_o(1),
- I3 => Q(13),
- I4 => wb_adr_o(0),
- I5 => Q(5),
- O => \wb_dat_o[5]_i_2_n_0\
- );
-\wb_dat_o[6]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[6]\,
- I1 => \ctr_reg[7]\(6),
- I2 => wb_adr_o(1),
- I3 => Q(14),
- I4 => wb_adr_o(0),
- I5 => Q(6),
- O => \wb_dat_o[6]_i_2_n_0\
- );
-\wb_dat_o[7]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => dout(7),
- I1 => \ctr_reg[7]\(7),
- I2 => wb_adr_o(1),
- I3 => Q(15),
- I4 => wb_adr_o(0),
- I5 => Q(7),
- O => \wb_dat_o[7]_i_2_n_0\
- );
-\wb_dat_o_reg[0]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[0]_i_2_n_0\,
- I1 => \cr_reg[0]_0\,
- O => D(0),
- S => wb_adr_o(2)
- );
-\wb_dat_o_reg[1]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[1]_i_2_n_0\,
- I1 => \cr_reg[1]\,
- O => D(1),
- S => wb_adr_o(2)
- );
-\wb_dat_o_reg[5]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[5]_i_2_n_0\,
- I1 => \cr_reg[5]\,
- O => D(5),
- S => wb_adr_o(2)
- );
-\wb_dat_o_reg[7]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[7]_i_2_n_0\,
- I1 => \cr_reg[7]_0\,
- O => D(7),
- S => wb_adr_o(2)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_0_1_i2c_master_top is
- port (
- wb_ack_i : out STD_LOGIC;
- wb_rst_o : out STD_LOGIC;
- axi_int_o : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_stb_r_reg : out STD_LOGIC;
- \s_rdata_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \s_rdata_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
- s_stb_r_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
- wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_arvalid : in STD_LOGIC;
- wb_cyc_o : in STD_LOGIC;
- wb_we_o : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_we_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
- s_we_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \s_addr_reg[4]\ : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_i2c_master_top : entity is "i2c_master_top";
-end system_design_axi_wb_i2c_master_0_1_i2c_master_top;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_top is
- signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal ack_in : STD_LOGIC;
- signal al : STD_LOGIC;
- signal byte_ctrl_n_12 : STD_LOGIC;
- signal \cr[0]_i_1_n_0\ : STD_LOGIC;
- signal \cr[1]_i_1_n_0\ : STD_LOGIC;
- signal \cr[2]_i_1_n_0\ : STD_LOGIC;
- signal \cr[3]_i_1_n_0\ : STD_LOGIC;
- signal \cr_reg_n_0_[0]\ : STD_LOGIC;
- signal \cr_reg_n_0_[1]\ : STD_LOGIC;
- signal \cr_reg_n_0_[2]\ : STD_LOGIC;
- signal ctr : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \ctr_reg_n_0_[0]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[1]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[2]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[3]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[4]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[5]\ : STD_LOGIC;
- signal data0 : STD_LOGIC_VECTOR ( 13 downto 0 );
- signal ien : STD_LOGIC;
- signal irq_flag : STD_LOGIC;
- signal irq_flag1_out : STD_LOGIC;
- signal \prer[10]_i_1_n_0\ : STD_LOGIC;
- signal \prer[11]_i_1_n_0\ : STD_LOGIC;
- signal \prer[12]_i_1_n_0\ : STD_LOGIC;
- signal \prer[13]_i_1_n_0\ : STD_LOGIC;
- signal \prer[14]_i_1_n_0\ : STD_LOGIC;
- signal \prer[15]_i_2_n_0\ : STD_LOGIC;
- signal \prer[8]_i_1_n_0\ : STD_LOGIC;
- signal \prer[9]_i_1_n_0\ : STD_LOGIC;
- signal \prer_reg_n_0_[0]\ : STD_LOGIC;
- signal \prer_reg_n_0_[1]\ : STD_LOGIC;
- signal read : STD_LOGIC;
- signal rxack : STD_LOGIC;
- signal rxack_0 : STD_LOGIC;
- signal \st_irq_block.al_reg_n_0\ : STD_LOGIC;
- signal \st_irq_block.wb_inta_o_i_1_n_0\ : STD_LOGIC;
- signal start : STD_LOGIC;
- signal stop : STD_LOGIC;
- signal tip : STD_LOGIC;
- signal tip_1 : STD_LOGIC;
- signal txr : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \^wb_ack_i\ : STD_LOGIC;
- signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \wb_dat_o[0]_i_3_n_0\ : STD_LOGIC;
- signal \wb_dat_o[1]_i_3_n_0\ : STD_LOGIC;
- signal \wb_dat_o[5]_i_3_n_0\ : STD_LOGIC;
- signal \wb_dat_o[7]_i_3_n_0\ : STD_LOGIC;
- signal \^wb_rst_o\ : STD_LOGIC;
- signal write : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair26";
-begin
- Q(0) <= \^q\(0);
- wb_ack_i <= \^wb_ack_i\;
- wb_rst_o <= \^wb_rst_o\;
-byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
- port map (
- D(7 downto 0) => wb_dat_o(7 downto 0),
- E(0) => byte_ctrl_n_12,
- Q(15 downto 2) => data0(13 downto 0),
- Q(1) => \prer_reg_n_0_[1]\,
- Q(0) => \prer_reg_n_0_[0]\,
- ack_in => ack_in,
- al => al,
- \cr_reg[0]\ => \cr_reg_n_0_[0]\,
- \cr_reg[0]_0\ => \wb_dat_o[0]_i_3_n_0\,
- \cr_reg[1]\ => \wb_dat_o[1]_i_3_n_0\,
- \cr_reg[2]\ => \cr_reg_n_0_[2]\,
- \cr_reg[5]\ => \wb_dat_o[5]_i_3_n_0\,
- \cr_reg[7]\(3) => start,
- \cr_reg[7]\(2) => stop,
- \cr_reg[7]\(1) => read,
- \cr_reg[7]\(0) => write,
- \cr_reg[7]_0\ => \wb_dat_o[7]_i_3_n_0\,
- \ctr_reg[7]\(7) => \^q\(0),
- \ctr_reg[7]\(6) => ien,
- \ctr_reg[7]\(5) => \ctr_reg_n_0_[5]\,
- \ctr_reg[7]\(4) => \ctr_reg_n_0_[4]\,
- \ctr_reg[7]\(3) => \ctr_reg_n_0_[3]\,
- \ctr_reg[7]\(2) => \ctr_reg_n_0_[2]\,
- \ctr_reg[7]\(1) => \ctr_reg_n_0_[1]\,
- \ctr_reg[7]\(0) => \ctr_reg_n_0_[0]\,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- iack_o_reg => \^wb_ack_i\,
- iack_o_reg_0 => iack_o_reg_0,
- irq_flag => irq_flag,
- irq_flag1_out => irq_flag1_out,
- iscl_oen_reg => \^wb_rst_o\,
- rxack_0 => rxack_0,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- \st_irq_block.al_reg\ => \st_irq_block.al_reg_n_0\,
- \txr_reg[7]\(7 downto 0) => txr(7 downto 0),
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_we_o => wb_we_o
- );
-\cr[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8000FFFF80000000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(0),
- I2 => wb_we_o,
- I3 => \^wb_ack_i\,
- I4 => \s_addr_reg[4]\,
- I5 => \cr_reg_n_0_[0]\,
- O => \cr[0]_i_1_n_0\
- );
-\cr[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8000FFFF80000000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(1),
- I2 => wb_we_o,
- I3 => \^wb_ack_i\,
- I4 => \s_addr_reg[4]\,
- I5 => \cr_reg_n_0_[1]\,
- O => \cr[1]_i_1_n_0\
- );
-\cr[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8000FFFF80000000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(2),
- I2 => wb_we_o,
- I3 => \^wb_ack_i\,
- I4 => \s_addr_reg[4]\,
- I5 => \cr_reg_n_0_[2]\,
- O => \cr[2]_i_1_n_0\
- );
-\cr[3]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"C808"
- )
- port map (
- I0 => s00_axi_wdata(3),
- I1 => s00_axi_aresetn,
- I2 => iack_o_reg_0,
- I3 => ack_in,
- O => \cr[3]_i_1_n_0\
- );
-\cr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[0]_i_1_n_0\,
- Q => \cr_reg_n_0_[0]\
- );
-\cr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[1]_i_1_n_0\,
- Q => \cr_reg_n_0_[1]\
- );
-\cr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[2]_i_1_n_0\,
- Q => \cr_reg_n_0_[2]\
- );
-\cr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[3]_i_1_n_0\,
- Q => ack_in
- );
-\cr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(0),
- Q => write
- );
-\cr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(1),
- Q => read
- );
-\cr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(2),
- Q => stop
- );
-\cr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(3),
- Q => start
- );
-\ctr[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(0),
- O => ctr(0)
- );
-\ctr[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(1),
- O => ctr(1)
- );
-\ctr[2]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(2),
- O => ctr(2)
- );
-\ctr[3]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(3),
- O => ctr(3)
- );
-\ctr[4]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(4),
- O => ctr(4)
- );
-\ctr[5]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(5),
- O => ctr(5)
- );
-\ctr[6]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(6),
- O => ctr(6)
- );
-\ctr[7]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(7),
- O => ctr(7)
- );
-\ctr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(0),
- Q => \ctr_reg_n_0_[0]\
- );
-\ctr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(1),
- Q => \ctr_reg_n_0_[1]\
- );
-\ctr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(2),
- Q => \ctr_reg_n_0_[2]\
- );
-\ctr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(3),
- Q => \ctr_reg_n_0_[3]\
- );
-\ctr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(4),
- Q => \ctr_reg_n_0_[4]\
- );
-\ctr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(5),
- Q => \ctr_reg_n_0_[5]\
- );
-\ctr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(6),
- Q => ien
- );
-\ctr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(7),
- Q => \^q\(0)
- );
-iack_o_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_stb_r_reg_0,
- Q => \^wb_ack_i\,
- R => '0'
- );
-\prer[10]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(2),
- I1 => s00_axi_aresetn,
- O => \prer[10]_i_1_n_0\
- );
-\prer[11]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(3),
- I1 => s00_axi_aresetn,
- O => \prer[11]_i_1_n_0\
- );
-\prer[12]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(4),
- I1 => s00_axi_aresetn,
- O => \prer[12]_i_1_n_0\
- );
-\prer[13]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(5),
- I1 => s00_axi_aresetn,
- O => \prer[13]_i_1_n_0\
- );
-\prer[14]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(6),
- I1 => s00_axi_aresetn,
- O => \prer[14]_i_1_n_0\
- );
-\prer[15]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(7),
- I1 => s00_axi_aresetn,
- O => \prer[15]_i_2_n_0\
- );
-\prer[8]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(0),
- I1 => s00_axi_aresetn,
- O => \prer[8]_i_1_n_0\
- );
-\prer[9]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(1),
- I1 => s00_axi_aresetn,
- O => \prer[9]_i_1_n_0\
- );
-\prer_reg[0]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[8]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => \prer_reg_n_0_[0]\
- );
-\prer_reg[10]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[10]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(8)
- );
-\prer_reg[11]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[11]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(9)
- );
-\prer_reg[12]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[12]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(10)
- );
-\prer_reg[13]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[13]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(11)
- );
-\prer_reg[14]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[14]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(12)
- );
-\prer_reg[15]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[15]_i_2_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(13)
- );
-\prer_reg[1]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[9]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => \prer_reg_n_0_[1]\
- );
-\prer_reg[2]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[10]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(0)
- );
-\prer_reg[3]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[11]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(1)
- );
-\prer_reg[4]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[12]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(2)
- );
-\prer_reg[5]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[13]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(3)
- );
-\prer_reg[6]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[14]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(4)
- );
-\prer_reg[7]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[15]_i_2_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(5)
- );
-\prer_reg[8]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[8]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(6)
- );
-\prer_reg[9]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[9]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(7)
- );
-\s_rdata[7]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \^wb_ack_i\,
- I1 => wb_we_o,
- O => \s_rdata_reg[0]\(0)
- );
-s_stb_r_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"EFEE"
- )
- port map (
- I0 => s00_axi_awvalid,
- I1 => s00_axi_arvalid,
- I2 => \^wb_ack_i\,
- I3 => wb_cyc_o,
- O => s_stb_r_reg
- );
-\st_irq_block.al_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => al,
- Q => \st_irq_block.al_reg_n_0\
- );
-\st_irq_block.irq_flag_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => irq_flag1_out,
- Q => irq_flag
- );
-\st_irq_block.rxack_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => rxack_0,
- Q => rxack
- );
-\st_irq_block.tip_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"A8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => write,
- I2 => read,
- O => tip_1
- );
-\st_irq_block.tip_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => tip_1,
- Q => tip
- );
-\st_irq_block.wb_inta_o_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"80"
- )
- port map (
- I0 => irq_flag,
- I1 => s00_axi_aresetn,
- I2 => ien,
- O => \st_irq_block.wb_inta_o_i_1_n_0\
- );
-\st_irq_block.wb_inta_o_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \st_irq_block.wb_inta_o_i_1_n_0\,
- Q => axi_int_o
- );
-\txr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(0),
- Q => txr(0)
- );
-\txr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(1),
- Q => txr(1)
- );
-\txr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(2),
- Q => txr(2)
- );
-\txr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(3),
- Q => txr(3)
- );
-\txr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(4),
- Q => txr(4)
- );
-\txr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(5),
- Q => txr(5)
- );
-\txr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(6),
- Q => txr(6)
- );
-\txr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(7),
- Q => txr(7)
- );
-\wb_dat_o[0]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \cr_reg_n_0_[0]\,
- I1 => wb_adr_o(1),
- I2 => txr(0),
- I3 => wb_adr_o(0),
- I4 => irq_flag,
- O => \wb_dat_o[0]_i_3_n_0\
- );
-\wb_dat_o[1]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \cr_reg_n_0_[1]\,
- I1 => wb_adr_o(1),
- I2 => txr(1),
- I3 => wb_adr_o(0),
- I4 => tip,
- O => \wb_dat_o[1]_i_3_n_0\
- );
-\wb_dat_o[5]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => read,
- I1 => wb_adr_o(1),
- I2 => txr(5),
- I3 => wb_adr_o(0),
- I4 => \st_irq_block.al_reg_n_0\,
- O => \wb_dat_o[5]_i_3_n_0\
- );
-\wb_dat_o[7]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => start,
- I1 => wb_adr_o(1),
- I2 => txr(7),
- I3 => wb_adr_o(0),
- I4 => rxack,
- O => \wb_dat_o[7]_i_3_n_0\
- );
-\wb_dat_o_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(0),
- Q => \s_rdata_reg[7]\(0),
- R => '0'
- );
-\wb_dat_o_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(1),
- Q => \s_rdata_reg[7]\(1),
- R => '0'
- );
-\wb_dat_o_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(2),
- Q => \s_rdata_reg[7]\(2),
- R => '0'
- );
-\wb_dat_o_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(3),
- Q => \s_rdata_reg[7]\(3),
- R => '0'
- );
-\wb_dat_o_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(4),
- Q => \s_rdata_reg[7]\(4),
- R => '0'
- );
-\wb_dat_o_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(5),
- Q => \s_rdata_reg[7]\(5),
- R => '0'
- );
-\wb_dat_o_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(6),
- Q => \s_rdata_reg[7]\(6),
- R => '0'
- );
-\wb_dat_o_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(7),
- Q => \s_rdata_reg[7]\(7),
- R => '0'
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master is
- port (
- i2c_scl_io : inout STD_LOGIC;
- i2c_sda_io : inout STD_LOGIC;
- axi_int_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_bvalid : out STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_rvalid : out STD_LOGIC;
- s00_axi_rready : in STD_LOGIC
- );
- attribute C_S00_AXI_ADDR_WIDTH : integer;
- attribute C_S00_AXI_ADDR_WIDTH of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master : entity is 32;
- attribute C_S00_AXI_DATA_WIDTH : integer;
- attribute C_S00_AXI_DATA_WIDTH of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master : entity is 32;
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master : entity is "axi_wb_i2c_master";
-end system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master is
- signal \<const0>\ : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_11 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_12 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_13 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_14 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_15 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_16 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_17 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_18 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_19 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_21 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_7 : STD_LOGIC;
- signal cmp_i2c_master_top_n_4 : STD_LOGIC;
- signal cmp_i2c_master_top_n_5 : STD_LOGIC;
- signal ena : STD_LOGIC;
- signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \^s00_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal wb_ack_i : STD_LOGIC;
- signal wb_adr_o : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal wb_cyc_o : STD_LOGIC;
- signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal wb_rst_o : STD_LOGIC;
- signal wb_we_o : STD_LOGIC;
-begin
- s00_axi_bresp(1) <= \^s00_axi_bresp\(1);
- s00_axi_bresp(0) <= \<const0>\;
- s00_axi_rdata(31) <= \<const0>\;
- s00_axi_rdata(30) <= \<const0>\;
- s00_axi_rdata(29) <= \<const0>\;
- s00_axi_rdata(28) <= \<const0>\;
- s00_axi_rdata(27) <= \<const0>\;
- s00_axi_rdata(26) <= \<const0>\;
- s00_axi_rdata(25) <= \<const0>\;
- s00_axi_rdata(24) <= \<const0>\;
- s00_axi_rdata(23) <= \<const0>\;
- s00_axi_rdata(22) <= \<const0>\;
- s00_axi_rdata(21) <= \<const0>\;
- s00_axi_rdata(20) <= \<const0>\;
- s00_axi_rdata(19) <= \<const0>\;
- s00_axi_rdata(18) <= \<const0>\;
- s00_axi_rdata(17) <= \<const0>\;
- s00_axi_rdata(16) <= \<const0>\;
- s00_axi_rdata(15) <= \<const0>\;
- s00_axi_rdata(14) <= \<const0>\;
- s00_axi_rdata(13) <= \<const0>\;
- s00_axi_rdata(12) <= \<const0>\;
- s00_axi_rdata(11) <= \<const0>\;
- s00_axi_rdata(10) <= \<const0>\;
- s00_axi_rdata(9) <= \<const0>\;
- s00_axi_rdata(8) <= \<const0>\;
- s00_axi_rdata(7 downto 0) <= \^s00_axi_rdata\(7 downto 0);
- s00_axi_rresp(1) <= \<const0>\;
- s00_axi_rresp(0) <= \<const0>\;
-GND: unisim.vcomponents.GND
- port map (
- G => \<const0>\
- );
-cmp_axis_wbm_bridge: entity work.system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge
- port map (
- D(3) => cmp_axis_wbm_bridge_n_12,
- D(2) => cmp_axis_wbm_bridge_n_13,
- D(1) => cmp_axis_wbm_bridge_n_14,
- D(0) => cmp_axis_wbm_bridge_n_15,
- E(0) => cmp_axis_wbm_bridge_n_11,
- Q(0) => ena,
- \cr_reg[2]\ => cmp_axis_wbm_bridge_n_7,
- \cr_reg[4]\ => cmp_axis_wbm_bridge_n_16,
- \ctr_reg[0]\(0) => cmp_axis_wbm_bridge_n_19,
- iack_o_reg => cmp_axis_wbm_bridge_n_21,
- iack_o_reg_0 => cmp_i2c_master_top_n_4,
- iack_o_reg_1(0) => cmp_i2c_master_top_n_5,
- \prer_reg[8]\(1) => cmp_axis_wbm_bridge_n_17,
- \prer_reg[8]\(0) => cmp_axis_wbm_bridge_n_18,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_araddr(2 downto 0) => s00_axi_araddr(4 downto 2),
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arready => s00_axi_arready,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awaddr(2 downto 0) => s00_axi_awaddr(4 downto 2),
- s00_axi_awready => s00_axi_awready,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_bready => s00_axi_bready,
- s00_axi_bresp(0) => \^s00_axi_bresp\(1),
- s00_axi_bvalid => s00_axi_bvalid,
- s00_axi_rdata(7 downto 0) => \^s00_axi_rdata\(7 downto 0),
- s00_axi_rready => s00_axi_rready,
- s00_axi_rvalid => s00_axi_rvalid,
- s00_axi_wdata(3 downto 0) => s00_axi_wdata(7 downto 4),
- s00_axi_wready => s00_axi_wready,
- s00_axi_wvalid => s00_axi_wvalid,
- wb_ack_i => wb_ack_i,
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_cyc_o => wb_cyc_o,
- \wb_dat_o_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
- wb_rst_o => wb_rst_o,
- wb_we_o => wb_we_o
- );
-cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_top
- port map (
- D(3) => cmp_axis_wbm_bridge_n_12,
- D(2) => cmp_axis_wbm_bridge_n_13,
- D(1) => cmp_axis_wbm_bridge_n_14,
- D(0) => cmp_axis_wbm_bridge_n_15,
- E(1) => cmp_axis_wbm_bridge_n_17,
- E(0) => cmp_axis_wbm_bridge_n_18,
- Q(0) => ena,
- axi_int_o => axi_int_o,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- iack_o_reg_0 => cmp_axis_wbm_bridge_n_16,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_wdata(7 downto 0) => s00_axi_wdata(7 downto 0),
- \s_addr_reg[4]\ => cmp_axis_wbm_bridge_n_7,
- \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_5,
- \s_rdata_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
- s_stb_r_reg => cmp_i2c_master_top_n_4,
- s_stb_r_reg_0 => cmp_axis_wbm_bridge_n_21,
- s_we_r_reg(0) => cmp_axis_wbm_bridge_n_19,
- s_we_r_reg_0(0) => cmp_axis_wbm_bridge_n_11,
- wb_ack_i => wb_ack_i,
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_cyc_o => wb_cyc_o,
- wb_rst_o => wb_rst_o,
- wb_we_o => wb_we_o
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_0_1 is
- port (
- i2c_scl_io : inout STD_LOGIC;
- i2c_sda_io : inout STD_LOGIC;
- axi_int_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_bvalid : out STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_rvalid : out STD_LOGIC;
- s00_axi_rready : in STD_LOGIC
- );
- attribute NotValidForBitStream : boolean;
- attribute NotValidForBitStream of system_design_axi_wb_i2c_master_0_1 : entity is true;
- attribute CHECK_LICENSE_TYPE : string;
- attribute CHECK_LICENSE_TYPE of system_design_axi_wb_i2c_master_0_1 : entity is "system_design_axi_wb_i2c_master_0_1,axi_wb_i2c_master,{}";
- attribute downgradeipidentifiedwarnings : string;
- attribute downgradeipidentifiedwarnings of system_design_axi_wb_i2c_master_0_1 : entity is "yes";
- attribute x_core_info : string;
- attribute x_core_info of system_design_axi_wb_i2c_master_0_1 : entity is "axi_wb_i2c_master,Vivado 2016.2";
-end system_design_axi_wb_i2c_master_0_1;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1 is
- attribute C_S00_AXI_ADDR_WIDTH : integer;
- attribute C_S00_AXI_ADDR_WIDTH of U0 : label is 32;
- attribute C_S00_AXI_DATA_WIDTH : integer;
- attribute C_S00_AXI_DATA_WIDTH of U0 : label is 32;
-begin
-U0: entity work.system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
- port map (
- axi_int_o => axi_int_o,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_araddr(31 downto 0) => s00_axi_araddr(31 downto 0),
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arprot(2 downto 0) => s00_axi_arprot(2 downto 0),
- s00_axi_arready => s00_axi_arready,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awaddr(31 downto 0) => s00_axi_awaddr(31 downto 0),
- s00_axi_awprot(2 downto 0) => s00_axi_awprot(2 downto 0),
- s00_axi_awready => s00_axi_awready,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_bready => s00_axi_bready,
- s00_axi_bresp(1 downto 0) => s00_axi_bresp(1 downto 0),
- s00_axi_bvalid => s00_axi_bvalid,
- s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
- s00_axi_rready => s00_axi_rready,
- s00_axi_rresp(1 downto 0) => s00_axi_rresp(1 downto 0),
- s00_axi_rvalid => s00_axi_rvalid,
- s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
- s00_axi_wready => s00_axi_wready,
- s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
- s00_axi_wvalid => s00_axi_wvalid
- );
-end STRUCTURE;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd
index 3a78ac8b44fc12371e56cb3d614e9f2470ce763f..3fd151b77b6c7a30a7263e0fe7e59e97cb1aa41c 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.1
--- IP Revision: 5
+-- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.2
+-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
deleted file mode 100644
index cc50b9b15665f9a734a8c241e70e78823bf5bc9d..0000000000000000000000000000000000000000
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
+++ /dev/null
@@ -1,4068 +0,0 @@
-// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Tue Jun 20 20:06:00 2017
-// Host : lapte24154 running 64-bit openSUSE Leap 42.2
-// Command : write_verilog -force -mode funcsim
-// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
-// Design : system_design_axi_wb_i2c_master_2_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z030ffg676-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "system_design_axi_wb_i2c_master_2_0,axi_wb_i2c_master,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_wb_i2c_master,Vivado 2016.2" *)
-(* NotValidForBitStream *)
-module system_design_axi_wb_i2c_master_2_0
- (i2c_scl_io,
- i2c_sda_io,
- axi_int_o,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_awaddr,
- s00_axi_awprot,
- s00_axi_awvalid,
- s00_axi_awready,
- s00_axi_wdata,
- s00_axi_wstrb,
- s00_axi_wvalid,
- s00_axi_wready,
- s00_axi_bresp,
- s00_axi_bvalid,
- s00_axi_bready,
- s00_axi_araddr,
- s00_axi_arprot,
- s00_axi_arvalid,
- s00_axi_arready,
- s00_axi_rdata,
- s00_axi_rresp,
- s00_axi_rvalid,
- s00_axi_rready);
- inout i2c_scl_io;
- inout i2c_sda_io;
- output axi_int_o;
- (* x_interface_info = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *) input s00_axi_aclk;
- (* x_interface_info = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *) input s00_axi_aresetn;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *) input [31:0]s00_axi_awaddr;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *) input [2:0]s00_axi_awprot;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *) input s00_axi_awvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *) output s00_axi_awready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *) input [31:0]s00_axi_wdata;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *) input [3:0]s00_axi_wstrb;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *) input s00_axi_wvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *) output s00_axi_wready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *) output [1:0]s00_axi_bresp;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *) output s00_axi_bvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *) input s00_axi_bready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *) input [31:0]s00_axi_araddr;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *) input [2:0]s00_axi_arprot;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *) input s00_axi_arvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *) output s00_axi_arready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *) output [31:0]s00_axi_rdata;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *) output [1:0]s00_axi_rresp;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *) output s00_axi_rvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *) input s00_axi_rready;
-
- wire axi_int_o;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire s00_axi_aclk;
- wire [31:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire [2:0]s00_axi_arprot;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [31:0]s00_axi_awaddr;
- wire [2:0]s00_axi_awprot;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [1:0]s00_axi_bresp;
- wire s00_axi_bvalid;
- wire [31:0]s00_axi_rdata;
- wire s00_axi_rready;
- wire [1:0]s00_axi_rresp;
- wire s00_axi_rvalid;
- wire [31:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire [3:0]s00_axi_wstrb;
- wire s00_axi_wvalid;
-
- (* C_S00_AXI_ADDR_WIDTH = "32" *)
- (* C_S00_AXI_DATA_WIDTH = "32" *)
- system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master U0
- (.axi_int_o(axi_int_o),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_araddr(s00_axi_araddr),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arprot(s00_axi_arprot),
- .s00_axi_arready(s00_axi_arready),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awaddr(s00_axi_awaddr),
- .s00_axi_awprot(s00_axi_awprot),
- .s00_axi_awready(s00_axi_awready),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_bready(s00_axi_bready),
- .s00_axi_bresp(s00_axi_bresp),
- .s00_axi_bvalid(s00_axi_bvalid),
- .s00_axi_rdata(s00_axi_rdata),
- .s00_axi_rready(s00_axi_rready),
- .s00_axi_rresp(s00_axi_rresp),
- .s00_axi_rvalid(s00_axi_rvalid),
- .s00_axi_wdata(s00_axi_wdata),
- .s00_axi_wready(s00_axi_wready),
- .s00_axi_wstrb(s00_axi_wstrb),
- .s00_axi_wvalid(s00_axi_wvalid));
-endmodule
-
-(* C_S00_AXI_ADDR_WIDTH = "32" *) (* C_S00_AXI_DATA_WIDTH = "32" *) (* ORIG_REF_NAME = "axi_wb_i2c_master" *)
-module system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
- (i2c_scl_io,
- i2c_sda_io,
- axi_int_o,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_awaddr,
- s00_axi_awprot,
- s00_axi_awvalid,
- s00_axi_awready,
- s00_axi_wdata,
- s00_axi_wstrb,
- s00_axi_wvalid,
- s00_axi_wready,
- s00_axi_bresp,
- s00_axi_bvalid,
- s00_axi_bready,
- s00_axi_araddr,
- s00_axi_arprot,
- s00_axi_arvalid,
- s00_axi_arready,
- s00_axi_rdata,
- s00_axi_rresp,
- s00_axi_rvalid,
- s00_axi_rready);
- inout i2c_scl_io;
- inout i2c_sda_io;
- output axi_int_o;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [31:0]s00_axi_awaddr;
- input [2:0]s00_axi_awprot;
- input s00_axi_awvalid;
- output s00_axi_awready;
- input [31:0]s00_axi_wdata;
- input [3:0]s00_axi_wstrb;
- input s00_axi_wvalid;
- output s00_axi_wready;
- output [1:0]s00_axi_bresp;
- output s00_axi_bvalid;
- input s00_axi_bready;
- input [31:0]s00_axi_araddr;
- input [2:0]s00_axi_arprot;
- input s00_axi_arvalid;
- output s00_axi_arready;
- output [31:0]s00_axi_rdata;
- output [1:0]s00_axi_rresp;
- output s00_axi_rvalid;
- input s00_axi_rready;
-
- wire \<const0> ;
- wire axi_int_o;
- wire cmp_axis_wbm_bridge_n_11;
- wire cmp_axis_wbm_bridge_n_12;
- wire cmp_axis_wbm_bridge_n_13;
- wire cmp_axis_wbm_bridge_n_14;
- wire cmp_axis_wbm_bridge_n_15;
- wire cmp_axis_wbm_bridge_n_16;
- wire cmp_axis_wbm_bridge_n_17;
- wire cmp_axis_wbm_bridge_n_18;
- wire cmp_axis_wbm_bridge_n_19;
- wire cmp_axis_wbm_bridge_n_21;
- wire cmp_axis_wbm_bridge_n_7;
- wire cmp_i2c_master_top_n_4;
- wire cmp_i2c_master_top_n_5;
- wire ena;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire s00_axi_aclk;
- wire [31:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [31:0]s00_axi_awaddr;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [1:1]\^s00_axi_bresp ;
- wire s00_axi_bvalid;
- wire [7:0]\^s00_axi_rdata ;
- wire s00_axi_rready;
- wire s00_axi_rvalid;
- wire [31:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire s00_axi_wvalid;
- wire wb_ack_i;
- wire [2:0]wb_adr_o;
- wire wb_cyc_o;
- wire [7:0]wb_dat_o;
- wire wb_rst_o;
- wire wb_we_o;
-
- assign s00_axi_bresp[1] = \^s00_axi_bresp [1];
- assign s00_axi_bresp[0] = \<const0> ;
- assign s00_axi_rdata[31] = \<const0> ;
- assign s00_axi_rdata[30] = \<const0> ;
- assign s00_axi_rdata[29] = \<const0> ;
- assign s00_axi_rdata[28] = \<const0> ;
- assign s00_axi_rdata[27] = \<const0> ;
- assign s00_axi_rdata[26] = \<const0> ;
- assign s00_axi_rdata[25] = \<const0> ;
- assign s00_axi_rdata[24] = \<const0> ;
- assign s00_axi_rdata[23] = \<const0> ;
- assign s00_axi_rdata[22] = \<const0> ;
- assign s00_axi_rdata[21] = \<const0> ;
- assign s00_axi_rdata[20] = \<const0> ;
- assign s00_axi_rdata[19] = \<const0> ;
- assign s00_axi_rdata[18] = \<const0> ;
- assign s00_axi_rdata[17] = \<const0> ;
- assign s00_axi_rdata[16] = \<const0> ;
- assign s00_axi_rdata[15] = \<const0> ;
- assign s00_axi_rdata[14] = \<const0> ;
- assign s00_axi_rdata[13] = \<const0> ;
- assign s00_axi_rdata[12] = \<const0> ;
- assign s00_axi_rdata[11] = \<const0> ;
- assign s00_axi_rdata[10] = \<const0> ;
- assign s00_axi_rdata[9] = \<const0> ;
- assign s00_axi_rdata[8] = \<const0> ;
- assign s00_axi_rdata[7:0] = \^s00_axi_rdata [7:0];
- assign s00_axi_rresp[1] = \<const0> ;
- assign s00_axi_rresp[0] = \<const0> ;
- GND GND
- (.G(\<const0> ));
- system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge cmp_axis_wbm_bridge
- (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
- .E(cmp_axis_wbm_bridge_n_11),
- .Q(ena),
- .\cr_reg[2] (cmp_axis_wbm_bridge_n_7),
- .\cr_reg[4] (cmp_axis_wbm_bridge_n_16),
- .\ctr_reg[0] (cmp_axis_wbm_bridge_n_19),
- .iack_o_reg(cmp_axis_wbm_bridge_n_21),
- .iack_o_reg_0(cmp_i2c_master_top_n_4),
- .iack_o_reg_1(cmp_i2c_master_top_n_5),
- .\prer_reg[8] ({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_araddr(s00_axi_araddr[4:2]),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arready(s00_axi_arready),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awaddr(s00_axi_awaddr[4:2]),
- .s00_axi_awready(s00_axi_awready),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_bready(s00_axi_bready),
- .s00_axi_bresp(\^s00_axi_bresp ),
- .s00_axi_bvalid(s00_axi_bvalid),
- .s00_axi_rdata(\^s00_axi_rdata ),
- .s00_axi_rready(s00_axi_rready),
- .s00_axi_rvalid(s00_axi_rvalid),
- .s00_axi_wdata(s00_axi_wdata[7:4]),
- .s00_axi_wready(s00_axi_wready),
- .s00_axi_wvalid(s00_axi_wvalid),
- .wb_ack_i(wb_ack_i),
- .wb_adr_o(wb_adr_o),
- .wb_cyc_o(wb_cyc_o),
- .\wb_dat_o_reg[7] (wb_dat_o),
- .wb_rst_o(wb_rst_o),
- .wb_we_o(wb_we_o));
- system_design_axi_wb_i2c_master_2_0_i2c_master_top cmp_i2c_master_top
- (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
- .E({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
- .Q(ena),
- .axi_int_o(axi_int_o),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .iack_o_reg_0(cmp_axis_wbm_bridge_n_16),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_wdata(s00_axi_wdata[7:0]),
- .\s_addr_reg[4] (cmp_axis_wbm_bridge_n_7),
- .\s_rdata_reg[0] (cmp_i2c_master_top_n_5),
- .\s_rdata_reg[7] (wb_dat_o),
- .s_stb_r_reg(cmp_i2c_master_top_n_4),
- .s_stb_r_reg_0(cmp_axis_wbm_bridge_n_21),
- .s_we_r_reg(cmp_axis_wbm_bridge_n_19),
- .s_we_r_reg_0(cmp_axis_wbm_bridge_n_11),
- .wb_ack_i(wb_ack_i),
- .wb_adr_o(wb_adr_o),
- .wb_cyc_o(wb_cyc_o),
- .wb_rst_o(wb_rst_o),
- .wb_we_o(wb_we_o));
-endmodule
-
-(* ORIG_REF_NAME = "axis_wbm_bridge" *)
-module system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge
- (s00_axi_awready,
- s00_axi_wready,
- s00_axi_arready,
- wb_we_o,
- wb_cyc_o,
- s00_axi_bresp,
- s00_axi_bvalid,
- \cr_reg[2] ,
- wb_adr_o,
- E,
- D,
- \cr_reg[4] ,
- \prer_reg[8] ,
- \ctr_reg[0] ,
- s00_axi_rvalid,
- iack_o_reg,
- s00_axi_rdata,
- wb_rst_o,
- s00_axi_aclk,
- iack_o_reg_0,
- Q,
- s00_axi_aresetn,
- wb_ack_i,
- s00_axi_awvalid,
- s00_axi_arvalid,
- s00_axi_bready,
- s00_axi_rready,
- s00_axi_wvalid,
- s00_axi_wdata,
- s00_axi_araddr,
- s00_axi_awaddr,
- iack_o_reg_1,
- \wb_dat_o_reg[7] );
- output s00_axi_awready;
- output s00_axi_wready;
- output s00_axi_arready;
- output wb_we_o;
- output wb_cyc_o;
- output [0:0]s00_axi_bresp;
- output s00_axi_bvalid;
- output \cr_reg[2] ;
- output [2:0]wb_adr_o;
- output [0:0]E;
- output [3:0]D;
- output \cr_reg[4] ;
- output [1:0]\prer_reg[8] ;
- output [0:0]\ctr_reg[0] ;
- output s00_axi_rvalid;
- output iack_o_reg;
- output [7:0]s00_axi_rdata;
- input wb_rst_o;
- input s00_axi_aclk;
- input iack_o_reg_0;
- input [0:0]Q;
- input s00_axi_aresetn;
- input wb_ack_i;
- input s00_axi_awvalid;
- input s00_axi_arvalid;
- input s00_axi_bready;
- input s00_axi_rready;
- input s00_axi_wvalid;
- input [3:0]s00_axi_wdata;
- input [2:0]s00_axi_araddr;
- input [2:0]s00_axi_awaddr;
- input [0:0]iack_o_reg_1;
- input [7:0]\wb_dat_o_reg[7] ;
-
- wire [3:0]D;
- wire [0:0]E;
- wire [0:0]Q;
- wire \cr[2]_i_3_n_0 ;
- wire \cr_reg[2] ;
- wire \cr_reg[4] ;
- wire [0:0]\ctr_reg[0] ;
- wire iack_o_reg;
- wire iack_o_reg_0;
- wire [0:0]iack_o_reg_1;
- wire [1:0]\prer_reg[8] ;
- wire s00_axi_aclk;
- wire [2:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [2:0]s00_axi_awaddr;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [0:0]s00_axi_bresp;
- wire s00_axi_bvalid;
- wire [7:0]s00_axi_rdata;
- wire s00_axi_rready;
- wire s00_axi_rvalid;
- wire [3:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire s00_axi_wvalid;
- wire \s_addr[2]_i_1_n_0 ;
- wire \s_addr[3]_i_1_n_0 ;
- wire \s_addr[4]_i_1_n_0 ;
- wire s_arready_i_1_n_0;
- wire s_awready_i_1_n_0;
- wire \s_bresp[1]_i_1_n_0 ;
- wire s_bvalid;
- wire s_bvalid_i_1_n_0;
- wire s_rvalid;
- wire s_rvalid_i_1_n_0;
- wire s_we_r_i_1_n_0;
- wire s_wready_i_1_n_0;
- wire wb_ack_i;
- wire [2:0]wb_adr_o;
- wire wb_cyc_o;
- wire [7:0]\wb_dat_o_reg[7] ;
- wire wb_rst_o;
- wire wb_we_o;
-
- LUT6 #(
- .INIT(64'hFFFF0008FFFFFFFF))
- \cr[2]_i_2
- (.I0(wb_adr_o[2]),
- .I1(Q),
- .I2(wb_adr_o[1]),
- .I3(wb_adr_o[0]),
- .I4(\cr[2]_i_3_n_0 ),
- .I5(s00_axi_aresetn),
- .O(\cr_reg[2] ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT2 #(
- .INIT(4'h7))
- \cr[2]_i_3
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .O(\cr[2]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[4]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[0]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[0]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[5]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[1]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[1]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[6]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[2]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[2]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h8000))
- \cr[7]_i_2
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[3]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(D[3]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF7FFF))
- \cr[7]_i_3
- (.I0(wb_ack_i),
- .I1(wb_we_o),
- .I2(wb_adr_o[2]),
- .I3(Q),
- .I4(wb_adr_o[1]),
- .I5(wb_adr_o[0]),
- .O(\cr_reg[4] ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h0080FFFF))
- \ctr[7]_i_1
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .I2(wb_adr_o[1]),
- .I3(wb_adr_o[0]),
- .I4(s00_axi_aresetn),
- .O(\ctr_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT2 #(
- .INIT(4'h2))
- iack_o_i_1
- (.I0(wb_cyc_o),
- .I1(wb_ack_i),
- .O(iack_o_reg));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h75555555))
- \prer[15]_i_1
- (.I0(s00_axi_aresetn),
- .I1(wb_adr_o[1]),
- .I2(wb_ack_i),
- .I3(wb_we_o),
- .I4(wb_adr_o[0]),
- .O(\prer_reg[8] [1]));
- LUT6 #(
- .INIT(64'h5555555557555555))
- \prer[7]_i_1
- (.I0(s00_axi_aresetn),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[2]),
- .I3(wb_ack_i),
- .I4(wb_we_o),
- .I5(wb_adr_o[0]),
- .O(\prer_reg[8] [0]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT2 #(
- .INIT(4'h8))
- s00_axi_bvalid_INST_0
- (.I0(s_bvalid),
- .I1(wb_we_o),
- .O(s00_axi_bvalid));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT2 #(
- .INIT(4'h2))
- s00_axi_rvalid_INST_0
- (.I0(s_rvalid),
- .I1(wb_we_o),
- .O(s00_axi_rvalid));
- LUT5 #(
- .INIT(32'hAACFAAC0))
- \s_addr[2]_i_1
- (.I0(s00_axi_araddr[0]),
- .I1(s00_axi_awaddr[0]),
- .I2(s00_axi_awvalid),
- .I3(s00_axi_arvalid),
- .I4(wb_adr_o[0]),
- .O(\s_addr[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hAACFAAC0))
- \s_addr[3]_i_1
- (.I0(s00_axi_araddr[1]),
- .I1(s00_axi_awaddr[1]),
- .I2(s00_axi_awvalid),
- .I3(s00_axi_arvalid),
- .I4(wb_adr_o[1]),
- .O(\s_addr[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hAACFAAC0))
- \s_addr[4]_i_1
- (.I0(s00_axi_araddr[2]),
- .I1(s00_axi_awaddr[2]),
- .I2(s00_axi_awvalid),
- .I3(s00_axi_arvalid),
- .I4(wb_adr_o[2]),
- .O(\s_addr[4]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_addr_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_addr[2]_i_1_n_0 ),
- .Q(wb_adr_o[0]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_addr_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_addr[3]_i_1_n_0 ),
- .Q(wb_adr_o[1]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_addr_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_addr[4]_i_1_n_0 ),
- .Q(wb_adr_o[2]),
- .R(wb_rst_o));
- LUT2 #(
- .INIT(4'h2))
- s_arready_i_1
- (.I0(s00_axi_arvalid),
- .I1(s00_axi_arready),
- .O(s_arready_i_1_n_0));
- FDRE s_arready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_arready_i_1_n_0),
- .Q(s00_axi_arready),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'h08))
- s_awready_i_1
- (.I0(s00_axi_wvalid),
- .I1(s00_axi_awvalid),
- .I2(s00_axi_awready),
- .O(s_awready_i_1_n_0));
- FDRE s_awready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_awready_i_1_n_0),
- .Q(s00_axi_awready),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'hFF7F0000))
- \s_bresp[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(wb_we_o),
- .I2(wb_ack_i),
- .I3(s_bvalid),
- .I4(s00_axi_bresp),
- .O(\s_bresp[1]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_bresp_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_bresp[1]_i_1_n_0 ),
- .Q(s00_axi_bresp),
- .R(1'b0));
- LUT4 #(
- .INIT(16'h0F88))
- s_bvalid_i_1
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .I2(s00_axi_bready),
- .I3(s_bvalid),
- .O(s_bvalid_i_1_n_0));
- FDRE s_bvalid_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_bvalid_i_1_n_0),
- .Q(s_bvalid),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[0]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [0]),
- .Q(s00_axi_rdata[0]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[1]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [1]),
- .Q(s00_axi_rdata[1]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[2]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [2]),
- .Q(s00_axi_rdata[2]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[3]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [3]),
- .Q(s00_axi_rdata[3]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[4]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [4]),
- .Q(s00_axi_rdata[4]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[5]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [5]),
- .Q(s00_axi_rdata[5]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[6]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [6]),
- .Q(s00_axi_rdata[6]),
- .R(wb_rst_o));
- FDRE #(
- .INIT(1'b0))
- \s_rdata_reg[7]
- (.C(s00_axi_aclk),
- .CE(iack_o_reg_1),
- .D(\wb_dat_o_reg[7] [7]),
- .Q(s00_axi_rdata[7]),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT4 #(
- .INIT(16'h4F44))
- s_rvalid_i_1
- (.I0(s00_axi_rready),
- .I1(s_rvalid),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .O(s_rvalid_i_1_n_0));
- FDRE s_rvalid_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_rvalid_i_1_n_0),
- .Q(s_rvalid),
- .R(wb_rst_o));
- FDRE s_stb_r_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(iack_o_reg_0),
- .Q(wb_cyc_o),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h00E0))
- s_we_r_i_1
- (.I0(wb_we_o),
- .I1(s00_axi_awvalid),
- .I2(s00_axi_aresetn),
- .I3(s00_axi_arvalid),
- .O(s_we_r_i_1_n_0));
- FDRE s_we_r_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_we_r_i_1_n_0),
- .Q(wb_we_o),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'h08))
- s_wready_i_1
- (.I0(s00_axi_wvalid),
- .I1(s00_axi_awvalid),
- .I2(s00_axi_wready),
- .O(s_wready_i_1_n_0));
- FDRE s_wready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_wready_i_1_n_0),
- .Q(s00_axi_wready),
- .R(wb_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h8000FFFF))
- \txr[7]_i_1
- (.I0(wb_we_o),
- .I1(wb_ack_i),
- .I2(wb_adr_o[0]),
- .I3(wb_adr_o[1]),
- .I4(s00_axi_aresetn),
- .O(E));
-endmodule
-
-(* ORIG_REF_NAME = "i2c_master_bit_ctrl" *)
-module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
- (iscl_oen_reg_0,
- E,
- irq_flag1_out,
- al,
- D,
- \statemachine.core_cmd_reg[3] ,
- \statemachine.ld_reg ,
- \statemachine.core_txd_reg ,
- \statemachine.shift_reg ,
- \statemachine.host_ack_reg ,
- \statemachine.ack_out_reg ,
- \cr_reg[4] ,
- \sr_reg[0] ,
- \FSM_sequential_statemachine.c_state_reg[2] ,
- i2c_sda_io,
- i2c_scl_io,
- s00_axi_aclk,
- s00_axi_aresetn,
- out,
- \cr_reg[0] ,
- cmd_ack,
- irq_flag,
- Q,
- \ctr_reg[7] ,
- \statemachine.core_cmd_reg[3]_0 ,
- \st_irq_block.al_reg ,
- \cr_reg[7] ,
- wb_adr_o,
- \sr_reg[6] ,
- \txr_reg[6] ,
- \FSM_sequential_statemachine.c_state_reg[1] ,
- core_cmd,
- \FSM_sequential_statemachine.c_state_reg[1]_0 ,
- cnt_done,
- ack_out,
- iack_o_reg,
- wb_we_o,
- iack_o_reg_0,
- \statemachine.ld_reg_0 ,
- \FSM_sequential_statemachine.c_state_reg[1]_1 ,
- \FSM_sequential_statemachine.c_state_reg[1]_2 ,
- ack_in,
- \sr_reg[7] ,
- \cr_reg[7]_0 ,
- \statemachine.core_txd_reg_0 );
- output iscl_oen_reg_0;
- output [0:0]E;
- output irq_flag1_out;
- output al;
- output [0:0]D;
- output [3:0]\statemachine.core_cmd_reg[3] ;
- output \statemachine.ld_reg ;
- output \statemachine.core_txd_reg ;
- output \statemachine.shift_reg ;
- output \statemachine.host_ack_reg ;
- output \statemachine.ack_out_reg ;
- output [0:0]\cr_reg[4] ;
- output [0:0]\sr_reg[0] ;
- output [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [2:0]out;
- input \cr_reg[0] ;
- input cmd_ack;
- input irq_flag;
- input [15:0]Q;
- input [0:0]\ctr_reg[7] ;
- input [3:0]\statemachine.core_cmd_reg[3]_0 ;
- input \st_irq_block.al_reg ;
- input [3:0]\cr_reg[7] ;
- input [2:0]wb_adr_o;
- input \sr_reg[6] ;
- input [1:0]\txr_reg[6] ;
- input \FSM_sequential_statemachine.c_state_reg[1] ;
- input [0:0]core_cmd;
- input \FSM_sequential_statemachine.c_state_reg[1]_0 ;
- input cnt_done;
- input ack_out;
- input iack_o_reg;
- input wb_we_o;
- input iack_o_reg_0;
- input \statemachine.ld_reg_0 ;
- input \FSM_sequential_statemachine.c_state_reg[1]_1 ;
- input \FSM_sequential_statemachine.c_state_reg[1]_2 ;
- input ack_in;
- input [0:0]\sr_reg[7] ;
- input \cr_reg[7]_0 ;
- input \statemachine.core_txd_reg_0 ;
-
- wire [0:0]D;
- wire [0:0]E;
- wire \FSM_sequential_c_state[0]_i_1_n_0 ;
- wire \FSM_sequential_c_state[0]_i_2_n_0 ;
- wire \FSM_sequential_c_state[1]_i_1_n_0 ;
- wire \FSM_sequential_c_state[1]_i_2_n_0 ;
- wire \FSM_sequential_c_state[1]_i_3_n_0 ;
- wire \FSM_sequential_c_state[2]_i_1_n_0 ;
- wire \FSM_sequential_c_state[2]_i_2_n_0 ;
- wire \FSM_sequential_c_state[3]_i_1_n_0 ;
- wire \FSM_sequential_c_state[3]_i_2_n_0 ;
- wire \FSM_sequential_c_state[3]_i_3_n_0 ;
- wire \FSM_sequential_c_state[4]_i_1_n_0 ;
- wire \FSM_sequential_c_state[4]_i_2_n_0 ;
- wire \FSM_sequential_c_state[4]_i_3_n_0 ;
- wire \FSM_sequential_statemachine.c_state[2]_i_3_n_0 ;
- wire \FSM_sequential_statemachine.c_state_reg[1] ;
- wire \FSM_sequential_statemachine.c_state_reg[1]_0 ;
- wire \FSM_sequential_statemachine.c_state_reg[1]_1 ;
- wire \FSM_sequential_statemachine.c_state_reg[1]_2 ;
- wire [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
- wire [15:0]Q;
- wire ack_in;
- wire ack_out;
- wire al;
- wire \bus_status_ctrl.cSCL[0]_i_1_n_0 ;
- wire \bus_status_ctrl.cSCL[1]_i_1_n_0 ;
- wire \bus_status_ctrl.cSDA[0]_i_1_n_0 ;
- wire \bus_status_ctrl.cSDA[1]_i_1_n_0 ;
- wire \bus_status_ctrl.cSDA_reg_n_0_[1] ;
- wire \bus_status_ctrl.cmd_stop_i_1_n_0 ;
- wire \bus_status_ctrl.cmd_stop_i_2_n_0 ;
- wire \bus_status_ctrl.cmd_stop_reg_n_0 ;
- wire \bus_status_ctrl.dSCL_i_1_n_0 ;
- wire \bus_status_ctrl.dSDA_i_1_n_0 ;
- wire \bus_status_ctrl.dout_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL[0]_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL[1]_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL[2]_i_1_n_0 ;
- wire \bus_status_ctrl.fSCL_reg_n_0_[2] ;
- wire \bus_status_ctrl.fSDA[0]_i_1_n_0 ;
- wire \bus_status_ctrl.fSDA[1]_i_1_n_0 ;
- wire \bus_status_ctrl.fSDA[2]_i_1_n_0 ;
- wire \bus_status_ctrl.fSDA[2]_i_2_n_0 ;
- wire \bus_status_ctrl.fSDA_reg_n_0_[0] ;
- wire \bus_status_ctrl.fSDA_reg_n_0_[1] ;
- wire \bus_status_ctrl.fSDA_reg_n_0_[2] ;
- wire \bus_status_ctrl.filter_cnt[0]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[10]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[11]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[12]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_2_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_3_n_0 ;
- wire \bus_status_ctrl.filter_cnt[13]_i_4_n_0 ;
- wire \bus_status_ctrl.filter_cnt[1]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[2]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[3]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[4]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[5]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[6]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[7]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[8]_i_1_n_0 ;
- wire \bus_status_ctrl.filter_cnt[9]_i_1_n_0 ;
- wire \bus_status_ctrl.ial_i_2_n_0 ;
- wire \bus_status_ctrl.ial_i_3_n_0 ;
- wire \bus_status_ctrl.sSCL_i_1_n_0 ;
- wire \bus_status_ctrl.sSDA_i_1_n_0 ;
- wire \bus_status_ctrl.sta_condition_reg_n_0 ;
- wire \bus_status_ctrl.sto_condition_reg_n_0 ;
- (* RTL_KEEP = "yes" *) wire [4:0]c_state;
- wire clk_en;
- wire clk_en_i_2_n_0;
- wire clk_en_i_3_n_0;
- wire clk_en_i_4_n_0;
- wire clk_en_i_5_n_0;
- wire clk_en_i_6_n_0;
- wire cmd_ack;
- wire cmd_ack3_out;
- wire cmd_ack_i_2_n_0;
- wire cnt1;
- wire \cnt[0]_i_10_n_0 ;
- wire \cnt[0]_i_1_n_0 ;
- wire \cnt[0]_i_3_n_0 ;
- wire \cnt[0]_i_4_n_0 ;
- wire \cnt[0]_i_5_n_0 ;
- wire \cnt[0]_i_6_n_0 ;
- wire \cnt[0]_i_7_n_0 ;
- wire \cnt[0]_i_8_n_0 ;
- wire \cnt[0]_i_9_n_0 ;
- wire \cnt[12]_i_2_n_0 ;
- wire \cnt[12]_i_3_n_0 ;
- wire \cnt[12]_i_4_n_0 ;
- wire \cnt[12]_i_5_n_0 ;
- wire \cnt[12]_i_6_n_0 ;
- wire \cnt[12]_i_7_n_0 ;
- wire \cnt[12]_i_8_n_0 ;
- wire \cnt[4]_i_2_n_0 ;
- wire \cnt[4]_i_3_n_0 ;
- wire \cnt[4]_i_4_n_0 ;
- wire \cnt[4]_i_5_n_0 ;
- wire \cnt[4]_i_6_n_0 ;
- wire \cnt[4]_i_7_n_0 ;
- wire \cnt[4]_i_8_n_0 ;
- wire \cnt[4]_i_9_n_0 ;
- wire \cnt[8]_i_2_n_0 ;
- wire \cnt[8]_i_3_n_0 ;
- wire \cnt[8]_i_4_n_0 ;
- wire \cnt[8]_i_5_n_0 ;
- wire \cnt[8]_i_6_n_0 ;
- wire \cnt[8]_i_7_n_0 ;
- wire \cnt[8]_i_8_n_0 ;
- wire \cnt[8]_i_9_n_0 ;
- wire cnt_done;
- wire [15:0]cnt_reg;
- wire \cnt_reg[0]_i_2_n_0 ;
- wire \cnt_reg[0]_i_2_n_1 ;
- wire \cnt_reg[0]_i_2_n_2 ;
- wire \cnt_reg[0]_i_2_n_3 ;
- wire \cnt_reg[0]_i_2_n_4 ;
- wire \cnt_reg[0]_i_2_n_5 ;
- wire \cnt_reg[0]_i_2_n_6 ;
- wire \cnt_reg[0]_i_2_n_7 ;
- wire \cnt_reg[12]_i_1_n_1 ;
- wire \cnt_reg[12]_i_1_n_2 ;
- wire \cnt_reg[12]_i_1_n_3 ;
- wire \cnt_reg[12]_i_1_n_4 ;
- wire \cnt_reg[12]_i_1_n_5 ;
- wire \cnt_reg[12]_i_1_n_6 ;
- wire \cnt_reg[12]_i_1_n_7 ;
- wire \cnt_reg[4]_i_1_n_0 ;
- wire \cnt_reg[4]_i_1_n_1 ;
- wire \cnt_reg[4]_i_1_n_2 ;
- wire \cnt_reg[4]_i_1_n_3 ;
- wire \cnt_reg[4]_i_1_n_4 ;
- wire \cnt_reg[4]_i_1_n_5 ;
- wire \cnt_reg[4]_i_1_n_6 ;
- wire \cnt_reg[4]_i_1_n_7 ;
- wire \cnt_reg[8]_i_1_n_0 ;
- wire \cnt_reg[8]_i_1_n_1 ;
- wire \cnt_reg[8]_i_1_n_2 ;
- wire \cnt_reg[8]_i_1_n_3 ;
- wire \cnt_reg[8]_i_1_n_4 ;
- wire \cnt_reg[8]_i_1_n_5 ;
- wire \cnt_reg[8]_i_1_n_6 ;
- wire \cnt_reg[8]_i_1_n_7 ;
- wire core_ack;
- wire [0:0]core_cmd;
- wire core_rxd;
- wire core_txd;
- wire \cr_reg[0] ;
- wire [0:0]\cr_reg[4] ;
- wire [3:0]\cr_reg[7] ;
- wire \cr_reg[7]_0 ;
- wire [0:0]\ctr_reg[7] ;
- wire dSCL;
- wire dSDA;
- wire dscl_oen;
- wire [13:0]filter_cnt;
- wire i2c_al;
- wire i2c_busy;
- wire i2c_scl_io;
- wire i2c_scl_io_INST_0_i_1_n_0;
- wire i2c_sda_io;
- wire i2c_sda_io_INST_0_i_1_n_0;
- wire iack_o_reg;
- wire iack_o_reg_0;
- wire ial;
- wire ibusy;
- wire irq_flag;
- wire irq_flag1_out;
- wire iscl_oen;
- wire iscl_oen9_out__0;
- wire iscl_oen_i_1_n_0;
- wire iscl_oen_reg_0;
- wire isda_oen;
- wire isda_oen7_out__0;
- wire isda_oen_i_1_n_0;
- wire minusOp_carry__0_i_1_n_0;
- wire minusOp_carry__0_i_2_n_0;
- wire minusOp_carry__0_i_3_n_0;
- wire minusOp_carry__0_i_4_n_0;
- wire minusOp_carry__0_n_0;
- wire minusOp_carry__0_n_1;
- wire minusOp_carry__0_n_2;
- wire minusOp_carry__0_n_3;
- wire minusOp_carry__0_n_4;
- wire minusOp_carry__0_n_5;
- wire minusOp_carry__0_n_6;
- wire minusOp_carry__0_n_7;
- wire minusOp_carry__1_i_1_n_0;
- wire minusOp_carry__1_i_2_n_0;
- wire minusOp_carry__1_i_3_n_0;
- wire minusOp_carry__1_i_4_n_0;
- wire minusOp_carry__1_n_0;
- wire minusOp_carry__1_n_1;
- wire minusOp_carry__1_n_2;
- wire minusOp_carry__1_n_3;
- wire minusOp_carry__1_n_4;
- wire minusOp_carry__1_n_5;
- wire minusOp_carry__1_n_6;
- wire minusOp_carry__1_n_7;
- wire minusOp_carry__2_i_1_n_0;
- wire minusOp_carry__2_n_7;
- wire minusOp_carry_i_1_n_0;
- wire minusOp_carry_i_2_n_0;
- wire minusOp_carry_i_3_n_0;
- wire minusOp_carry_i_4_n_0;
- wire minusOp_carry_n_0;
- wire minusOp_carry_n_1;
- wire minusOp_carry_n_2;
- wire minusOp_carry_n_3;
- wire minusOp_carry_n_4;
- wire minusOp_carry_n_5;
- wire minusOp_carry_n_6;
- wire minusOp_carry_n_7;
- wire [2:0]out;
- wire [1:1]p_0_in;
- wire [1:1]p_0_in__0;
- wire [2:0]p_0_in__1;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire sSCL;
- wire sSDA;
- wire scl_padoen_o;
- wire sda_chk_i_1_n_0;
- wire sda_chk_reg_n_0;
- wire sda_padoen_o;
- wire slave_wait;
- wire slave_wait0;
- wire [0:0]\sr_reg[0] ;
- wire \sr_reg[6] ;
- wire [0:0]\sr_reg[7] ;
- wire \st_irq_block.al_reg ;
- wire sta_condition;
- wire \statemachine.ack_out_i_2_n_0 ;
- wire \statemachine.ack_out_reg ;
- wire [3:0]\statemachine.core_cmd_reg[3] ;
- wire [3:0]\statemachine.core_cmd_reg[3]_0 ;
- wire \statemachine.core_txd_reg ;
- wire \statemachine.core_txd_reg_0 ;
- wire \statemachine.host_ack_reg ;
- wire \statemachine.ld_reg ;
- wire \statemachine.ld_reg_0 ;
- wire \statemachine.shift_reg ;
- wire sto_condition;
- wire [1:0]\txr_reg[6] ;
- wire [2:0]wb_adr_o;
- wire \wb_dat_o[6]_i_3_n_0 ;
- wire wb_we_o;
- wire [3:3]\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED ;
- wire [3:0]NLW_minusOp_carry__2_CO_UNCONNECTED;
- wire [3:1]NLW_minusOp_carry__2_O_UNCONNECTED;
-
- LUT6 #(
- .INIT(64'h1111111111111110))
- \FSM_sequential_c_state[0]_i_1
- (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .I1(c_state[0]),
- .I2(c_state[2]),
- .I3(c_state[3]),
- .I4(\FSM_sequential_c_state[0]_i_2_n_0 ),
- .I5(c_state[4]),
- .O(\FSM_sequential_c_state[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hAAAAAABA))
- \FSM_sequential_c_state[0]_i_2
- (.I0(c_state[1]),
- .I1(\statemachine.core_cmd_reg[3]_0 [1]),
- .I2(\statemachine.core_cmd_reg[3]_0 [0]),
- .I3(\statemachine.core_cmd_reg[3]_0 [3]),
- .I4(\statemachine.core_cmd_reg[3]_0 [2]),
- .O(\FSM_sequential_c_state[0]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'h0400))
- \FSM_sequential_c_state[1]_i_1
- (.I0(i2c_al),
- .I1(s00_axi_aresetn),
- .I2(c_state[4]),
- .I3(\FSM_sequential_c_state[1]_i_2_n_0 ),
- .O(\FSM_sequential_c_state[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hEEEFEFFE44444444))
- \FSM_sequential_c_state[1]_i_2
- (.I0(c_state[0]),
- .I1(c_state[1]),
- .I2(\statemachine.core_cmd_reg[3]_0 [1]),
- .I3(\statemachine.core_cmd_reg[3]_0 [2]),
- .I4(\statemachine.core_cmd_reg[3]_0 [3]),
- .I5(\FSM_sequential_c_state[1]_i_3_n_0 ),
- .O(\FSM_sequential_c_state[1]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'h00001101))
- \FSM_sequential_c_state[1]_i_3
- (.I0(c_state[2]),
- .I1(c_state[1]),
- .I2(\statemachine.core_cmd_reg[3]_0 [0]),
- .I3(c_state[0]),
- .I4(c_state[3]),
- .O(\FSM_sequential_c_state[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0002A0A2AAAA0002))
- \FSM_sequential_c_state[2]_i_1
- (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
- .I1(c_state[3]),
- .I2(c_state[1]),
- .I3(\FSM_sequential_c_state[2]_i_2_n_0 ),
- .I4(c_state[2]),
- .I5(c_state[0]),
- .O(\FSM_sequential_c_state[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFEEF))
- \FSM_sequential_c_state[2]_i_2
- (.I0(c_state[0]),
- .I1(\statemachine.core_cmd_reg[3]_0 [3]),
- .I2(\statemachine.core_cmd_reg[3]_0 [1]),
- .I3(\statemachine.core_cmd_reg[3]_0 [2]),
- .I4(\statemachine.core_cmd_reg[3]_0 [0]),
- .O(\FSM_sequential_c_state[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0AA8A0A800A800A8))
- \FSM_sequential_c_state[3]_i_1
- (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
- .I1(\FSM_sequential_c_state[3]_i_3_n_0 ),
- .I2(c_state[3]),
- .I3(c_state[0]),
- .I4(c_state[2]),
- .I5(c_state[1]),
- .O(\FSM_sequential_c_state[3]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h04))
- \FSM_sequential_c_state[3]_i_2
- (.I0(c_state[4]),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .O(\FSM_sequential_c_state[3]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000006))
- \FSM_sequential_c_state[3]_i_3
- (.I0(\statemachine.core_cmd_reg[3]_0 [3]),
- .I1(\statemachine.core_cmd_reg[3]_0 [2]),
- .I2(\statemachine.core_cmd_reg[3]_0 [0]),
- .I3(\statemachine.core_cmd_reg[3]_0 [1]),
- .I4(c_state[1]),
- .I5(c_state[2]),
- .O(\FSM_sequential_c_state[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hBBBBBBBFAAAAAAAA))
- \FSM_sequential_c_state[4]_i_1
- (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .I1(c_state[4]),
- .I2(c_state[3]),
- .I3(c_state[1]),
- .I4(c_state[2]),
- .I5(clk_en),
- .O(\FSM_sequential_c_state[4]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000080FF8000))
- \FSM_sequential_c_state[4]_i_2
- (.I0(c_state[3]),
- .I1(c_state[1]),
- .I2(c_state[2]),
- .I3(c_state[0]),
- .I4(c_state[4]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\FSM_sequential_c_state[4]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT2 #(
- .INIT(4'hB))
- \FSM_sequential_c_state[4]_i_3
- (.I0(i2c_al),
- .I1(s00_axi_aresetn),
- .O(\FSM_sequential_c_state[4]_i_3_n_0 ));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[0]_i_1_n_0 ),
- .Q(c_state[0]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[1]_i_1_n_0 ),
- .Q(c_state[1]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[2]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[2]_i_1_n_0 ),
- .Q(c_state[2]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[3]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[3]_i_1_n_0 ),
- .Q(c_state[3]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_c_state_reg[4]
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\FSM_sequential_c_state[4]_i_2_n_0 ),
- .Q(c_state[4]));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \FSM_sequential_statemachine.c_state[0]_i_1
- (.I0(\FSM_sequential_statemachine.c_state_reg[1]_1 ),
- .I1(out[2]),
- .I2(out[1]),
- .I3(\cr_reg[7] [2]),
- .I4(out[0]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\FSM_sequential_statemachine.c_state_reg[2] [0]));
- LUT6 #(
- .INIT(64'h0000000015100000))
- \FSM_sequential_statemachine.c_state[1]_i_1
- (.I0(out[2]),
- .I1(cnt_done),
- .I2(out[1]),
- .I3(\cr_reg[7]_0 ),
- .I4(s00_axi_aresetn),
- .I5(i2c_al),
- .O(\FSM_sequential_statemachine.c_state_reg[2] [1]));
- LUT6 #(
- .INIT(64'hDDFFDDDDFFFDDDFD))
- \FSM_sequential_statemachine.c_state[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_al),
- .I2(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
- .I3(out[1]),
- .I4(core_ack),
- .I5(out[2]),
- .O(E));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \FSM_sequential_statemachine.c_state[2]_i_2
- (.I0(\FSM_sequential_statemachine.c_state_reg[1]_2 ),
- .I1(out[2]),
- .I2(out[1]),
- .I3(\cr_reg[7] [2]),
- .I4(out[0]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\FSM_sequential_statemachine.c_state_reg[2] [2]));
- LUT6 #(
- .INIT(64'h8B8B8B8B8B8B8B88))
- \FSM_sequential_statemachine.c_state[2]_i_3
- (.I0(core_ack),
- .I1(out[0]),
- .I2(cmd_ack),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [1]),
- .I5(\cr_reg[7] [2]),
- .O(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSCL[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_scl_io),
- .O(\bus_status_ctrl.cSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSCL[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(p_0_in__0),
- .O(\bus_status_ctrl.cSCL[1]_i_1_n_0 ));
- FDCE \bus_status_ctrl.cSCL_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSCL[0]_i_1_n_0 ),
- .Q(p_0_in__0));
- FDCE \bus_status_ctrl.cSCL_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSCL[1]_i_1_n_0 ),
- .Q(p_0_in__1[0]));
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSDA[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_sda_io),
- .O(\bus_status_ctrl.cSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT2 #(
- .INIT(4'h8))
- \bus_status_ctrl.cSDA[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(p_0_in),
- .O(\bus_status_ctrl.cSDA[1]_i_1_n_0 ));
- FDCE \bus_status_ctrl.cSDA_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSDA[0]_i_1_n_0 ),
- .Q(p_0_in));
- FDCE \bus_status_ctrl.cSDA_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cSDA[1]_i_1_n_0 ),
- .Q(\bus_status_ctrl.cSDA_reg_n_0_[1] ));
- LUT6 #(
- .INIT(64'h04FF000004000000))
- \bus_status_ctrl.cmd_stop_i_1
- (.I0(\statemachine.core_cmd_reg[3]_0 [0]),
- .I1(\statemachine.core_cmd_reg[3]_0 [1]),
- .I2(\bus_status_ctrl.cmd_stop_i_2_n_0 ),
- .I3(clk_en),
- .I4(s00_axi_aresetn),
- .I5(\bus_status_ctrl.cmd_stop_reg_n_0 ),
- .O(\bus_status_ctrl.cmd_stop_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \bus_status_ctrl.cmd_stop_i_2
- (.I0(\statemachine.core_cmd_reg[3]_0 [2]),
- .I1(\statemachine.core_cmd_reg[3]_0 [3]),
- .O(\bus_status_ctrl.cmd_stop_i_2_n_0 ));
- FDCE \bus_status_ctrl.cmd_stop_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.cmd_stop_i_1_n_0 ),
- .Q(\bus_status_ctrl.cmd_stop_reg_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.dSCL_i_1
- (.I0(sSCL),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.dSCL_i_1_n_0 ));
- FDPE \bus_status_ctrl.dSCL_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.dSCL_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(dSCL));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.dSDA_i_1
- (.I0(sSDA),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.dSDA_i_1_n_0 ));
- FDPE \bus_status_ctrl.dSDA_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.dSDA_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(dSDA));
- LUT4 #(
- .INIT(16'hFB08))
- \bus_status_ctrl.dout_i_1
- (.I0(sSDA),
- .I1(sSCL),
- .I2(dSCL),
- .I3(core_rxd),
- .O(\bus_status_ctrl.dout_i_1_n_0 ));
- FDCE \bus_status_ctrl.dout_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.dout_i_1_n_0 ),
- .Q(core_rxd));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSCL[0]_i_1
- (.I0(p_0_in__1[0]),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSCL[1]_i_1
- (.I0(p_0_in__1[1]),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSCL[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSCL[2]_i_1
- (.I0(p_0_in__1[2]),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSCL[2]_i_1_n_0 ));
- FDPE \bus_status_ctrl.fSCL_reg[0]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSCL[0]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(p_0_in__1[1]));
- FDPE \bus_status_ctrl.fSCL_reg[1]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSCL[1]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(p_0_in__1[2]));
- FDPE \bus_status_ctrl.fSCL_reg[2]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSCL[2]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSCL_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[0]_i_1
- (.I0(\bus_status_ctrl.cSDA_reg_n_0_[1] ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[1]_i_1
- (.I0(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[1]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[2]_i_1
- (.I0(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT2 #(
- .INIT(4'hB))
- \bus_status_ctrl.fSDA[2]_i_2
- (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
- .I1(s00_axi_aresetn),
- .O(\bus_status_ctrl.fSDA[2]_i_2_n_0 ));
- FDPE \bus_status_ctrl.fSDA_reg[0]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSDA[0]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSDA_reg_n_0_[0] ));
- FDPE \bus_status_ctrl.fSDA_reg[1]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSDA[1]_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSDA_reg_n_0_[1] ));
- FDPE \bus_status_ctrl.fSDA_reg[2]
- (.C(s00_axi_aclk),
- .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
- .D(\bus_status_ctrl.fSDA[2]_i_2_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(\bus_status_ctrl.fSDA_reg_n_0_[2] ));
- LUT5 #(
- .INIT(32'hD1000000))
- \bus_status_ctrl.filter_cnt[0]_i_1
- (.I0(filter_cnt[0]),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[2]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[10]_i_1
- (.I0(minusOp_carry__1_n_6),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[12]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[11]_i_1
- (.I0(minusOp_carry__1_n_5),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[13]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[12]_i_1
- (.I0(minusOp_carry__1_n_4),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[14]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[13]_i_1
- (.I0(minusOp_carry__2_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[15]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000001))
- \bus_status_ctrl.filter_cnt[13]_i_2
- (.I0(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ),
- .I2(filter_cnt[6]),
- .I3(filter_cnt[7]),
- .I4(filter_cnt[4]),
- .I5(filter_cnt[5]),
- .O(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \bus_status_ctrl.filter_cnt[13]_i_3
- (.I0(filter_cnt[13]),
- .I1(filter_cnt[12]),
- .I2(filter_cnt[9]),
- .I3(filter_cnt[8]),
- .I4(filter_cnt[11]),
- .I5(filter_cnt[10]),
- .O(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \bus_status_ctrl.filter_cnt[13]_i_4
- (.I0(filter_cnt[2]),
- .I1(filter_cnt[3]),
- .I2(filter_cnt[0]),
- .I3(filter_cnt[1]),
- .O(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[1]_i_1
- (.I0(minusOp_carry_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[3]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[2]_i_1
- (.I0(minusOp_carry_n_6),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[4]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[3]_i_1
- (.I0(minusOp_carry_n_5),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[5]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[4]_i_1
- (.I0(minusOp_carry_n_4),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[6]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[5]_i_1
- (.I0(minusOp_carry__0_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[7]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[6]_i_1
- (.I0(minusOp_carry__0_n_6),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[8]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[7]_i_1
- (.I0(minusOp_carry__0_n_5),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[9]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[8]_i_1
- (.I0(minusOp_carry__0_n_4),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[10]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hE2000000))
- \bus_status_ctrl.filter_cnt[9]_i_1
- (.I0(minusOp_carry__1_n_7),
- .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
- .I2(Q[11]),
- .I3(\ctr_reg[7] ),
- .I4(s00_axi_aresetn),
- .O(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ));
- FDCE \bus_status_ctrl.filter_cnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ),
- .Q(filter_cnt[0]));
- FDCE \bus_status_ctrl.filter_cnt_reg[10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ),
- .Q(filter_cnt[10]));
- FDCE \bus_status_ctrl.filter_cnt_reg[11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ),
- .Q(filter_cnt[11]));
- FDCE \bus_status_ctrl.filter_cnt_reg[12]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ),
- .Q(filter_cnt[12]));
- FDCE \bus_status_ctrl.filter_cnt_reg[13]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ),
- .Q(filter_cnt[13]));
- FDCE \bus_status_ctrl.filter_cnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ),
- .Q(filter_cnt[1]));
- FDCE \bus_status_ctrl.filter_cnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ),
- .Q(filter_cnt[2]));
- FDCE \bus_status_ctrl.filter_cnt_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ),
- .Q(filter_cnt[3]));
- FDCE \bus_status_ctrl.filter_cnt_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ),
- .Q(filter_cnt[4]));
- FDCE \bus_status_ctrl.filter_cnt_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ),
- .Q(filter_cnt[5]));
- FDCE \bus_status_ctrl.filter_cnt_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ),
- .Q(filter_cnt[6]));
- FDCE \bus_status_ctrl.filter_cnt_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ),
- .Q(filter_cnt[7]));
- FDCE \bus_status_ctrl.filter_cnt_reg[8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ),
- .Q(filter_cnt[8]));
- FDCE \bus_status_ctrl.filter_cnt_reg[9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ),
- .Q(filter_cnt[9]));
- LUT6 #(
- .INIT(64'h08000800AAAA0800))
- \bus_status_ctrl.ial_i_1
- (.I0(s00_axi_aresetn),
- .I1(sda_chk_reg_n_0),
- .I2(sSDA),
- .I3(sda_padoen_o),
- .I4(\bus_status_ctrl.ial_i_2_n_0 ),
- .I5(\bus_status_ctrl.ial_i_3_n_0 ),
- .O(ial));
- LUT2 #(
- .INIT(4'h1))
- \bus_status_ctrl.ial_i_2
- (.I0(c_state[0]),
- .I1(c_state[4]),
- .O(\bus_status_ctrl.ial_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFEF))
- \bus_status_ctrl.ial_i_3
- (.I0(c_state[2]),
- .I1(c_state[3]),
- .I2(\bus_status_ctrl.sto_condition_reg_n_0 ),
- .I3(\bus_status_ctrl.cmd_stop_reg_n_0 ),
- .I4(c_state[1]),
- .O(\bus_status_ctrl.ial_i_3_n_0 ));
- FDCE \bus_status_ctrl.ial_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(ial),
- .Q(i2c_al));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h5400))
- \bus_status_ctrl.ibusy_i_1
- (.I0(\bus_status_ctrl.sto_condition_reg_n_0 ),
- .I1(\bus_status_ctrl.sta_condition_reg_n_0 ),
- .I2(i2c_busy),
- .I3(s00_axi_aresetn),
- .O(ibusy));
- FDCE \bus_status_ctrl.ibusy_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(ibusy),
- .Q(i2c_busy));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'hE8FF))
- \bus_status_ctrl.sSCL_i_1
- (.I0(p_0_in__1[2]),
- .I1(\bus_status_ctrl.fSCL_reg_n_0_[2] ),
- .I2(p_0_in__1[1]),
- .I3(s00_axi_aresetn),
- .O(\bus_status_ctrl.sSCL_i_1_n_0 ));
- FDPE \bus_status_ctrl.sSCL_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.sSCL_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(sSCL));
- LUT4 #(
- .INIT(16'hE8FF))
- \bus_status_ctrl.sSDA_i_1
- (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
- .I1(\bus_status_ctrl.fSDA_reg_n_0_[2] ),
- .I2(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
- .I3(s00_axi_aresetn),
- .O(\bus_status_ctrl.sSDA_i_1_n_0 ));
- FDPE \bus_status_ctrl.sSDA_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\bus_status_ctrl.sSDA_i_1_n_0 ),
- .PRE(iscl_oen_reg_0),
- .Q(sSDA));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h2000))
- \bus_status_ctrl.sta_condition_i_1
- (.I0(dSDA),
- .I1(sSDA),
- .I2(s00_axi_aresetn),
- .I3(sSCL),
- .O(sta_condition));
- FDCE \bus_status_ctrl.sta_condition_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(sta_condition),
- .Q(\bus_status_ctrl.sta_condition_reg_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h4000))
- \bus_status_ctrl.sto_condition_i_1
- (.I0(dSDA),
- .I1(s00_axi_aresetn),
- .I2(sSCL),
- .I3(sSDA),
- .O(sto_condition));
- FDCE \bus_status_ctrl.sto_condition_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(sto_condition),
- .Q(\bus_status_ctrl.sto_condition_reg_n_0 ));
- LUT5 #(
- .INIT(32'hAAAAAAAB))
- clk_en_i_1
- (.I0(clk_en_i_2_n_0),
- .I1(clk_en_i_3_n_0),
- .I2(clk_en_i_4_n_0),
- .I3(clk_en_i_5_n_0),
- .I4(clk_en_i_6_n_0),
- .O(cnt1));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT5 #(
- .INIT(32'h7555FFFF))
- clk_en_i_2
- (.I0(\ctr_reg[7] ),
- .I1(sSCL),
- .I2(scl_padoen_o),
- .I3(dSCL),
- .I4(s00_axi_aresetn),
- .O(clk_en_i_2_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_3
- (.I0(cnt_reg[6]),
- .I1(cnt_reg[7]),
- .I2(cnt_reg[4]),
- .I3(cnt_reg[5]),
- .O(clk_en_i_3_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_4
- (.I0(cnt_reg[2]),
- .I1(cnt_reg[3]),
- .I2(cnt_reg[0]),
- .I3(cnt_reg[1]),
- .O(clk_en_i_4_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_5
- (.I0(cnt_reg[15]),
- .I1(cnt_reg[14]),
- .I2(cnt_reg[12]),
- .I3(cnt_reg[13]),
- .O(clk_en_i_5_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- clk_en_i_6
- (.I0(cnt_reg[10]),
- .I1(cnt_reg[11]),
- .I2(cnt_reg[8]),
- .I3(cnt_reg[9]),
- .O(clk_en_i_6_n_0));
- FDPE clk_en_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cnt1),
- .PRE(iscl_oen_reg_0),
- .Q(clk_en));
- LUT6 #(
- .INIT(64'h0008000000000000))
- cmd_ack_i_1
- (.I0(cmd_ack_i_2_n_0),
- .I1(c_state[0]),
- .I2(c_state[1]),
- .I3(i2c_al),
- .I4(s00_axi_aresetn),
- .I5(clk_en),
- .O(cmd_ack3_out));
- LUT3 #(
- .INIT(8'h1E))
- cmd_ack_i_2
- (.I0(c_state[2]),
- .I1(c_state[3]),
- .I2(c_state[4]),
- .O(cmd_ack_i_2_n_0));
- FDCE cmd_ack_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(cmd_ack3_out),
- .Q(core_ack));
- LUT2 #(
- .INIT(4'hB))
- \cnt[0]_i_1
- (.I0(cnt1),
- .I1(slave_wait),
- .O(\cnt[0]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_10
- (.I0(cnt_reg[0]),
- .I1(Q[0]),
- .I2(cnt1),
- .O(\cnt[0]_i_10_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_3
- (.I0(Q[3]),
- .I1(cnt1),
- .I2(cnt_reg[3]),
- .O(\cnt[0]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_4
- (.I0(Q[2]),
- .I1(cnt1),
- .I2(cnt_reg[2]),
- .O(\cnt[0]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_5
- (.I0(Q[1]),
- .I1(cnt1),
- .I2(cnt_reg[1]),
- .O(\cnt[0]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[0]_i_6
- (.I0(Q[0]),
- .I1(cnt1),
- .I2(cnt_reg[0]),
- .O(\cnt[0]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_7
- (.I0(cnt_reg[3]),
- .I1(Q[3]),
- .I2(cnt1),
- .O(\cnt[0]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_8
- (.I0(cnt_reg[2]),
- .I1(Q[2]),
- .I2(cnt1),
- .O(\cnt[0]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[0]_i_9
- (.I0(cnt_reg[1]),
- .I1(Q[1]),
- .I2(cnt1),
- .O(\cnt[0]_i_9_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[12]_i_2
- (.I0(Q[14]),
- .I1(cnt1),
- .I2(cnt_reg[14]),
- .O(\cnt[12]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[12]_i_3
- (.I0(Q[13]),
- .I1(cnt1),
- .I2(cnt_reg[13]),
- .O(\cnt[12]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[12]_i_4
- (.I0(Q[12]),
- .I1(cnt1),
- .I2(cnt_reg[12]),
- .O(\cnt[12]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_5
- (.I0(cnt_reg[15]),
- .I1(Q[15]),
- .I2(cnt1),
- .O(\cnt[12]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_6
- (.I0(cnt_reg[14]),
- .I1(Q[14]),
- .I2(cnt1),
- .O(\cnt[12]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_7
- (.I0(cnt_reg[13]),
- .I1(Q[13]),
- .I2(cnt1),
- .O(\cnt[12]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[12]_i_8
- (.I0(cnt_reg[12]),
- .I1(Q[12]),
- .I2(cnt1),
- .O(\cnt[12]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_2
- (.I0(Q[7]),
- .I1(cnt1),
- .I2(cnt_reg[7]),
- .O(\cnt[4]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_3
- (.I0(Q[6]),
- .I1(cnt1),
- .I2(cnt_reg[6]),
- .O(\cnt[4]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_4
- (.I0(Q[5]),
- .I1(cnt1),
- .I2(cnt_reg[5]),
- .O(\cnt[4]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[4]_i_5
- (.I0(Q[4]),
- .I1(cnt1),
- .I2(cnt_reg[4]),
- .O(\cnt[4]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_6
- (.I0(cnt_reg[7]),
- .I1(Q[7]),
- .I2(cnt1),
- .O(\cnt[4]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_7
- (.I0(cnt_reg[6]),
- .I1(Q[6]),
- .I2(cnt1),
- .O(\cnt[4]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_8
- (.I0(cnt_reg[5]),
- .I1(Q[5]),
- .I2(cnt1),
- .O(\cnt[4]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[4]_i_9
- (.I0(cnt_reg[4]),
- .I1(Q[4]),
- .I2(cnt1),
- .O(\cnt[4]_i_9_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_2
- (.I0(Q[11]),
- .I1(cnt1),
- .I2(cnt_reg[11]),
- .O(\cnt[8]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_3
- (.I0(Q[10]),
- .I1(cnt1),
- .I2(cnt_reg[10]),
- .O(\cnt[8]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_4
- (.I0(Q[9]),
- .I1(cnt1),
- .I2(cnt_reg[9]),
- .O(\cnt[8]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \cnt[8]_i_5
- (.I0(Q[8]),
- .I1(cnt1),
- .I2(cnt_reg[8]),
- .O(\cnt[8]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_6
- (.I0(cnt_reg[11]),
- .I1(Q[11]),
- .I2(cnt1),
- .O(\cnt[8]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_7
- (.I0(cnt_reg[10]),
- .I1(Q[10]),
- .I2(cnt1),
- .O(\cnt[8]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_8
- (.I0(cnt_reg[9]),
- .I1(Q[9]),
- .I2(cnt1),
- .O(\cnt[8]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'hC5))
- \cnt[8]_i_9
- (.I0(cnt_reg[8]),
- .I1(Q[8]),
- .I2(cnt1),
- .O(\cnt[8]_i_9_n_0 ));
- FDCE \cnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_7 ),
- .Q(cnt_reg[0]));
- CARRY4 \cnt_reg[0]_i_2
- (.CI(1'b0),
- .CO({\cnt_reg[0]_i_2_n_0 ,\cnt_reg[0]_i_2_n_1 ,\cnt_reg[0]_i_2_n_2 ,\cnt_reg[0]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({\cnt[0]_i_3_n_0 ,\cnt[0]_i_4_n_0 ,\cnt[0]_i_5_n_0 ,\cnt[0]_i_6_n_0 }),
- .O({\cnt_reg[0]_i_2_n_4 ,\cnt_reg[0]_i_2_n_5 ,\cnt_reg[0]_i_2_n_6 ,\cnt_reg[0]_i_2_n_7 }),
- .S({\cnt[0]_i_7_n_0 ,\cnt[0]_i_8_n_0 ,\cnt[0]_i_9_n_0 ,\cnt[0]_i_10_n_0 }));
- FDCE \cnt_reg[10]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_5 ),
- .Q(cnt_reg[10]));
- FDCE \cnt_reg[11]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_4 ),
- .Q(cnt_reg[11]));
- FDCE \cnt_reg[12]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_7 ),
- .Q(cnt_reg[12]));
- CARRY4 \cnt_reg[12]_i_1
- (.CI(\cnt_reg[8]_i_1_n_0 ),
- .CO({\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED [3],\cnt_reg[12]_i_1_n_1 ,\cnt_reg[12]_i_1_n_2 ,\cnt_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,\cnt[12]_i_2_n_0 ,\cnt[12]_i_3_n_0 ,\cnt[12]_i_4_n_0 }),
- .O({\cnt_reg[12]_i_1_n_4 ,\cnt_reg[12]_i_1_n_5 ,\cnt_reg[12]_i_1_n_6 ,\cnt_reg[12]_i_1_n_7 }),
- .S({\cnt[12]_i_5_n_0 ,\cnt[12]_i_6_n_0 ,\cnt[12]_i_7_n_0 ,\cnt[12]_i_8_n_0 }));
- FDCE \cnt_reg[13]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_6 ),
- .Q(cnt_reg[13]));
- FDCE \cnt_reg[14]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_5 ),
- .Q(cnt_reg[14]));
- FDCE \cnt_reg[15]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[12]_i_1_n_4 ),
- .Q(cnt_reg[15]));
- FDCE \cnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_6 ),
- .Q(cnt_reg[1]));
- FDCE \cnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_5 ),
- .Q(cnt_reg[2]));
- FDCE \cnt_reg[3]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[0]_i_2_n_4 ),
- .Q(cnt_reg[3]));
- FDCE \cnt_reg[4]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_7 ),
- .Q(cnt_reg[4]));
- CARRY4 \cnt_reg[4]_i_1
- (.CI(\cnt_reg[0]_i_2_n_0 ),
- .CO({\cnt_reg[4]_i_1_n_0 ,\cnt_reg[4]_i_1_n_1 ,\cnt_reg[4]_i_1_n_2 ,\cnt_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({\cnt[4]_i_2_n_0 ,\cnt[4]_i_3_n_0 ,\cnt[4]_i_4_n_0 ,\cnt[4]_i_5_n_0 }),
- .O({\cnt_reg[4]_i_1_n_4 ,\cnt_reg[4]_i_1_n_5 ,\cnt_reg[4]_i_1_n_6 ,\cnt_reg[4]_i_1_n_7 }),
- .S({\cnt[4]_i_6_n_0 ,\cnt[4]_i_7_n_0 ,\cnt[4]_i_8_n_0 ,\cnt[4]_i_9_n_0 }));
- FDCE \cnt_reg[5]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_6 ),
- .Q(cnt_reg[5]));
- FDCE \cnt_reg[6]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_5 ),
- .Q(cnt_reg[6]));
- FDCE \cnt_reg[7]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[4]_i_1_n_4 ),
- .Q(cnt_reg[7]));
- FDCE \cnt_reg[8]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_7 ),
- .Q(cnt_reg[8]));
- CARRY4 \cnt_reg[8]_i_1
- (.CI(\cnt_reg[4]_i_1_n_0 ),
- .CO({\cnt_reg[8]_i_1_n_0 ,\cnt_reg[8]_i_1_n_1 ,\cnt_reg[8]_i_1_n_2 ,\cnt_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({\cnt[8]_i_2_n_0 ,\cnt[8]_i_3_n_0 ,\cnt[8]_i_4_n_0 ,\cnt[8]_i_5_n_0 }),
- .O({\cnt_reg[8]_i_1_n_4 ,\cnt_reg[8]_i_1_n_5 ,\cnt_reg[8]_i_1_n_6 ,\cnt_reg[8]_i_1_n_7 }),
- .S({\cnt[8]_i_6_n_0 ,\cnt[8]_i_7_n_0 ,\cnt[8]_i_8_n_0 ,\cnt[8]_i_9_n_0 }));
- FDCE \cnt_reg[9]
- (.C(s00_axi_aclk),
- .CE(\cnt[0]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(\cnt_reg[8]_i_1_n_6 ),
- .Q(cnt_reg[9]));
- LUT6 #(
- .INIT(64'h55FDFDFDFFFFFFFF))
- \cr[7]_i_1
- (.I0(s00_axi_aresetn),
- .I1(i2c_al),
- .I2(cmd_ack),
- .I3(iack_o_reg),
- .I4(wb_we_o),
- .I5(iack_o_reg_0),
- .O(\cr_reg[4] ));
- FDCE dscl_oen_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(scl_padoen_o),
- .Q(dscl_oen));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_scl_io_INST_0
- (.I0(1'b0),
- .I1(i2c_scl_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_scl_io));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_scl_io_INST_0_i_1
- (.I0(scl_padoen_o),
- .O(i2c_scl_io_INST_0_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_sda_io_INST_0
- (.I0(1'b0),
- .I1(i2c_sda_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_sda_io));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_sda_io_INST_0_i_1
- (.I0(sda_padoen_o),
- .O(i2c_sda_io_INST_0_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT5 #(
- .INIT(32'hFBFFFBF3))
- iscl_oen_i_1
- (.I0(iscl_oen),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .I3(iscl_oen9_out__0),
- .I4(scl_padoen_o),
- .O(iscl_oen_i_1_n_0));
- LUT5 #(
- .INIT(32'h00F3011F))
- iscl_oen_i_2
- (.I0(c_state[3]),
- .I1(c_state[2]),
- .I2(c_state[1]),
- .I3(c_state[4]),
- .I4(c_state[0]),
- .O(iscl_oen));
- LUT5 #(
- .INIT(32'h55560000))
- iscl_oen_i_3
- (.I0(c_state[4]),
- .I1(c_state[3]),
- .I2(c_state[2]),
- .I3(c_state[1]),
- .I4(clk_en),
- .O(iscl_oen9_out__0));
- FDPE iscl_oen_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(iscl_oen_i_1_n_0),
- .PRE(iscl_oen_reg_0),
- .Q(scl_padoen_o));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT5 #(
- .INIT(32'hFBFFFBF3))
- isda_oen_i_1
- (.I0(isda_oen),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .I3(isda_oen7_out__0),
- .I4(sda_padoen_o),
- .O(isda_oen_i_1_n_0));
- LUT6 #(
- .INIT(64'h0000C8CB03038F83))
- isda_oen_i_2
- (.I0(\statemachine.core_txd_reg_0 ),
- .I1(c_state[3]),
- .I2(c_state[2]),
- .I3(c_state[0]),
- .I4(c_state[4]),
- .I5(c_state[1]),
- .O(isda_oen));
- LUT6 #(
- .INIT(64'h0F0F1F1E00000000))
- isda_oen_i_3
- (.I0(c_state[1]),
- .I1(c_state[2]),
- .I2(c_state[4]),
- .I3(c_state[0]),
- .I4(c_state[3]),
- .I5(clk_en),
- .O(isda_oen7_out__0));
- FDPE isda_oen_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(isda_oen_i_1_n_0),
- .PRE(iscl_oen_reg_0),
- .Q(sda_padoen_o));
- CARRY4 minusOp_carry
- (.CI(1'b0),
- .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
- .CYINIT(filter_cnt[0]),
- .DI(filter_cnt[4:1]),
- .O({minusOp_carry_n_4,minusOp_carry_n_5,minusOp_carry_n_6,minusOp_carry_n_7}),
- .S({minusOp_carry_i_1_n_0,minusOp_carry_i_2_n_0,minusOp_carry_i_3_n_0,minusOp_carry_i_4_n_0}));
- CARRY4 minusOp_carry__0
- (.CI(minusOp_carry_n_0),
- .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
- .CYINIT(1'b0),
- .DI(filter_cnt[8:5]),
- .O({minusOp_carry__0_n_4,minusOp_carry__0_n_5,minusOp_carry__0_n_6,minusOp_carry__0_n_7}),
- .S({minusOp_carry__0_i_1_n_0,minusOp_carry__0_i_2_n_0,minusOp_carry__0_i_3_n_0,minusOp_carry__0_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_1
- (.I0(filter_cnt[8]),
- .O(minusOp_carry__0_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_2
- (.I0(filter_cnt[7]),
- .O(minusOp_carry__0_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_3
- (.I0(filter_cnt[6]),
- .O(minusOp_carry__0_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__0_i_4
- (.I0(filter_cnt[5]),
- .O(minusOp_carry__0_i_4_n_0));
- CARRY4 minusOp_carry__1
- (.CI(minusOp_carry__0_n_0),
- .CO({minusOp_carry__1_n_0,minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}),
- .CYINIT(1'b0),
- .DI(filter_cnt[12:9]),
- .O({minusOp_carry__1_n_4,minusOp_carry__1_n_5,minusOp_carry__1_n_6,minusOp_carry__1_n_7}),
- .S({minusOp_carry__1_i_1_n_0,minusOp_carry__1_i_2_n_0,minusOp_carry__1_i_3_n_0,minusOp_carry__1_i_4_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_1
- (.I0(filter_cnt[12]),
- .O(minusOp_carry__1_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_2
- (.I0(filter_cnt[11]),
- .O(minusOp_carry__1_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_3
- (.I0(filter_cnt[10]),
- .O(minusOp_carry__1_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__1_i_4
- (.I0(filter_cnt[9]),
- .O(minusOp_carry__1_i_4_n_0));
- CARRY4 minusOp_carry__2
- (.CI(minusOp_carry__1_n_0),
- .CO(NLW_minusOp_carry__2_CO_UNCONNECTED[3:0]),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({NLW_minusOp_carry__2_O_UNCONNECTED[3:1],minusOp_carry__2_n_7}),
- .S({1'b0,1'b0,1'b0,minusOp_carry__2_i_1_n_0}));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry__2_i_1
- (.I0(filter_cnt[13]),
- .O(minusOp_carry__2_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_1
- (.I0(filter_cnt[4]),
- .O(minusOp_carry_i_1_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_2
- (.I0(filter_cnt[3]),
- .O(minusOp_carry_i_2_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_3
- (.I0(filter_cnt[2]),
- .O(minusOp_carry_i_3_n_0));
- LUT1 #(
- .INIT(2'h1))
- minusOp_carry_i_4
- (.I0(filter_cnt[1]),
- .O(minusOp_carry_i_4_n_0));
- LUT6 #(
- .INIT(64'h0000000000100000))
- sda_chk_i_1
- (.I0(c_state[4]),
- .I1(c_state[1]),
- .I2(c_state[3]),
- .I3(c_state[0]),
- .I4(c_state[2]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(sda_chk_i_1_n_0));
- FDCE sda_chk_reg
- (.C(s00_axi_aclk),
- .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
- .CLR(iscl_oen_reg_0),
- .D(sda_chk_i_1_n_0),
- .Q(sda_chk_reg_n_0));
- LUT4 #(
- .INIT(16'h0F04))
- slave_wait_i_1
- (.I0(dscl_oen),
- .I1(scl_padoen_o),
- .I2(sSCL),
- .I3(slave_wait),
- .O(slave_wait0));
- FDCE slave_wait_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg_0),
- .D(slave_wait0),
- .Q(slave_wait));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT4 #(
- .INIT(16'hE400))
- \sr[0]_i_1
- (.I0(\statemachine.ld_reg_0 ),
- .I1(core_rxd),
- .I2(\txr_reg[6] [0]),
- .I3(s00_axi_aresetn),
- .O(\sr_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'hAA08))
- \st_irq_block.al_i_1
- (.I0(s00_axi_aresetn),
- .I1(\st_irq_block.al_reg ),
- .I2(\cr_reg[7] [3]),
- .I3(i2c_al),
- .O(al));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT5 #(
- .INIT(32'h55540000))
- \st_irq_block.irq_flag_i_1
- (.I0(\cr_reg[0] ),
- .I1(i2c_al),
- .I2(cmd_ack),
- .I3(irq_flag),
- .I4(s00_axi_aresetn),
- .O(irq_flag1_out));
- LUT1 #(
- .INIT(2'h1))
- \st_irq_block.wb_inta_o_i_2
- (.I0(s00_axi_aresetn),
- .O(iscl_oen_reg_0));
- LUT5 #(
- .INIT(32'h08FF0800))
- \statemachine.ack_out_i_1
- (.I0(core_rxd),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .I3(\statemachine.ack_out_i_2_n_0 ),
- .I4(ack_out),
- .O(\statemachine.ack_out_reg ));
- LUT6 #(
- .INIT(64'hDDDDDDDDDDFDDDDD))
- \statemachine.ack_out_i_2
- (.I0(s00_axi_aresetn),
- .I1(i2c_al),
- .I2(out[2]),
- .I3(out[0]),
- .I4(core_ack),
- .I5(out[1]),
- .O(\statemachine.ack_out_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000100000))
- \statemachine.core_cmd[0]_i_1
- (.I0(out[2]),
- .I1(out[0]),
- .I2(\cr_reg[7] [3]),
- .I3(out[1]),
- .I4(s00_axi_aresetn),
- .I5(i2c_al),
- .O(\statemachine.core_cmd_reg[3] [0]));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \statemachine.core_cmd[1]_i_1
- (.I0(\FSM_sequential_statemachine.c_state_reg[1]_0 ),
- .I1(out[2]),
- .I2(out[1]),
- .I3(\cr_reg[7] [2]),
- .I4(out[0]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\statemachine.core_cmd_reg[3] [1]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT3 #(
- .INIT(8'h08))
- \statemachine.core_cmd[2]_i_1
- (.I0(core_cmd),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .O(\statemachine.core_cmd_reg[3] [2]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0040))
- \statemachine.core_cmd[3]_i_1
- (.I0(out[2]),
- .I1(\FSM_sequential_statemachine.c_state_reg[1] ),
- .I2(s00_axi_aresetn),
- .I3(i2c_al),
- .O(\statemachine.core_cmd_reg[3] [3]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT3 #(
- .INIT(8'h08))
- \statemachine.core_txd_i_1
- (.I0(core_txd),
- .I1(s00_axi_aresetn),
- .I2(i2c_al),
- .O(\statemachine.core_txd_reg ));
- LUT6 #(
- .INIT(64'h5455FFFD10002220))
- \statemachine.core_txd_i_2
- (.I0(out[2]),
- .I1(out[0]),
- .I2(ack_in),
- .I3(core_ack),
- .I4(out[1]),
- .I5(\sr_reg[7] ),
- .O(core_txd));
- LUT6 #(
- .INIT(64'h000000000000A020))
- \statemachine.host_ack_i_1
- (.I0(out[2]),
- .I1(\cr_reg[7] [2]),
- .I2(core_ack),
- .I3(out[0]),
- .I4(out[1]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\statemachine.host_ack_reg ));
- LUT5 #(
- .INIT(32'h00000400))
- \statemachine.ld_i_1
- (.I0(out[2]),
- .I1(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
- .I2(out[1]),
- .I3(s00_axi_aresetn),
- .I4(i2c_al),
- .O(\statemachine.ld_reg ));
- LUT6 #(
- .INIT(64'h0000000004440000))
- \statemachine.shift_i_1
- (.I0(out[2]),
- .I1(core_ack),
- .I2(out[0]),
- .I3(cnt_done),
- .I4(out[1]),
- .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
- .O(\statemachine.shift_reg ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[6]_i_3
- (.I0(\cr_reg[7] [2]),
- .I1(wb_adr_o[1]),
- .I2(\txr_reg[6] [1]),
- .I3(wb_adr_o[0]),
- .I4(i2c_busy),
- .O(\wb_dat_o[6]_i_3_n_0 ));
- MUXF7 \wb_dat_o_reg[6]_i_1
- (.I0(\sr_reg[6] ),
- .I1(\wb_dat_o[6]_i_3_n_0 ),
- .O(D),
- .S(wb_adr_o[2]));
-endmodule
-
-(* ORIG_REF_NAME = "i2c_master_byte_ctrl" *)
-module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
- (iscl_oen_reg,
- irq_flag1_out,
- rxack_0,
- al,
- D,
- E,
- i2c_sda_io,
- i2c_scl_io,
- s00_axi_aclk,
- s00_axi_aresetn,
- \cr_reg[0] ,
- irq_flag,
- Q,
- \ctr_reg[7] ,
- \st_irq_block.al_reg ,
- \cr_reg[7] ,
- wb_adr_o,
- \cr_reg[0]_0 ,
- \cr_reg[1] ,
- \cr_reg[2] ,
- \txr_reg[7] ,
- ack_in,
- \cr_reg[5] ,
- \cr_reg[7]_0 ,
- iack_o_reg,
- wb_we_o,
- iack_o_reg_0);
- output iscl_oen_reg;
- output irq_flag1_out;
- output rxack_0;
- output al;
- output [7:0]D;
- output [0:0]E;
- inout i2c_sda_io;
- inout i2c_scl_io;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input \cr_reg[0] ;
- input irq_flag;
- input [15:0]Q;
- input [7:0]\ctr_reg[7] ;
- input \st_irq_block.al_reg ;
- input [3:0]\cr_reg[7] ;
- input [2:0]wb_adr_o;
- input \cr_reg[0]_0 ;
- input \cr_reg[1] ;
- input \cr_reg[2] ;
- input [7:0]\txr_reg[7] ;
- input ack_in;
- input \cr_reg[5] ;
- input \cr_reg[7]_0 ;
- input iack_o_reg;
- input wb_we_o;
- input iack_o_reg_0;
-
- wire [7:0]D;
- wire [0:0]E;
- wire \FSM_sequential_statemachine.c_state[0]_i_2_n_0 ;
- wire \FSM_sequential_statemachine.c_state[1]_i_3_n_0 ;
- wire \FSM_sequential_statemachine.c_state[2]_i_4_n_0 ;
- wire [15:0]Q;
- wire ack_in;
- wire ack_out;
- wire al;
- wire bit_ctrl_n_10;
- wire bit_ctrl_n_11;
- wire bit_ctrl_n_12;
- wire bit_ctrl_n_13;
- wire bit_ctrl_n_15;
- wire bit_ctrl_n_16;
- wire bit_ctrl_n_17;
- wire bit_ctrl_n_18;
- wire bit_ctrl_n_5;
- wire bit_ctrl_n_6;
- wire bit_ctrl_n_7;
- wire bit_ctrl_n_8;
- wire bit_ctrl_n_9;
- wire c_state;
- (* RTL_KEEP = "yes" *) wire [2:0]c_state__0;
- wire [3:0]cmd;
- wire cmd_ack;
- wire cnt_done;
- wire [2:2]core_cmd;
- wire \cr_reg[0] ;
- wire \cr_reg[0]_0 ;
- wire \cr_reg[1] ;
- wire \cr_reg[2] ;
- wire \cr_reg[5] ;
- wire [3:0]\cr_reg[7] ;
- wire \cr_reg[7]_0 ;
- wire [7:0]\ctr_reg[7] ;
- wire dcnt;
- wire \dcnt[0]_i_1_n_0 ;
- wire \dcnt[1]_i_1_n_0 ;
- wire \dcnt[2]_i_1_n_0 ;
- wire \dcnt_reg_n_0_[0] ;
- wire \dcnt_reg_n_0_[1] ;
- wire \dcnt_reg_n_0_[2] ;
- wire [7:7]dout;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire iack_o_reg;
- wire iack_o_reg_0;
- wire irq_flag;
- wire irq_flag1_out;
- wire iscl_oen_reg;
- wire rxack_0;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire \sr[1]_i_1_n_0 ;
- wire \sr[2]_i_1_n_0 ;
- wire \sr[3]_i_1_n_0 ;
- wire \sr[4]_i_1_n_0 ;
- wire \sr[5]_i_1_n_0 ;
- wire \sr[6]_i_1_n_0 ;
- wire \sr[7]_i_2_n_0 ;
- wire \sr_reg_n_0_[0] ;
- wire \sr_reg_n_0_[1] ;
- wire \sr_reg_n_0_[2] ;
- wire \sr_reg_n_0_[3] ;
- wire \sr_reg_n_0_[4] ;
- wire \sr_reg_n_0_[5] ;
- wire \sr_reg_n_0_[6] ;
- wire \st_irq_block.al_reg ;
- wire \statemachine.core_cmd[1]_i_2_n_0 ;
- wire \statemachine.core_cmd[3]_i_2_n_0 ;
- wire \statemachine.core_txd_reg_n_0 ;
- wire \statemachine.ld_reg_n_0 ;
- wire \statemachine.shift_reg_n_0 ;
- wire [7:0]\txr_reg[7] ;
- wire [2:0]wb_adr_o;
- wire \wb_dat_o[0]_i_2_n_0 ;
- wire \wb_dat_o[1]_i_2_n_0 ;
- wire \wb_dat_o[2]_i_2_n_0 ;
- wire \wb_dat_o[3]_i_2_n_0 ;
- wire \wb_dat_o[4]_i_2_n_0 ;
- wire \wb_dat_o[5]_i_2_n_0 ;
- wire \wb_dat_o[6]_i_2_n_0 ;
- wire \wb_dat_o[7]_i_2_n_0 ;
- wire wb_we_o;
-
- LUT5 #(
- .INIT(32'h43407373))
- \FSM_sequential_statemachine.c_state[0]_i_2
- (.I0(cnt_done),
- .I1(c_state__0[1]),
- .I2(c_state__0[0]),
- .I3(\cr_reg[7] [3]),
- .I4(\cr_reg[7] [1]),
- .O(\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h01))
- \FSM_sequential_statemachine.c_state[1]_i_2
- (.I0(\dcnt_reg_n_0_[1] ),
- .I1(\dcnt_reg_n_0_[0] ),
- .I2(\dcnt_reg_n_0_[2] ),
- .O(cnt_done));
- LUT4 #(
- .INIT(16'hFF54))
- \FSM_sequential_statemachine.c_state[1]_i_3
- (.I0(\cr_reg[7] [3]),
- .I1(\cr_reg[7] [1]),
- .I2(\cr_reg[7] [0]),
- .I3(c_state__0[0]),
- .O(\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h888888888888888B))
- \FSM_sequential_statemachine.c_state[2]_i_4
- (.I0(cnt_done),
- .I1(c_state__0[1]),
- .I2(\cr_reg[7] [3]),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [1]),
- .I5(c_state__0[0]),
- .O(\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_statemachine.c_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_18),
- .Q(c_state__0[0]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_statemachine.c_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_17),
- .Q(c_state__0[1]));
- (* KEEP = "yes" *)
- FDCE \FSM_sequential_statemachine.c_state_reg[2]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_16),
- .Q(c_state__0[2]));
- system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl bit_ctrl
- (.D(D[6]),
- .E(c_state),
- .\FSM_sequential_statemachine.c_state_reg[1] (\statemachine.core_cmd[3]_i_2_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[1]_0 (\statemachine.core_cmd[1]_i_2_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[1]_1 (\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[1]_2 (\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_16,bit_ctrl_n_17,bit_ctrl_n_18}),
- .Q(Q),
- .ack_in(ack_in),
- .ack_out(ack_out),
- .al(al),
- .cmd_ack(cmd_ack),
- .cnt_done(cnt_done),
- .core_cmd(core_cmd),
- .\cr_reg[0] (\cr_reg[0] ),
- .\cr_reg[4] (E),
- .\cr_reg[7] (\cr_reg[7] ),
- .\cr_reg[7]_0 (\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ),
- .\ctr_reg[7] (\ctr_reg[7] [7]),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .iack_o_reg(iack_o_reg),
- .iack_o_reg_0(iack_o_reg_0),
- .irq_flag(irq_flag),
- .irq_flag1_out(irq_flag1_out),
- .iscl_oen_reg_0(iscl_oen_reg),
- .out(c_state__0),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .\sr_reg[0] (bit_ctrl_n_15),
- .\sr_reg[6] (\wb_dat_o[6]_i_2_n_0 ),
- .\sr_reg[7] (dout),
- .\st_irq_block.al_reg (\st_irq_block.al_reg ),
- .\statemachine.ack_out_reg (bit_ctrl_n_13),
- .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_5,bit_ctrl_n_6,bit_ctrl_n_7,bit_ctrl_n_8}),
- .\statemachine.core_cmd_reg[3]_0 (cmd),
- .\statemachine.core_txd_reg (bit_ctrl_n_10),
- .\statemachine.core_txd_reg_0 (\statemachine.core_txd_reg_n_0 ),
- .\statemachine.host_ack_reg (bit_ctrl_n_12),
- .\statemachine.ld_reg (bit_ctrl_n_9),
- .\statemachine.ld_reg_0 (\statemachine.ld_reg_n_0 ),
- .\statemachine.shift_reg (bit_ctrl_n_11),
- .\txr_reg[6] ({\txr_reg[7] [6],\txr_reg[7] [0]}),
- .wb_adr_o(wb_adr_o),
- .wb_we_o(wb_we_o));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT3 #(
- .INIT(8'h8A))
- \dcnt[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(\statemachine.ld_reg_n_0 ),
- .I2(\dcnt_reg_n_0_[0] ),
- .O(\dcnt[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT4 #(
- .INIT(16'hA88A))
- \dcnt[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(\statemachine.ld_reg_n_0 ),
- .I2(\dcnt_reg_n_0_[0] ),
- .I3(\dcnt_reg_n_0_[1] ),
- .O(\dcnt[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT5 #(
- .INIT(32'hAAA8888A))
- \dcnt[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(\statemachine.ld_reg_n_0 ),
- .I2(\dcnt_reg_n_0_[1] ),
- .I3(\dcnt_reg_n_0_[0] ),
- .I4(\dcnt_reg_n_0_[2] ),
- .O(\dcnt[2]_i_1_n_0 ));
- FDCE \dcnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\dcnt[0]_i_1_n_0 ),
- .Q(\dcnt_reg_n_0_[0] ));
- FDCE \dcnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\dcnt[1]_i_1_n_0 ),
- .Q(\dcnt_reg_n_0_[1] ));
- FDCE \dcnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\dcnt[2]_i_1_n_0 ),
- .Q(\dcnt_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT4 #(
- .INIT(16'hE400))
- \sr[1]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[0] ),
- .I2(\txr_reg[7] [1]),
- .I3(s00_axi_aresetn),
- .O(\sr[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT4 #(
- .INIT(16'hE400))
- \sr[2]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[1] ),
- .I2(\txr_reg[7] [2]),
- .I3(s00_axi_aresetn),
- .O(\sr[2]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[3]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[2] ),
- .I2(\txr_reg[7] [3]),
- .I3(s00_axi_aresetn),
- .O(\sr[3]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[4]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[3] ),
- .I2(\txr_reg[7] [4]),
- .I3(s00_axi_aresetn),
- .O(\sr[4]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[5]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[4] ),
- .I2(\txr_reg[7] [5]),
- .I3(s00_axi_aresetn),
- .O(\sr[5]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hE400))
- \sr[6]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[5] ),
- .I2(\txr_reg[7] [6]),
- .I3(s00_axi_aresetn),
- .O(\sr[6]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'hFB))
- \sr[7]_i_1
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(s00_axi_aresetn),
- .I2(\statemachine.shift_reg_n_0 ),
- .O(dcnt));
- LUT4 #(
- .INIT(16'hE400))
- \sr[7]_i_2
- (.I0(\statemachine.ld_reg_n_0 ),
- .I1(\sr_reg_n_0_[6] ),
- .I2(\txr_reg[7] [7]),
- .I3(s00_axi_aresetn),
- .O(\sr[7]_i_2_n_0 ));
- FDCE \sr_reg[0]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_15),
- .Q(\sr_reg_n_0_[0] ));
- FDCE \sr_reg[1]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[1]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[1] ));
- FDCE \sr_reg[2]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[2]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[2] ));
- FDCE \sr_reg[3]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[3]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[3] ));
- FDCE \sr_reg[4]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[4]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[4] ));
- FDCE \sr_reg[5]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[5]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[5] ));
- FDCE \sr_reg[6]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[6]_i_1_n_0 ),
- .Q(\sr_reg_n_0_[6] ));
- FDCE \sr_reg[7]
- (.C(s00_axi_aclk),
- .CE(dcnt),
- .CLR(iscl_oen_reg),
- .D(\sr[7]_i_2_n_0 ),
- .Q(dout));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT2 #(
- .INIT(4'h8))
- \st_irq_block.rxack_i_1
- (.I0(s00_axi_aresetn),
- .I1(ack_out),
- .O(rxack_0));
- FDCE \statemachine.ack_out_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_13),
- .Q(ack_out));
- LUT5 #(
- .INIT(32'h00000001))
- \statemachine.core_cmd[1]_i_2
- (.I0(c_state__0[1]),
- .I1(c_state__0[0]),
- .I2(\cr_reg[7] [3]),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [1]),
- .O(\statemachine.core_cmd[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h00000000F0C40FC4))
- \statemachine.core_cmd[2]_i_2
- (.I0(\cr_reg[7] [3]),
- .I1(\cr_reg[7] [1]),
- .I2(c_state__0[0]),
- .I3(c_state__0[1]),
- .I4(cnt_done),
- .I5(c_state__0[2]),
- .O(core_cmd));
- LUT6 #(
- .INIT(64'h4848484878787B78))
- \statemachine.core_cmd[3]_i_2
- (.I0(cnt_done),
- .I1(c_state__0[1]),
- .I2(c_state__0[0]),
- .I3(\cr_reg[7] [0]),
- .I4(\cr_reg[7] [3]),
- .I5(\cr_reg[7] [1]),
- .O(\statemachine.core_cmd[3]_i_2_n_0 ));
- FDCE \statemachine.core_cmd_reg[0]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_8),
- .Q(cmd[0]));
- FDCE \statemachine.core_cmd_reg[1]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_7),
- .Q(cmd[1]));
- FDCE \statemachine.core_cmd_reg[2]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_6),
- .Q(cmd[2]));
- FDCE \statemachine.core_cmd_reg[3]
- (.C(s00_axi_aclk),
- .CE(c_state),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_5),
- .Q(cmd[3]));
- FDCE \statemachine.core_txd_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_10),
- .Q(\statemachine.core_txd_reg_n_0 ));
- FDCE \statemachine.host_ack_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_12),
- .Q(cmd_ack));
- FDCE \statemachine.ld_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_9),
- .Q(\statemachine.ld_reg_n_0 ));
- FDCE \statemachine.shift_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(iscl_oen_reg),
- .D(bit_ctrl_n_11),
- .Q(\statemachine.shift_reg_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[0]_i_2
- (.I0(\sr_reg_n_0_[0] ),
- .I1(\ctr_reg[7] [0]),
- .I2(wb_adr_o[1]),
- .I3(Q[8]),
- .I4(wb_adr_o[0]),
- .I5(Q[0]),
- .O(\wb_dat_o[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[1]_i_2
- (.I0(\sr_reg_n_0_[1] ),
- .I1(\ctr_reg[7] [1]),
- .I2(wb_adr_o[1]),
- .I3(Q[9]),
- .I4(wb_adr_o[0]),
- .I5(Q[1]),
- .O(\wb_dat_o[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h3808FFFF38080000))
- \wb_dat_o[2]_i_1
- (.I0(\cr_reg[2] ),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[0]),
- .I3(\txr_reg[7] [2]),
- .I4(wb_adr_o[2]),
- .I5(\wb_dat_o[2]_i_2_n_0 ),
- .O(D[2]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[2]_i_2
- (.I0(\sr_reg_n_0_[2] ),
- .I1(\ctr_reg[7] [2]),
- .I2(wb_adr_o[1]),
- .I3(Q[10]),
- .I4(wb_adr_o[0]),
- .I5(Q[2]),
- .O(\wb_dat_o[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h3808FFFF38080000))
- \wb_dat_o[3]_i_1
- (.I0(ack_in),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[0]),
- .I3(\txr_reg[7] [3]),
- .I4(wb_adr_o[2]),
- .I5(\wb_dat_o[3]_i_2_n_0 ),
- .O(D[3]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[3]_i_2
- (.I0(\sr_reg_n_0_[3] ),
- .I1(\ctr_reg[7] [3]),
- .I2(wb_adr_o[1]),
- .I3(Q[11]),
- .I4(wb_adr_o[0]),
- .I5(Q[3]),
- .O(\wb_dat_o[3]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h3808FFFF38080000))
- \wb_dat_o[4]_i_1
- (.I0(\cr_reg[7] [0]),
- .I1(wb_adr_o[1]),
- .I2(wb_adr_o[0]),
- .I3(\txr_reg[7] [4]),
- .I4(wb_adr_o[2]),
- .I5(\wb_dat_o[4]_i_2_n_0 ),
- .O(D[4]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[4]_i_2
- (.I0(\sr_reg_n_0_[4] ),
- .I1(\ctr_reg[7] [4]),
- .I2(wb_adr_o[1]),
- .I3(Q[12]),
- .I4(wb_adr_o[0]),
- .I5(Q[4]),
- .O(\wb_dat_o[4]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[5]_i_2
- (.I0(\sr_reg_n_0_[5] ),
- .I1(\ctr_reg[7] [5]),
- .I2(wb_adr_o[1]),
- .I3(Q[13]),
- .I4(wb_adr_o[0]),
- .I5(Q[5]),
- .O(\wb_dat_o[5]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[6]_i_2
- (.I0(\sr_reg_n_0_[6] ),
- .I1(\ctr_reg[7] [6]),
- .I2(wb_adr_o[1]),
- .I3(Q[14]),
- .I4(wb_adr_o[0]),
- .I5(Q[6]),
- .O(\wb_dat_o[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \wb_dat_o[7]_i_2
- (.I0(dout),
- .I1(\ctr_reg[7] [7]),
- .I2(wb_adr_o[1]),
- .I3(Q[15]),
- .I4(wb_adr_o[0]),
- .I5(Q[7]),
- .O(\wb_dat_o[7]_i_2_n_0 ));
- MUXF7 \wb_dat_o_reg[0]_i_1
- (.I0(\wb_dat_o[0]_i_2_n_0 ),
- .I1(\cr_reg[0]_0 ),
- .O(D[0]),
- .S(wb_adr_o[2]));
- MUXF7 \wb_dat_o_reg[1]_i_1
- (.I0(\wb_dat_o[1]_i_2_n_0 ),
- .I1(\cr_reg[1] ),
- .O(D[1]),
- .S(wb_adr_o[2]));
- MUXF7 \wb_dat_o_reg[5]_i_1
- (.I0(\wb_dat_o[5]_i_2_n_0 ),
- .I1(\cr_reg[5] ),
- .O(D[5]),
- .S(wb_adr_o[2]));
- MUXF7 \wb_dat_o_reg[7]_i_1
- (.I0(\wb_dat_o[7]_i_2_n_0 ),
- .I1(\cr_reg[7]_0 ),
- .O(D[7]),
- .S(wb_adr_o[2]));
-endmodule
-
-(* ORIG_REF_NAME = "i2c_master_top" *)
-module system_design_axi_wb_i2c_master_2_0_i2c_master_top
- (wb_ack_i,
- wb_rst_o,
- axi_int_o,
- Q,
- s_stb_r_reg,
- \s_rdata_reg[0] ,
- \s_rdata_reg[7] ,
- i2c_sda_io,
- i2c_scl_io,
- s_stb_r_reg_0,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_wdata,
- wb_adr_o,
- s00_axi_awvalid,
- s00_axi_arvalid,
- wb_cyc_o,
- wb_we_o,
- iack_o_reg_0,
- E,
- s_we_r_reg,
- s_we_r_reg_0,
- D,
- \s_addr_reg[4] );
- output wb_ack_i;
- output wb_rst_o;
- output axi_int_o;
- output [0:0]Q;
- output s_stb_r_reg;
- output [0:0]\s_rdata_reg[0] ;
- output [7:0]\s_rdata_reg[7] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
- input s_stb_r_reg_0;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [7:0]s00_axi_wdata;
- input [2:0]wb_adr_o;
- input s00_axi_awvalid;
- input s00_axi_arvalid;
- input wb_cyc_o;
- input wb_we_o;
- input iack_o_reg_0;
- input [1:0]E;
- input [0:0]s_we_r_reg;
- input [0:0]s_we_r_reg_0;
- input [3:0]D;
- input \s_addr_reg[4] ;
-
- wire [3:0]D;
- wire [1:0]E;
- wire [0:0]Q;
- wire ack_in;
- wire al;
- wire axi_int_o;
- wire byte_ctrl_n_12;
- wire \cr[0]_i_1_n_0 ;
- wire \cr[1]_i_1_n_0 ;
- wire \cr[2]_i_1_n_0 ;
- wire \cr[3]_i_1_n_0 ;
- wire \cr_reg_n_0_[0] ;
- wire \cr_reg_n_0_[1] ;
- wire \cr_reg_n_0_[2] ;
- wire [7:0]ctr;
- wire \ctr_reg_n_0_[0] ;
- wire \ctr_reg_n_0_[1] ;
- wire \ctr_reg_n_0_[2] ;
- wire \ctr_reg_n_0_[3] ;
- wire \ctr_reg_n_0_[4] ;
- wire \ctr_reg_n_0_[5] ;
- wire [13:0]data0;
- wire i2c_scl_io;
- wire i2c_sda_io;
- wire iack_o_reg_0;
- wire ien;
- wire irq_flag;
- wire irq_flag1_out;
- wire \prer[10]_i_1_n_0 ;
- wire \prer[11]_i_1_n_0 ;
- wire \prer[12]_i_1_n_0 ;
- wire \prer[13]_i_1_n_0 ;
- wire \prer[14]_i_1_n_0 ;
- wire \prer[15]_i_2_n_0 ;
- wire \prer[8]_i_1_n_0 ;
- wire \prer[9]_i_1_n_0 ;
- wire \prer_reg_n_0_[0] ;
- wire \prer_reg_n_0_[1] ;
- wire read;
- wire rxack;
- wire rxack_0;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s00_axi_arvalid;
- wire s00_axi_awvalid;
- wire [7:0]s00_axi_wdata;
- wire \s_addr_reg[4] ;
- wire [0:0]\s_rdata_reg[0] ;
- wire [7:0]\s_rdata_reg[7] ;
- wire s_stb_r_reg;
- wire s_stb_r_reg_0;
- wire [0:0]s_we_r_reg;
- wire [0:0]s_we_r_reg_0;
- wire \st_irq_block.al_reg_n_0 ;
- wire \st_irq_block.wb_inta_o_i_1_n_0 ;
- wire start;
- wire stop;
- wire tip;
- wire tip_1;
- wire [7:0]txr;
- wire wb_ack_i;
- wire [2:0]wb_adr_o;
- wire wb_cyc_o;
- wire [7:0]wb_dat_o;
- wire \wb_dat_o[0]_i_3_n_0 ;
- wire \wb_dat_o[1]_i_3_n_0 ;
- wire \wb_dat_o[5]_i_3_n_0 ;
- wire \wb_dat_o[7]_i_3_n_0 ;
- wire wb_rst_o;
- wire wb_we_o;
- wire write;
-
- system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl byte_ctrl
- (.D(wb_dat_o),
- .E(byte_ctrl_n_12),
- .Q({data0,\prer_reg_n_0_[1] ,\prer_reg_n_0_[0] }),
- .ack_in(ack_in),
- .al(al),
- .\cr_reg[0] (\cr_reg_n_0_[0] ),
- .\cr_reg[0]_0 (\wb_dat_o[0]_i_3_n_0 ),
- .\cr_reg[1] (\wb_dat_o[1]_i_3_n_0 ),
- .\cr_reg[2] (\cr_reg_n_0_[2] ),
- .\cr_reg[5] (\wb_dat_o[5]_i_3_n_0 ),
- .\cr_reg[7] ({start,stop,read,write}),
- .\cr_reg[7]_0 (\wb_dat_o[7]_i_3_n_0 ),
- .\ctr_reg[7] ({Q,ien,\ctr_reg_n_0_[5] ,\ctr_reg_n_0_[4] ,\ctr_reg_n_0_[3] ,\ctr_reg_n_0_[2] ,\ctr_reg_n_0_[1] ,\ctr_reg_n_0_[0] }),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
- .iack_o_reg(wb_ack_i),
- .iack_o_reg_0(iack_o_reg_0),
- .irq_flag(irq_flag),
- .irq_flag1_out(irq_flag1_out),
- .iscl_oen_reg(wb_rst_o),
- .rxack_0(rxack_0),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .\st_irq_block.al_reg (\st_irq_block.al_reg_n_0 ),
- .\txr_reg[7] (txr),
- .wb_adr_o(wb_adr_o),
- .wb_we_o(wb_we_o));
- LUT6 #(
- .INIT(64'h8000FFFF80000000))
- \cr[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[0]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .I4(\s_addr_reg[4] ),
- .I5(\cr_reg_n_0_[0] ),
- .O(\cr[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8000FFFF80000000))
- \cr[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[1]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .I4(\s_addr_reg[4] ),
- .I5(\cr_reg_n_0_[1] ),
- .O(\cr[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h8000FFFF80000000))
- \cr[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[2]),
- .I2(wb_we_o),
- .I3(wb_ack_i),
- .I4(\s_addr_reg[4] ),
- .I5(\cr_reg_n_0_[2] ),
- .O(\cr[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT4 #(
- .INIT(16'hC808))
- \cr[3]_i_1
- (.I0(s00_axi_wdata[3]),
- .I1(s00_axi_aresetn),
- .I2(iack_o_reg_0),
- .I3(ack_in),
- .O(\cr[3]_i_1_n_0 ));
- FDCE \cr_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[0]_i_1_n_0 ),
- .Q(\cr_reg_n_0_[0] ));
- FDCE \cr_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[1]_i_1_n_0 ),
- .Q(\cr_reg_n_0_[1] ));
- FDCE \cr_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[2]_i_1_n_0 ),
- .Q(\cr_reg_n_0_[2] ));
- FDCE \cr_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\cr[3]_i_1_n_0 ),
- .Q(ack_in));
- FDCE \cr_reg[4]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[0]),
- .Q(write));
- FDCE \cr_reg[5]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[1]),
- .Q(read));
- FDCE \cr_reg[6]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[2]),
- .Q(stop));
- FDCE \cr_reg[7]
- (.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
- .CLR(wb_rst_o),
- .D(D[3]),
- .Q(start));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[0]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[0]),
- .O(ctr[0]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[1]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[1]),
- .O(ctr[1]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[2]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[2]),
- .O(ctr[2]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[3]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[3]),
- .O(ctr[3]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[4]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[4]),
- .O(ctr[4]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[5]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[5]),
- .O(ctr[5]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[6]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[6]),
- .O(ctr[6]));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT2 #(
- .INIT(4'h8))
- \ctr[7]_i_2
- (.I0(s00_axi_aresetn),
- .I1(s00_axi_wdata[7]),
- .O(ctr[7]));
- FDCE \ctr_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[0]),
- .Q(\ctr_reg_n_0_[0] ));
- FDCE \ctr_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[1]),
- .Q(\ctr_reg_n_0_[1] ));
- FDCE \ctr_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[2]),
- .Q(\ctr_reg_n_0_[2] ));
- FDCE \ctr_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[3]),
- .Q(\ctr_reg_n_0_[3] ));
- FDCE \ctr_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[4]),
- .Q(\ctr_reg_n_0_[4] ));
- FDCE \ctr_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[5]),
- .Q(\ctr_reg_n_0_[5] ));
- FDCE \ctr_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[6]),
- .Q(ien));
- FDCE \ctr_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg),
- .CLR(wb_rst_o),
- .D(ctr[7]),
- .Q(Q));
- FDRE iack_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_stb_r_reg_0),
- .Q(wb_ack_i),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[10]_i_1
- (.I0(s00_axi_wdata[2]),
- .I1(s00_axi_aresetn),
- .O(\prer[10]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hB))
- \prer[11]_i_1
- (.I0(s00_axi_wdata[3]),
- .I1(s00_axi_aresetn),
- .O(\prer[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[12]_i_1
- (.I0(s00_axi_wdata[4]),
- .I1(s00_axi_aresetn),
- .O(\prer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[13]_i_1
- (.I0(s00_axi_wdata[5]),
- .I1(s00_axi_aresetn),
- .O(\prer[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[14]_i_1
- (.I0(s00_axi_wdata[6]),
- .I1(s00_axi_aresetn),
- .O(\prer[14]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[15]_i_2
- (.I0(s00_axi_wdata[7]),
- .I1(s00_axi_aresetn),
- .O(\prer[15]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[8]_i_1
- (.I0(s00_axi_wdata[0]),
- .I1(s00_axi_aresetn),
- .O(\prer[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'hB))
- \prer[9]_i_1
- (.I0(s00_axi_wdata[1]),
- .I1(s00_axi_aresetn),
- .O(\prer[9]_i_1_n_0 ));
- FDPE \prer_reg[0]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[8]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(\prer_reg_n_0_[0] ));
- FDPE \prer_reg[10]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[10]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[8]));
- FDPE \prer_reg[11]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[11]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[9]));
- FDPE \prer_reg[12]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[12]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[10]));
- FDPE \prer_reg[13]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[13]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[11]));
- FDPE \prer_reg[14]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[14]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[12]));
- FDPE \prer_reg[15]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[15]_i_2_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[13]));
- FDPE \prer_reg[1]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[9]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(\prer_reg_n_0_[1] ));
- FDPE \prer_reg[2]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[10]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[0]));
- FDPE \prer_reg[3]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[11]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[1]));
- FDPE \prer_reg[4]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[12]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[2]));
- FDPE \prer_reg[5]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[13]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[3]));
- FDPE \prer_reg[6]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[14]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[4]));
- FDPE \prer_reg[7]
- (.C(s00_axi_aclk),
- .CE(E[0]),
- .D(\prer[15]_i_2_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[5]));
- FDPE \prer_reg[8]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[8]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[6]));
- FDPE \prer_reg[9]
- (.C(s00_axi_aclk),
- .CE(E[1]),
- .D(\prer[9]_i_1_n_0 ),
- .PRE(wb_rst_o),
- .Q(data0[7]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT2 #(
- .INIT(4'h2))
- \s_rdata[7]_i_1
- (.I0(wb_ack_i),
- .I1(wb_we_o),
- .O(\s_rdata_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT4 #(
- .INIT(16'hEFEE))
- s_stb_r_i_1
- (.I0(s00_axi_awvalid),
- .I1(s00_axi_arvalid),
- .I2(wb_ack_i),
- .I3(wb_cyc_o),
- .O(s_stb_r_reg));
- FDCE \st_irq_block.al_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(al),
- .Q(\st_irq_block.al_reg_n_0 ));
- FDCE \st_irq_block.irq_flag_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(irq_flag1_out),
- .Q(irq_flag));
- FDCE \st_irq_block.rxack_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(rxack_0),
- .Q(rxack));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT3 #(
- .INIT(8'hA8))
- \st_irq_block.tip_i_1
- (.I0(s00_axi_aresetn),
- .I1(write),
- .I2(read),
- .O(tip_1));
- FDCE \st_irq_block.tip_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(tip_1),
- .Q(tip));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT3 #(
- .INIT(8'h80))
- \st_irq_block.wb_inta_o_i_1
- (.I0(irq_flag),
- .I1(s00_axi_aresetn),
- .I2(ien),
- .O(\st_irq_block.wb_inta_o_i_1_n_0 ));
- FDCE \st_irq_block.wb_inta_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(wb_rst_o),
- .D(\st_irq_block.wb_inta_o_i_1_n_0 ),
- .Q(axi_int_o));
- FDCE \txr_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[0]),
- .Q(txr[0]));
- FDCE \txr_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[1]),
- .Q(txr[1]));
- FDCE \txr_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[2]),
- .Q(txr[2]));
- FDCE \txr_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[3]),
- .Q(txr[3]));
- FDCE \txr_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[4]),
- .Q(txr[4]));
- FDCE \txr_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[5]),
- .Q(txr[5]));
- FDCE \txr_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[6]),
- .Q(txr[6]));
- FDCE \txr_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_we_r_reg_0),
- .CLR(wb_rst_o),
- .D(ctr[7]),
- .Q(txr[7]));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[0]_i_3
- (.I0(\cr_reg_n_0_[0] ),
- .I1(wb_adr_o[1]),
- .I2(txr[0]),
- .I3(wb_adr_o[0]),
- .I4(irq_flag),
- .O(\wb_dat_o[0]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[1]_i_3
- (.I0(\cr_reg_n_0_[1] ),
- .I1(wb_adr_o[1]),
- .I2(txr[1]),
- .I3(wb_adr_o[0]),
- .I4(tip),
- .O(\wb_dat_o[1]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[5]_i_3
- (.I0(read),
- .I1(wb_adr_o[1]),
- .I2(txr[5]),
- .I3(wb_adr_o[0]),
- .I4(\st_irq_block.al_reg_n_0 ),
- .O(\wb_dat_o[5]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \wb_dat_o[7]_i_3
- (.I0(start),
- .I1(wb_adr_o[1]),
- .I2(txr[7]),
- .I3(wb_adr_o[0]),
- .I4(rxack),
- .O(\wb_dat_o[7]_i_3_n_0 ));
- FDRE \wb_dat_o_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[0]),
- .Q(\s_rdata_reg[7] [0]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[1]),
- .Q(\s_rdata_reg[7] [1]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[2]),
- .Q(\s_rdata_reg[7] [2]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[3]),
- .Q(\s_rdata_reg[7] [3]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[4]),
- .Q(\s_rdata_reg[7] [4]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[5]),
- .Q(\s_rdata_reg[7] [5]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[6]),
- .Q(\s_rdata_reg[7] [6]),
- .R(1'b0));
- FDRE \wb_dat_o_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(wb_dat_o[7]),
- .Q(\s_rdata_reg[7] [7]),
- .R(1'b0));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (weak1, weak0) GSR = GSR_int;
- assign (weak1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
deleted file mode 100644
index 9d359d30277af7191c6849a74542afefc918c126..0000000000000000000000000000000000000000
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
+++ /dev/null
@@ -1,4880 +0,0 @@
--- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Tue Jun 20 20:06:00 2017
--- Host : lapte24154 running 64-bit openSUSE Leap 42.2
--- Command : write_vhdl -force -mode funcsim
--- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
--- Design : system_design_axi_wb_i2c_master_2_0
--- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--- synthesized. This netlist cannot be used for SDF annotated simulation.
--- Device : xc7z030ffg676-2
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge is
- port (
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- wb_we_o : out STD_LOGIC;
- wb_cyc_o : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_bvalid : out STD_LOGIC;
- \cr_reg[2]\ : out STD_LOGIC;
- wb_adr_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 3 downto 0 );
- \cr_reg[4]\ : out STD_LOGIC;
- \prer_reg[8]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
- \ctr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_rvalid : out STD_LOGIC;
- iack_o_reg : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
- wb_rst_o : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC;
- wb_ack_i : in STD_LOGIC;
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_rready : in STD_LOGIC;
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
- iack_o_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \wb_dat_o_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge : entity is "axis_wbm_bridge";
-end system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge is
- signal \cr[2]_i_3_n_0\ : STD_LOGIC;
- signal \^s00_axi_arready\ : STD_LOGIC;
- signal \^s00_axi_awready\ : STD_LOGIC;
- signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s00_axi_wready\ : STD_LOGIC;
- signal \s_addr[2]_i_1_n_0\ : STD_LOGIC;
- signal \s_addr[3]_i_1_n_0\ : STD_LOGIC;
- signal \s_addr[4]_i_1_n_0\ : STD_LOGIC;
- signal s_arready_i_1_n_0 : STD_LOGIC;
- signal s_awready_i_1_n_0 : STD_LOGIC;
- signal \s_bresp[1]_i_1_n_0\ : STD_LOGIC;
- signal s_bvalid : STD_LOGIC;
- signal s_bvalid_i_1_n_0 : STD_LOGIC;
- signal s_rvalid : STD_LOGIC;
- signal s_rvalid_i_1_n_0 : STD_LOGIC;
- signal s_we_r_i_1_n_0 : STD_LOGIC;
- signal s_wready_i_1_n_0 : STD_LOGIC;
- signal \^wb_adr_o\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^wb_cyc_o\ : STD_LOGIC;
- signal \^wb_we_o\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \cr[2]_i_3\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \ctr[7]_i_1\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of iack_o_i_1 : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of \prer[15]_i_1\ : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of s00_axi_bvalid_INST_0 : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of s00_axi_rvalid_INST_0 : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of s_awready_i_1 : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \s_bresp[1]_i_1\ : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of s_rvalid_i_1 : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of s_we_r_i_1 : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of s_wready_i_1 : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \txr[7]_i_1\ : label is "soft_lutpair0";
-begin
- s00_axi_arready <= \^s00_axi_arready\;
- s00_axi_awready <= \^s00_axi_awready\;
- s00_axi_bresp(0) <= \^s00_axi_bresp\(0);
- s00_axi_wready <= \^s00_axi_wready\;
- wb_adr_o(2 downto 0) <= \^wb_adr_o\(2 downto 0);
- wb_cyc_o <= \^wb_cyc_o\;
- wb_we_o <= \^wb_we_o\;
-\cr[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFF0008FFFFFFFF"
- )
- port map (
- I0 => \^wb_adr_o\(2),
- I1 => Q(0),
- I2 => \^wb_adr_o\(1),
- I3 => \^wb_adr_o\(0),
- I4 => \cr[2]_i_3_n_0\,
- I5 => s00_axi_aresetn,
- O => \cr_reg[2]\
- );
-\cr[2]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- O => \cr[2]_i_3_n_0\
- );
-\cr[4]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(0),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(0)
- );
-\cr[5]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(1),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(1)
- );
-\cr[6]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(2),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(2)
- );
-\cr[7]_i_2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(3),
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => D(3)
- );
-\cr[7]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFF7FFF"
- )
- port map (
- I0 => wb_ack_i,
- I1 => \^wb_we_o\,
- I2 => \^wb_adr_o\(2),
- I3 => Q(0),
- I4 => \^wb_adr_o\(1),
- I5 => \^wb_adr_o\(0),
- O => \cr_reg[4]\
- );
-\ctr[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0080FFFF"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- I2 => \^wb_adr_o\(1),
- I3 => \^wb_adr_o\(0),
- I4 => s00_axi_aresetn,
- O => \ctr_reg[0]\(0)
- );
-iack_o_i_1: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \^wb_cyc_o\,
- I1 => wb_ack_i,
- O => iack_o_reg
- );
-\prer[15]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"75555555"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \^wb_adr_o\(1),
- I2 => wb_ack_i,
- I3 => \^wb_we_o\,
- I4 => \^wb_adr_o\(0),
- O => \prer_reg[8]\(1)
- );
-\prer[7]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"5555555557555555"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \^wb_adr_o\(1),
- I2 => \^wb_adr_o\(2),
- I3 => wb_ack_i,
- I4 => \^wb_we_o\,
- I5 => \^wb_adr_o\(0),
- O => \prer_reg[8]\(0)
- );
-s00_axi_bvalid_INST_0: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s_bvalid,
- I1 => \^wb_we_o\,
- O => s00_axi_bvalid
- );
-s00_axi_rvalid_INST_0: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => s_rvalid,
- I1 => \^wb_we_o\,
- O => s00_axi_rvalid
- );
-\s_addr[2]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AACFAAC0"
- )
- port map (
- I0 => s00_axi_araddr(0),
- I1 => s00_axi_awaddr(0),
- I2 => s00_axi_awvalid,
- I3 => s00_axi_arvalid,
- I4 => \^wb_adr_o\(0),
- O => \s_addr[2]_i_1_n_0\
- );
-\s_addr[3]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AACFAAC0"
- )
- port map (
- I0 => s00_axi_araddr(1),
- I1 => s00_axi_awaddr(1),
- I2 => s00_axi_awvalid,
- I3 => s00_axi_arvalid,
- I4 => \^wb_adr_o\(1),
- O => \s_addr[3]_i_1_n_0\
- );
-\s_addr[4]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AACFAAC0"
- )
- port map (
- I0 => s00_axi_araddr(2),
- I1 => s00_axi_awaddr(2),
- I2 => s00_axi_awvalid,
- I3 => s00_axi_arvalid,
- I4 => \^wb_adr_o\(2),
- O => \s_addr[4]_i_1_n_0\
- );
-\s_addr_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_addr[2]_i_1_n_0\,
- Q => \^wb_adr_o\(0),
- R => wb_rst_o
- );
-\s_addr_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_addr[3]_i_1_n_0\,
- Q => \^wb_adr_o\(1),
- R => wb_rst_o
- );
-\s_addr_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_addr[4]_i_1_n_0\,
- Q => \^wb_adr_o\(2),
- R => wb_rst_o
- );
-s_arready_i_1: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => s00_axi_arvalid,
- I1 => \^s00_axi_arready\,
- O => s_arready_i_1_n_0
- );
-s_arready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_arready_i_1_n_0,
- Q => \^s00_axi_arready\,
- R => wb_rst_o
- );
-s_awready_i_1: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s00_axi_wvalid,
- I1 => s00_axi_awvalid,
- I2 => \^s00_axi_awready\,
- O => s_awready_i_1_n_0
- );
-s_awready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_awready_i_1_n_0,
- Q => \^s00_axi_awready\,
- R => wb_rst_o
- );
-\s_bresp[1]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FF7F0000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \^wb_we_o\,
- I2 => wb_ack_i,
- I3 => s_bvalid,
- I4 => \^s00_axi_bresp\(0),
- O => \s_bresp[1]_i_1_n_0\
- );
-\s_bresp_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_bresp[1]_i_1_n_0\,
- Q => \^s00_axi_bresp\(0),
- R => '0'
- );
-s_bvalid_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0F88"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- I2 => s00_axi_bready,
- I3 => s_bvalid,
- O => s_bvalid_i_1_n_0
- );
-s_bvalid_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_bvalid_i_1_n_0,
- Q => s_bvalid,
- R => wb_rst_o
- );
-\s_rdata_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(0),
- Q => s00_axi_rdata(0),
- R => wb_rst_o
- );
-\s_rdata_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(1),
- Q => s00_axi_rdata(1),
- R => wb_rst_o
- );
-\s_rdata_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(2),
- Q => s00_axi_rdata(2),
- R => wb_rst_o
- );
-\s_rdata_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(3),
- Q => s00_axi_rdata(3),
- R => wb_rst_o
- );
-\s_rdata_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(4),
- Q => s00_axi_rdata(4),
- R => wb_rst_o
- );
-\s_rdata_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(5),
- Q => s00_axi_rdata(5),
- R => wb_rst_o
- );
-\s_rdata_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(6),
- Q => s00_axi_rdata(6),
- R => wb_rst_o
- );
-\s_rdata_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => iack_o_reg_1(0),
- D => \wb_dat_o_reg[7]\(7),
- Q => s00_axi_rdata(7),
- R => wb_rst_o
- );
-s_rvalid_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4F44"
- )
- port map (
- I0 => s00_axi_rready,
- I1 => s_rvalid,
- I2 => \^wb_we_o\,
- I3 => wb_ack_i,
- O => s_rvalid_i_1_n_0
- );
-s_rvalid_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_rvalid_i_1_n_0,
- Q => s_rvalid,
- R => wb_rst_o
- );
-s_stb_r_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => iack_o_reg_0,
- Q => \^wb_cyc_o\,
- R => wb_rst_o
- );
-s_we_r_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00E0"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => s00_axi_awvalid,
- I2 => s00_axi_aresetn,
- I3 => s00_axi_arvalid,
- O => s_we_r_i_1_n_0
- );
-s_we_r_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_we_r_i_1_n_0,
- Q => \^wb_we_o\,
- R => '0'
- );
-s_wready_i_1: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s00_axi_wvalid,
- I1 => s00_axi_awvalid,
- I2 => \^s00_axi_wready\,
- O => s_wready_i_1_n_0
- );
-s_wready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_wready_i_1_n_0,
- Q => \^s00_axi_wready\,
- R => wb_rst_o
- );
-\txr[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"8000FFFF"
- )
- port map (
- I0 => \^wb_we_o\,
- I1 => wb_ack_i,
- I2 => \^wb_adr_o\(0),
- I3 => \^wb_adr_o\(1),
- I4 => s00_axi_aresetn,
- O => E(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl is
- port (
- iscl_oen_reg_0 : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- irq_flag1_out : out STD_LOGIC;
- al : out STD_LOGIC;
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- \statemachine.core_cmd_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
- \statemachine.ld_reg\ : out STD_LOGIC;
- \statemachine.core_txd_reg\ : out STD_LOGIC;
- \statemachine.shift_reg\ : out STD_LOGIC;
- \statemachine.host_ack_reg\ : out STD_LOGIC;
- \statemachine.ack_out_reg\ : out STD_LOGIC;
- \cr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \sr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \FSM_sequential_statemachine.c_state_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \cr_reg[0]\ : in STD_LOGIC;
- cmd_ack : in STD_LOGIC;
- irq_flag : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
- \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \statemachine.core_cmd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \st_irq_block.al_reg\ : in STD_LOGIC;
- \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \sr_reg[6]\ : in STD_LOGIC;
- \txr_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \FSM_sequential_statemachine.c_state_reg[1]\ : in STD_LOGIC;
- core_cmd : in STD_LOGIC_VECTOR ( 0 to 0 );
- \FSM_sequential_statemachine.c_state_reg[1]_0\ : in STD_LOGIC;
- cnt_done : in STD_LOGIC;
- ack_out : in STD_LOGIC;
- iack_o_reg : in STD_LOGIC;
- wb_we_o : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC;
- \statemachine.ld_reg_0\ : in STD_LOGIC;
- \FSM_sequential_statemachine.c_state_reg[1]_1\ : in STD_LOGIC;
- \FSM_sequential_statemachine.c_state_reg[1]_2\ : in STD_LOGIC;
- ack_in : in STD_LOGIC;
- \sr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \cr_reg[7]_0\ : in STD_LOGIC;
- \statemachine.core_txd_reg_0\ : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl : entity is "i2c_master_bit_ctrl";
-end system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl is
- signal \FSM_sequential_c_state[0]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[0]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[1]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[1]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[1]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[2]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[2]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[3]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[3]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[3]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[4]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[4]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_c_state[4]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_statemachine.c_state[2]_i_3_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSCL[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSCL[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSDA[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSDA[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cSDA_reg_n_0_[1]\ : STD_LOGIC;
- signal \bus_status_ctrl.cmd_stop_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cmd_stop_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.cmd_stop_reg_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.dSCL_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.dSDA_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.dout_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL[2]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSCL_reg_n_0_[2]\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[2]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA[2]_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA_reg_n_0_[0]\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA_reg_n_0_[1]\ : STD_LOGIC;
- signal \bus_status_ctrl.fSDA_reg_n_0_[2]\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[0]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[10]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[11]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[12]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_3_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[13]_i_4_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[1]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[2]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[3]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[4]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[5]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[6]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[7]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[8]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.filter_cnt[9]_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.ial_i_2_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.ial_i_3_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sSCL_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sSDA_i_1_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sta_condition_reg_n_0\ : STD_LOGIC;
- signal \bus_status_ctrl.sto_condition_reg_n_0\ : STD_LOGIC;
- signal c_state : STD_LOGIC_VECTOR ( 4 downto 0 );
- attribute RTL_KEEP : string;
- attribute RTL_KEEP of c_state : signal is "yes";
- signal clk_en : STD_LOGIC;
- signal clk_en_i_2_n_0 : STD_LOGIC;
- signal clk_en_i_3_n_0 : STD_LOGIC;
- signal clk_en_i_4_n_0 : STD_LOGIC;
- signal clk_en_i_5_n_0 : STD_LOGIC;
- signal clk_en_i_6_n_0 : STD_LOGIC;
- signal cmd_ack3_out : STD_LOGIC;
- signal cmd_ack_i_2_n_0 : STD_LOGIC;
- signal cnt1 : STD_LOGIC;
- signal \cnt[0]_i_10_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_1_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[0]_i_9_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_2_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[12]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_2_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[4]_i_9_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_2_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_3_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_4_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_5_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_6_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_7_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_8_n_0\ : STD_LOGIC;
- signal \cnt[8]_i_9_n_0\ : STD_LOGIC;
- signal cnt_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal \cnt_reg[0]_i_2_n_0\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_1\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_2\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_3\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_4\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_5\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_6\ : STD_LOGIC;
- signal \cnt_reg[0]_i_2_n_7\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_1\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_2\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_3\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_4\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_5\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_6\ : STD_LOGIC;
- signal \cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
- signal \cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
- signal \cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
- signal core_ack : STD_LOGIC;
- signal core_rxd : STD_LOGIC;
- signal core_txd : STD_LOGIC;
- signal dSCL : STD_LOGIC;
- signal dSDA : STD_LOGIC;
- signal dscl_oen : STD_LOGIC;
- signal filter_cnt : STD_LOGIC_VECTOR ( 13 downto 0 );
- signal i2c_al : STD_LOGIC;
- signal i2c_busy : STD_LOGIC;
- signal i2c_scl_io_INST_0_i_1_n_0 : STD_LOGIC;
- signal i2c_sda_io_INST_0_i_1_n_0 : STD_LOGIC;
- signal ial : STD_LOGIC;
- signal ibusy : STD_LOGIC;
- signal iscl_oen : STD_LOGIC;
- signal \iscl_oen9_out__0\ : STD_LOGIC;
- signal iscl_oen_i_1_n_0 : STD_LOGIC;
- signal \^iscl_oen_reg_0\ : STD_LOGIC;
- signal isda_oen : STD_LOGIC;
- signal \isda_oen7_out__0\ : STD_LOGIC;
- signal isda_oen_i_1_n_0 : STD_LOGIC;
- signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_n_0\ : STD_LOGIC;
- signal \minusOp_carry__0_n_1\ : STD_LOGIC;
- signal \minusOp_carry__0_n_2\ : STD_LOGIC;
- signal \minusOp_carry__0_n_3\ : STD_LOGIC;
- signal \minusOp_carry__0_n_4\ : STD_LOGIC;
- signal \minusOp_carry__0_n_5\ : STD_LOGIC;
- signal \minusOp_carry__0_n_6\ : STD_LOGIC;
- signal \minusOp_carry__0_n_7\ : STD_LOGIC;
- signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__1_n_1\ : STD_LOGIC;
- signal \minusOp_carry__1_n_2\ : STD_LOGIC;
- signal \minusOp_carry__1_n_3\ : STD_LOGIC;
- signal \minusOp_carry__1_n_4\ : STD_LOGIC;
- signal \minusOp_carry__1_n_5\ : STD_LOGIC;
- signal \minusOp_carry__1_n_6\ : STD_LOGIC;
- signal \minusOp_carry__1_n_7\ : STD_LOGIC;
- signal \minusOp_carry__2_i_1_n_0\ : STD_LOGIC;
- signal \minusOp_carry__2_n_7\ : STD_LOGIC;
- signal minusOp_carry_i_1_n_0 : STD_LOGIC;
- signal minusOp_carry_i_2_n_0 : STD_LOGIC;
- signal minusOp_carry_i_3_n_0 : STD_LOGIC;
- signal minusOp_carry_i_4_n_0 : STD_LOGIC;
- signal minusOp_carry_n_0 : STD_LOGIC;
- signal minusOp_carry_n_1 : STD_LOGIC;
- signal minusOp_carry_n_2 : STD_LOGIC;
- signal minusOp_carry_n_3 : STD_LOGIC;
- signal minusOp_carry_n_4 : STD_LOGIC;
- signal minusOp_carry_n_5 : STD_LOGIC;
- signal minusOp_carry_n_6 : STD_LOGIC;
- signal minusOp_carry_n_7 : STD_LOGIC;
- signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal sSCL : STD_LOGIC;
- signal sSDA : STD_LOGIC;
- signal scl_padoen_o : STD_LOGIC;
- signal sda_chk_i_1_n_0 : STD_LOGIC;
- signal sda_chk_reg_n_0 : STD_LOGIC;
- signal sda_padoen_o : STD_LOGIC;
- signal slave_wait : STD_LOGIC;
- signal slave_wait0 : STD_LOGIC;
- signal sta_condition : STD_LOGIC;
- signal \statemachine.ack_out_i_2_n_0\ : STD_LOGIC;
- signal sto_condition : STD_LOGIC;
- signal \wb_dat_o[6]_i_3_n_0\ : STD_LOGIC;
- signal \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
- signal \NLW_minusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_minusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \FSM_sequential_c_state[4]_i_3\ : label is "soft_lutpair9";
- attribute KEEP : string;
- attribute KEEP of \FSM_sequential_c_state_reg[0]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[1]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[2]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[3]\ : label is "yes";
- attribute KEEP of \FSM_sequential_c_state_reg[4]\ : label is "yes";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \bus_status_ctrl.dSCL_i_1\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of clk_en_i_2 : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of i2c_scl_io_INST_0_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of i2c_sda_io_INST_0_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of iscl_oen_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of isda_oen_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair16";
- attribute SOFT_HLUTNM of \st_irq_block.irq_flag_i_1\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair16";
-begin
- iscl_oen_reg_0 <= \^iscl_oen_reg_0\;
-\FSM_sequential_c_state[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"1111111111111110"
- )
- port map (
- I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
- I1 => c_state(0),
- I2 => c_state(2),
- I3 => c_state(3),
- I4 => \FSM_sequential_c_state[0]_i_2_n_0\,
- I5 => c_state(4),
- O => \FSM_sequential_c_state[0]_i_1_n_0\
- );
-\FSM_sequential_c_state[0]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AAAAAABA"
- )
- port map (
- I0 => c_state(1),
- I1 => \statemachine.core_cmd_reg[3]_0\(1),
- I2 => \statemachine.core_cmd_reg[3]_0\(0),
- I3 => \statemachine.core_cmd_reg[3]_0\(3),
- I4 => \statemachine.core_cmd_reg[3]_0\(2),
- O => \FSM_sequential_c_state[0]_i_2_n_0\
- );
-\FSM_sequential_c_state[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0400"
- )
- port map (
- I0 => i2c_al,
- I1 => s00_axi_aresetn,
- I2 => c_state(4),
- I3 => \FSM_sequential_c_state[1]_i_2_n_0\,
- O => \FSM_sequential_c_state[1]_i_1_n_0\
- );
-\FSM_sequential_c_state[1]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"EEEFEFFE44444444"
- )
- port map (
- I0 => c_state(0),
- I1 => c_state(1),
- I2 => \statemachine.core_cmd_reg[3]_0\(1),
- I3 => \statemachine.core_cmd_reg[3]_0\(2),
- I4 => \statemachine.core_cmd_reg[3]_0\(3),
- I5 => \FSM_sequential_c_state[1]_i_3_n_0\,
- O => \FSM_sequential_c_state[1]_i_2_n_0\
- );
-\FSM_sequential_c_state[1]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00001101"
- )
- port map (
- I0 => c_state(2),
- I1 => c_state(1),
- I2 => \statemachine.core_cmd_reg[3]_0\(0),
- I3 => c_state(0),
- I4 => c_state(3),
- O => \FSM_sequential_c_state[1]_i_3_n_0\
- );
-\FSM_sequential_c_state[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0002A0A2AAAA0002"
- )
- port map (
- I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
- I1 => c_state(3),
- I2 => c_state(1),
- I3 => \FSM_sequential_c_state[2]_i_2_n_0\,
- I4 => c_state(2),
- I5 => c_state(0),
- O => \FSM_sequential_c_state[2]_i_1_n_0\
- );
-\FSM_sequential_c_state[2]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFEEF"
- )
- port map (
- I0 => c_state(0),
- I1 => \statemachine.core_cmd_reg[3]_0\(3),
- I2 => \statemachine.core_cmd_reg[3]_0\(1),
- I3 => \statemachine.core_cmd_reg[3]_0\(2),
- I4 => \statemachine.core_cmd_reg[3]_0\(0),
- O => \FSM_sequential_c_state[2]_i_2_n_0\
- );
-\FSM_sequential_c_state[3]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0AA8A0A800A800A8"
- )
- port map (
- I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
- I1 => \FSM_sequential_c_state[3]_i_3_n_0\,
- I2 => c_state(3),
- I3 => c_state(0),
- I4 => c_state(2),
- I5 => c_state(1),
- O => \FSM_sequential_c_state[3]_i_1_n_0\
- );
-\FSM_sequential_c_state[3]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"04"
- )
- port map (
- I0 => c_state(4),
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- O => \FSM_sequential_c_state[3]_i_2_n_0\
- );
-\FSM_sequential_c_state[3]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000000006"
- )
- port map (
- I0 => \statemachine.core_cmd_reg[3]_0\(3),
- I1 => \statemachine.core_cmd_reg[3]_0\(2),
- I2 => \statemachine.core_cmd_reg[3]_0\(0),
- I3 => \statemachine.core_cmd_reg[3]_0\(1),
- I4 => c_state(1),
- I5 => c_state(2),
- O => \FSM_sequential_c_state[3]_i_3_n_0\
- );
-\FSM_sequential_c_state[4]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"BBBBBBBFAAAAAAAA"
- )
- port map (
- I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
- I1 => c_state(4),
- I2 => c_state(3),
- I3 => c_state(1),
- I4 => c_state(2),
- I5 => clk_en,
- O => \FSM_sequential_c_state[4]_i_1_n_0\
- );
-\FSM_sequential_c_state[4]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000080FF8000"
- )
- port map (
- I0 => c_state(3),
- I1 => c_state(1),
- I2 => c_state(2),
- I3 => c_state(0),
- I4 => c_state(4),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \FSM_sequential_c_state[4]_i_2_n_0\
- );
-\FSM_sequential_c_state[4]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => i2c_al,
- I1 => s00_axi_aresetn,
- O => \FSM_sequential_c_state[4]_i_3_n_0\
- );
-\FSM_sequential_c_state_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[0]_i_1_n_0\,
- Q => c_state(0)
- );
-\FSM_sequential_c_state_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[1]_i_1_n_0\,
- Q => c_state(1)
- );
-\FSM_sequential_c_state_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[2]_i_1_n_0\,
- Q => c_state(2)
- );
-\FSM_sequential_c_state_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[3]_i_1_n_0\,
- Q => c_state(3)
- );
-\FSM_sequential_c_state_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \FSM_sequential_c_state[4]_i_2_n_0\,
- Q => c_state(4)
- );
-\FSM_sequential_statemachine.c_state[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \FSM_sequential_statemachine.c_state_reg[1]_1\,
- I1 => \out\(2),
- I2 => \out\(1),
- I3 => \cr_reg[7]\(2),
- I4 => \out\(0),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \FSM_sequential_statemachine.c_state_reg[2]\(0)
- );
-\FSM_sequential_statemachine.c_state[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000015100000"
- )
- port map (
- I0 => \out\(2),
- I1 => cnt_done,
- I2 => \out\(1),
- I3 => \cr_reg[7]_0\,
- I4 => s00_axi_aresetn,
- I5 => i2c_al,
- O => \FSM_sequential_statemachine.c_state_reg[2]\(1)
- );
-\FSM_sequential_statemachine.c_state[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"DDFFDDDDFFFDDDFD"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_al,
- I2 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
- I3 => \out\(1),
- I4 => core_ack,
- I5 => \out\(2),
- O => E(0)
- );
-\FSM_sequential_statemachine.c_state[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \FSM_sequential_statemachine.c_state_reg[1]_2\,
- I1 => \out\(2),
- I2 => \out\(1),
- I3 => \cr_reg[7]\(2),
- I4 => \out\(0),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \FSM_sequential_statemachine.c_state_reg[2]\(2)
- );
-\FSM_sequential_statemachine.c_state[2]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8B8B8B8B8B8B8B88"
- )
- port map (
- I0 => core_ack,
- I1 => \out\(0),
- I2 => cmd_ack,
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(1),
- I5 => \cr_reg[7]\(2),
- O => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\
- );
-\bus_status_ctrl.cSCL[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_scl_io,
- O => \bus_status_ctrl.cSCL[0]_i_1_n_0\
- );
-\bus_status_ctrl.cSCL[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \p_0_in__0\(1),
- O => \bus_status_ctrl.cSCL[1]_i_1_n_0\
- );
-\bus_status_ctrl.cSCL_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSCL[0]_i_1_n_0\,
- Q => \p_0_in__0\(1)
- );
-\bus_status_ctrl.cSCL_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSCL[1]_i_1_n_0\,
- Q => \p_0_in__1\(0)
- );
-\bus_status_ctrl.cSDA[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_sda_io,
- O => \bus_status_ctrl.cSDA[0]_i_1_n_0\
- );
-\bus_status_ctrl.cSDA[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => p_0_in(1),
- O => \bus_status_ctrl.cSDA[1]_i_1_n_0\
- );
-\bus_status_ctrl.cSDA_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSDA[0]_i_1_n_0\,
- Q => p_0_in(1)
- );
-\bus_status_ctrl.cSDA_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cSDA[1]_i_1_n_0\,
- Q => \bus_status_ctrl.cSDA_reg_n_0_[1]\
- );
-\bus_status_ctrl.cmd_stop_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"04FF000004000000"
- )
- port map (
- I0 => \statemachine.core_cmd_reg[3]_0\(0),
- I1 => \statemachine.core_cmd_reg[3]_0\(1),
- I2 => \bus_status_ctrl.cmd_stop_i_2_n_0\,
- I3 => clk_en,
- I4 => s00_axi_aresetn,
- I5 => \bus_status_ctrl.cmd_stop_reg_n_0\,
- O => \bus_status_ctrl.cmd_stop_i_1_n_0\
- );
-\bus_status_ctrl.cmd_stop_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => \statemachine.core_cmd_reg[3]_0\(2),
- I1 => \statemachine.core_cmd_reg[3]_0\(3),
- O => \bus_status_ctrl.cmd_stop_i_2_n_0\
- );
-\bus_status_ctrl.cmd_stop_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.cmd_stop_i_1_n_0\,
- Q => \bus_status_ctrl.cmd_stop_reg_n_0\
- );
-\bus_status_ctrl.dSCL_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => sSCL,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.dSCL_i_1_n_0\
- );
-\bus_status_ctrl.dSCL_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.dSCL_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => dSCL
- );
-\bus_status_ctrl.dSDA_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => sSDA,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.dSDA_i_1_n_0\
- );
-\bus_status_ctrl.dSDA_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.dSDA_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => dSDA
- );
-\bus_status_ctrl.dout_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FB08"
- )
- port map (
- I0 => sSDA,
- I1 => sSCL,
- I2 => dSCL,
- I3 => core_rxd,
- O => \bus_status_ctrl.dout_i_1_n_0\
- );
-\bus_status_ctrl.dout_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.dout_i_1_n_0\,
- Q => core_rxd
- );
-\bus_status_ctrl.fSCL[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \p_0_in__1\(0),
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSCL[0]_i_1_n_0\
- );
-\bus_status_ctrl.fSCL[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \p_0_in__1\(1),
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSCL[1]_i_1_n_0\
- );
-\bus_status_ctrl.fSCL[2]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \p_0_in__1\(2),
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSCL[2]_i_1_n_0\
- );
-\bus_status_ctrl.fSCL_reg[0]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSCL[0]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \p_0_in__1\(1)
- );
-\bus_status_ctrl.fSCL_reg[1]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSCL[1]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \p_0_in__1\(2)
- );
-\bus_status_ctrl.fSCL_reg[2]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSCL[2]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSCL_reg_n_0_[2]\
- );
-\bus_status_ctrl.fSDA[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.cSDA_reg_n_0_[1]\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[0]_i_1_n_0\
- );
-\bus_status_ctrl.fSDA[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[1]_i_1_n_0\
- );
-\bus_status_ctrl.fSDA[2]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[2]_i_1_n_0\
- );
-\bus_status_ctrl.fSDA[2]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
- I1 => s00_axi_aresetn,
- O => \bus_status_ctrl.fSDA[2]_i_2_n_0\
- );
-\bus_status_ctrl.fSDA_reg[0]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSDA[0]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSDA_reg_n_0_[0]\
- );
-\bus_status_ctrl.fSDA_reg[1]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSDA[1]_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSDA_reg_n_0_[1]\
- );
-\bus_status_ctrl.fSDA_reg[2]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
- D => \bus_status_ctrl.fSDA[2]_i_2_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => \bus_status_ctrl.fSDA_reg_n_0_[2]\
- );
-\bus_status_ctrl.filter_cnt[0]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"D1000000"
- )
- port map (
- I0 => filter_cnt(0),
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(2),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[10]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_6\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(12),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[11]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_5\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(13),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[12]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_4\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(14),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__2_n_7\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(15),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000000001"
- )
- port map (
- I0 => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\,
- I2 => filter_cnt(6),
- I3 => filter_cnt(7),
- I4 => filter_cnt(4),
- I5 => filter_cnt(5),
- O => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFE"
- )
- port map (
- I0 => filter_cnt(13),
- I1 => filter_cnt(12),
- I2 => filter_cnt(9),
- I3 => filter_cnt(8),
- I4 => filter_cnt(11),
- I5 => filter_cnt(10),
- O => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\
- );
-\bus_status_ctrl.filter_cnt[13]_i_4\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => filter_cnt(2),
- I1 => filter_cnt(3),
- I2 => filter_cnt(0),
- I3 => filter_cnt(1),
- O => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\
- );
-\bus_status_ctrl.filter_cnt[1]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_7,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(3),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[2]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_6,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(4),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[3]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_5,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(5),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[4]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => minusOp_carry_n_4,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(6),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[5]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_7\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(7),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[6]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_6\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(8),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_5\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(9),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[8]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__0_n_4\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(10),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt[9]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"E2000000"
- )
- port map (
- I0 => \minusOp_carry__1_n_7\,
- I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
- I2 => Q(11),
- I3 => \ctr_reg[7]\(0),
- I4 => s00_axi_aresetn,
- O => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\
- );
-\bus_status_ctrl.filter_cnt_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\,
- Q => filter_cnt(0)
- );
-\bus_status_ctrl.filter_cnt_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\,
- Q => filter_cnt(10)
- );
-\bus_status_ctrl.filter_cnt_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\,
- Q => filter_cnt(11)
- );
-\bus_status_ctrl.filter_cnt_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\,
- Q => filter_cnt(12)
- );
-\bus_status_ctrl.filter_cnt_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\,
- Q => filter_cnt(13)
- );
-\bus_status_ctrl.filter_cnt_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\,
- Q => filter_cnt(1)
- );
-\bus_status_ctrl.filter_cnt_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\,
- Q => filter_cnt(2)
- );
-\bus_status_ctrl.filter_cnt_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\,
- Q => filter_cnt(3)
- );
-\bus_status_ctrl.filter_cnt_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\,
- Q => filter_cnt(4)
- );
-\bus_status_ctrl.filter_cnt_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\,
- Q => filter_cnt(5)
- );
-\bus_status_ctrl.filter_cnt_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\,
- Q => filter_cnt(6)
- );
-\bus_status_ctrl.filter_cnt_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\,
- Q => filter_cnt(7)
- );
-\bus_status_ctrl.filter_cnt_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\,
- Q => filter_cnt(8)
- );
-\bus_status_ctrl.filter_cnt_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\,
- Q => filter_cnt(9)
- );
-\bus_status_ctrl.ial_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"08000800AAAA0800"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => sda_chk_reg_n_0,
- I2 => sSDA,
- I3 => sda_padoen_o,
- I4 => \bus_status_ctrl.ial_i_2_n_0\,
- I5 => \bus_status_ctrl.ial_i_3_n_0\,
- O => ial
- );
-\bus_status_ctrl.ial_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => c_state(0),
- I1 => c_state(4),
- O => \bus_status_ctrl.ial_i_2_n_0\
- );
-\bus_status_ctrl.ial_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFEF"
- )
- port map (
- I0 => c_state(2),
- I1 => c_state(3),
- I2 => \bus_status_ctrl.sto_condition_reg_n_0\,
- I3 => \bus_status_ctrl.cmd_stop_reg_n_0\,
- I4 => c_state(1),
- O => \bus_status_ctrl.ial_i_3_n_0\
- );
-\bus_status_ctrl.ial_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => ial,
- Q => i2c_al
- );
-\bus_status_ctrl.ibusy_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"5400"
- )
- port map (
- I0 => \bus_status_ctrl.sto_condition_reg_n_0\,
- I1 => \bus_status_ctrl.sta_condition_reg_n_0\,
- I2 => i2c_busy,
- I3 => s00_axi_aresetn,
- O => ibusy
- );
-\bus_status_ctrl.ibusy_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => ibusy,
- Q => i2c_busy
- );
-\bus_status_ctrl.sSCL_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E8FF"
- )
- port map (
- I0 => \p_0_in__1\(2),
- I1 => \bus_status_ctrl.fSCL_reg_n_0_[2]\,
- I2 => \p_0_in__1\(1),
- I3 => s00_axi_aresetn,
- O => \bus_status_ctrl.sSCL_i_1_n_0\
- );
-\bus_status_ctrl.sSCL_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.sSCL_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => sSCL
- );
-\bus_status_ctrl.sSDA_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E8FF"
- )
- port map (
- I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
- I1 => \bus_status_ctrl.fSDA_reg_n_0_[2]\,
- I2 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
- I3 => s00_axi_aresetn,
- O => \bus_status_ctrl.sSDA_i_1_n_0\
- );
-\bus_status_ctrl.sSDA_reg\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \bus_status_ctrl.sSDA_i_1_n_0\,
- PRE => \^iscl_oen_reg_0\,
- Q => sSDA
- );
-\bus_status_ctrl.sta_condition_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"2000"
- )
- port map (
- I0 => dSDA,
- I1 => sSDA,
- I2 => s00_axi_aresetn,
- I3 => sSCL,
- O => sta_condition
- );
-\bus_status_ctrl.sta_condition_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => sta_condition,
- Q => \bus_status_ctrl.sta_condition_reg_n_0\
- );
-\bus_status_ctrl.sto_condition_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4000"
- )
- port map (
- I0 => dSDA,
- I1 => s00_axi_aresetn,
- I2 => sSCL,
- I3 => sSDA,
- O => sto_condition
- );
-\bus_status_ctrl.sto_condition_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => sto_condition,
- Q => \bus_status_ctrl.sto_condition_reg_n_0\
- );
-clk_en_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AAAAAAAB"
- )
- port map (
- I0 => clk_en_i_2_n_0,
- I1 => clk_en_i_3_n_0,
- I2 => clk_en_i_4_n_0,
- I3 => clk_en_i_5_n_0,
- I4 => clk_en_i_6_n_0,
- O => cnt1
- );
-clk_en_i_2: unisim.vcomponents.LUT5
- generic map(
- INIT => X"7555FFFF"
- )
- port map (
- I0 => \ctr_reg[7]\(0),
- I1 => sSCL,
- I2 => scl_padoen_o,
- I3 => dSCL,
- I4 => s00_axi_aresetn,
- O => clk_en_i_2_n_0
- );
-clk_en_i_3: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(6),
- I1 => cnt_reg(7),
- I2 => cnt_reg(4),
- I3 => cnt_reg(5),
- O => clk_en_i_3_n_0
- );
-clk_en_i_4: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(2),
- I1 => cnt_reg(3),
- I2 => cnt_reg(0),
- I3 => cnt_reg(1),
- O => clk_en_i_4_n_0
- );
-clk_en_i_5: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(15),
- I1 => cnt_reg(14),
- I2 => cnt_reg(12),
- I3 => cnt_reg(13),
- O => clk_en_i_5_n_0
- );
-clk_en_i_6: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => cnt_reg(10),
- I1 => cnt_reg(11),
- I2 => cnt_reg(8),
- I3 => cnt_reg(9),
- O => clk_en_i_6_n_0
- );
-clk_en_reg: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cnt1,
- PRE => \^iscl_oen_reg_0\,
- Q => clk_en
- );
-cmd_ack_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0008000000000000"
- )
- port map (
- I0 => cmd_ack_i_2_n_0,
- I1 => c_state(0),
- I2 => c_state(1),
- I3 => i2c_al,
- I4 => s00_axi_aresetn,
- I5 => clk_en,
- O => cmd_ack3_out
- );
-cmd_ack_i_2: unisim.vcomponents.LUT3
- generic map(
- INIT => X"1E"
- )
- port map (
- I0 => c_state(2),
- I1 => c_state(3),
- I2 => c_state(4),
- O => cmd_ack_i_2_n_0
- );
-cmd_ack_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => cmd_ack3_out,
- Q => core_ack
- );
-\cnt[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => cnt1,
- I1 => slave_wait,
- O => \cnt[0]_i_1_n_0\
- );
-\cnt[0]_i_10\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(0),
- I1 => Q(0),
- I2 => cnt1,
- O => \cnt[0]_i_10_n_0\
- );
-\cnt[0]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(3),
- I1 => cnt1,
- I2 => cnt_reg(3),
- O => \cnt[0]_i_3_n_0\
- );
-\cnt[0]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(2),
- I1 => cnt1,
- I2 => cnt_reg(2),
- O => \cnt[0]_i_4_n_0\
- );
-\cnt[0]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(1),
- I1 => cnt1,
- I2 => cnt_reg(1),
- O => \cnt[0]_i_5_n_0\
- );
-\cnt[0]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(0),
- I1 => cnt1,
- I2 => cnt_reg(0),
- O => \cnt[0]_i_6_n_0\
- );
-\cnt[0]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(3),
- I1 => Q(3),
- I2 => cnt1,
- O => \cnt[0]_i_7_n_0\
- );
-\cnt[0]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(2),
- I1 => Q(2),
- I2 => cnt1,
- O => \cnt[0]_i_8_n_0\
- );
-\cnt[0]_i_9\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(1),
- I1 => Q(1),
- I2 => cnt1,
- O => \cnt[0]_i_9_n_0\
- );
-\cnt[12]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(14),
- I1 => cnt1,
- I2 => cnt_reg(14),
- O => \cnt[12]_i_2_n_0\
- );
-\cnt[12]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(13),
- I1 => cnt1,
- I2 => cnt_reg(13),
- O => \cnt[12]_i_3_n_0\
- );
-\cnt[12]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(12),
- I1 => cnt1,
- I2 => cnt_reg(12),
- O => \cnt[12]_i_4_n_0\
- );
-\cnt[12]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(15),
- I1 => Q(15),
- I2 => cnt1,
- O => \cnt[12]_i_5_n_0\
- );
-\cnt[12]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(14),
- I1 => Q(14),
- I2 => cnt1,
- O => \cnt[12]_i_6_n_0\
- );
-\cnt[12]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(13),
- I1 => Q(13),
- I2 => cnt1,
- O => \cnt[12]_i_7_n_0\
- );
-\cnt[12]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(12),
- I1 => Q(12),
- I2 => cnt1,
- O => \cnt[12]_i_8_n_0\
- );
-\cnt[4]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(7),
- I1 => cnt1,
- I2 => cnt_reg(7),
- O => \cnt[4]_i_2_n_0\
- );
-\cnt[4]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(6),
- I1 => cnt1,
- I2 => cnt_reg(6),
- O => \cnt[4]_i_3_n_0\
- );
-\cnt[4]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(5),
- I1 => cnt1,
- I2 => cnt_reg(5),
- O => \cnt[4]_i_4_n_0\
- );
-\cnt[4]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(4),
- I1 => cnt1,
- I2 => cnt_reg(4),
- O => \cnt[4]_i_5_n_0\
- );
-\cnt[4]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(7),
- I1 => Q(7),
- I2 => cnt1,
- O => \cnt[4]_i_6_n_0\
- );
-\cnt[4]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(6),
- I1 => Q(6),
- I2 => cnt1,
- O => \cnt[4]_i_7_n_0\
- );
-\cnt[4]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(5),
- I1 => Q(5),
- I2 => cnt1,
- O => \cnt[4]_i_8_n_0\
- );
-\cnt[4]_i_9\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(4),
- I1 => Q(4),
- I2 => cnt1,
- O => \cnt[4]_i_9_n_0\
- );
-\cnt[8]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(11),
- I1 => cnt1,
- I2 => cnt_reg(11),
- O => \cnt[8]_i_2_n_0\
- );
-\cnt[8]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(10),
- I1 => cnt1,
- I2 => cnt_reg(10),
- O => \cnt[8]_i_3_n_0\
- );
-\cnt[8]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(9),
- I1 => cnt1,
- I2 => cnt_reg(9),
- O => \cnt[8]_i_4_n_0\
- );
-\cnt[8]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => Q(8),
- I1 => cnt1,
- I2 => cnt_reg(8),
- O => \cnt[8]_i_5_n_0\
- );
-\cnt[8]_i_6\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(11),
- I1 => Q(11),
- I2 => cnt1,
- O => \cnt[8]_i_6_n_0\
- );
-\cnt[8]_i_7\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(10),
- I1 => Q(10),
- I2 => cnt1,
- O => \cnt[8]_i_7_n_0\
- );
-\cnt[8]_i_8\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(9),
- I1 => Q(9),
- I2 => cnt1,
- O => \cnt[8]_i_8_n_0\
- );
-\cnt[8]_i_9\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"C5"
- )
- port map (
- I0 => cnt_reg(8),
- I1 => Q(8),
- I2 => cnt1,
- O => \cnt[8]_i_9_n_0\
- );
-\cnt_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_7\,
- Q => cnt_reg(0)
- );
-\cnt_reg[0]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \cnt_reg[0]_i_2_n_0\,
- CO(2) => \cnt_reg[0]_i_2_n_1\,
- CO(1) => \cnt_reg[0]_i_2_n_2\,
- CO(0) => \cnt_reg[0]_i_2_n_3\,
- CYINIT => '0',
- DI(3) => \cnt[0]_i_3_n_0\,
- DI(2) => \cnt[0]_i_4_n_0\,
- DI(1) => \cnt[0]_i_5_n_0\,
- DI(0) => \cnt[0]_i_6_n_0\,
- O(3) => \cnt_reg[0]_i_2_n_4\,
- O(2) => \cnt_reg[0]_i_2_n_5\,
- O(1) => \cnt_reg[0]_i_2_n_6\,
- O(0) => \cnt_reg[0]_i_2_n_7\,
- S(3) => \cnt[0]_i_7_n_0\,
- S(2) => \cnt[0]_i_8_n_0\,
- S(1) => \cnt[0]_i_9_n_0\,
- S(0) => \cnt[0]_i_10_n_0\
- );
-\cnt_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_5\,
- Q => cnt_reg(10)
- );
-\cnt_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_4\,
- Q => cnt_reg(11)
- );
-\cnt_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_7\,
- Q => cnt_reg(12)
- );
-\cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \cnt_reg[8]_i_1_n_0\,
- CO(3) => \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\(3),
- CO(2) => \cnt_reg[12]_i_1_n_1\,
- CO(1) => \cnt_reg[12]_i_1_n_2\,
- CO(0) => \cnt_reg[12]_i_1_n_3\,
- CYINIT => '0',
- DI(3) => '0',
- DI(2) => \cnt[12]_i_2_n_0\,
- DI(1) => \cnt[12]_i_3_n_0\,
- DI(0) => \cnt[12]_i_4_n_0\,
- O(3) => \cnt_reg[12]_i_1_n_4\,
- O(2) => \cnt_reg[12]_i_1_n_5\,
- O(1) => \cnt_reg[12]_i_1_n_6\,
- O(0) => \cnt_reg[12]_i_1_n_7\,
- S(3) => \cnt[12]_i_5_n_0\,
- S(2) => \cnt[12]_i_6_n_0\,
- S(1) => \cnt[12]_i_7_n_0\,
- S(0) => \cnt[12]_i_8_n_0\
- );
-\cnt_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_6\,
- Q => cnt_reg(13)
- );
-\cnt_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_5\,
- Q => cnt_reg(14)
- );
-\cnt_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[12]_i_1_n_4\,
- Q => cnt_reg(15)
- );
-\cnt_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_6\,
- Q => cnt_reg(1)
- );
-\cnt_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_5\,
- Q => cnt_reg(2)
- );
-\cnt_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[0]_i_2_n_4\,
- Q => cnt_reg(3)
- );
-\cnt_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_7\,
- Q => cnt_reg(4)
- );
-\cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \cnt_reg[0]_i_2_n_0\,
- CO(3) => \cnt_reg[4]_i_1_n_0\,
- CO(2) => \cnt_reg[4]_i_1_n_1\,
- CO(1) => \cnt_reg[4]_i_1_n_2\,
- CO(0) => \cnt_reg[4]_i_1_n_3\,
- CYINIT => '0',
- DI(3) => \cnt[4]_i_2_n_0\,
- DI(2) => \cnt[4]_i_3_n_0\,
- DI(1) => \cnt[4]_i_4_n_0\,
- DI(0) => \cnt[4]_i_5_n_0\,
- O(3) => \cnt_reg[4]_i_1_n_4\,
- O(2) => \cnt_reg[4]_i_1_n_5\,
- O(1) => \cnt_reg[4]_i_1_n_6\,
- O(0) => \cnt_reg[4]_i_1_n_7\,
- S(3) => \cnt[4]_i_6_n_0\,
- S(2) => \cnt[4]_i_7_n_0\,
- S(1) => \cnt[4]_i_8_n_0\,
- S(0) => \cnt[4]_i_9_n_0\
- );
-\cnt_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_6\,
- Q => cnt_reg(5)
- );
-\cnt_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_5\,
- Q => cnt_reg(6)
- );
-\cnt_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[4]_i_1_n_4\,
- Q => cnt_reg(7)
- );
-\cnt_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_7\,
- Q => cnt_reg(8)
- );
-\cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \cnt_reg[4]_i_1_n_0\,
- CO(3) => \cnt_reg[8]_i_1_n_0\,
- CO(2) => \cnt_reg[8]_i_1_n_1\,
- CO(1) => \cnt_reg[8]_i_1_n_2\,
- CO(0) => \cnt_reg[8]_i_1_n_3\,
- CYINIT => '0',
- DI(3) => \cnt[8]_i_2_n_0\,
- DI(2) => \cnt[8]_i_3_n_0\,
- DI(1) => \cnt[8]_i_4_n_0\,
- DI(0) => \cnt[8]_i_5_n_0\,
- O(3) => \cnt_reg[8]_i_1_n_4\,
- O(2) => \cnt_reg[8]_i_1_n_5\,
- O(1) => \cnt_reg[8]_i_1_n_6\,
- O(0) => \cnt_reg[8]_i_1_n_7\,
- S(3) => \cnt[8]_i_6_n_0\,
- S(2) => \cnt[8]_i_7_n_0\,
- S(1) => \cnt[8]_i_8_n_0\,
- S(0) => \cnt[8]_i_9_n_0\
- );
-\cnt_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \cnt[0]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => \cnt_reg[8]_i_1_n_6\,
- Q => cnt_reg(9)
- );
-\cr[7]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"55FDFDFDFFFFFFFF"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_al,
- I2 => cmd_ack,
- I3 => iack_o_reg,
- I4 => wb_we_o,
- I5 => iack_o_reg_0,
- O => \cr_reg[4]\(0)
- );
-dscl_oen_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => scl_padoen_o,
- Q => dscl_oen
- );
-i2c_scl_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_scl_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_scl_io
- );
-i2c_scl_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => scl_padoen_o,
- O => i2c_scl_io_INST_0_i_1_n_0
- );
-i2c_sda_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_sda_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_sda_io
- );
-i2c_sda_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => sda_padoen_o,
- O => i2c_sda_io_INST_0_i_1_n_0
- );
-iscl_oen_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FBFFFBF3"
- )
- port map (
- I0 => iscl_oen,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- I3 => \iscl_oen9_out__0\,
- I4 => scl_padoen_o,
- O => iscl_oen_i_1_n_0
- );
-iscl_oen_i_2: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00F3011F"
- )
- port map (
- I0 => c_state(3),
- I1 => c_state(2),
- I2 => c_state(1),
- I3 => c_state(4),
- I4 => c_state(0),
- O => iscl_oen
- );
-iscl_oen_i_3: unisim.vcomponents.LUT5
- generic map(
- INIT => X"55560000"
- )
- port map (
- I0 => c_state(4),
- I1 => c_state(3),
- I2 => c_state(2),
- I3 => c_state(1),
- I4 => clk_en,
- O => \iscl_oen9_out__0\
- );
-iscl_oen_reg: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => iscl_oen_i_1_n_0,
- PRE => \^iscl_oen_reg_0\,
- Q => scl_padoen_o
- );
-isda_oen_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FBFFFBF3"
- )
- port map (
- I0 => isda_oen,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- I3 => \isda_oen7_out__0\,
- I4 => sda_padoen_o,
- O => isda_oen_i_1_n_0
- );
-isda_oen_i_2: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000C8CB03038F83"
- )
- port map (
- I0 => \statemachine.core_txd_reg_0\,
- I1 => c_state(3),
- I2 => c_state(2),
- I3 => c_state(0),
- I4 => c_state(4),
- I5 => c_state(1),
- O => isda_oen
- );
-isda_oen_i_3: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0F0F1F1E00000000"
- )
- port map (
- I0 => c_state(1),
- I1 => c_state(2),
- I2 => c_state(4),
- I3 => c_state(0),
- I4 => c_state(3),
- I5 => clk_en,
- O => \isda_oen7_out__0\
- );
-isda_oen_reg: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => isda_oen_i_1_n_0,
- PRE => \^iscl_oen_reg_0\,
- Q => sda_padoen_o
- );
-minusOp_carry: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => minusOp_carry_n_0,
- CO(2) => minusOp_carry_n_1,
- CO(1) => minusOp_carry_n_2,
- CO(0) => minusOp_carry_n_3,
- CYINIT => filter_cnt(0),
- DI(3 downto 0) => filter_cnt(4 downto 1),
- O(3) => minusOp_carry_n_4,
- O(2) => minusOp_carry_n_5,
- O(1) => minusOp_carry_n_6,
- O(0) => minusOp_carry_n_7,
- S(3) => minusOp_carry_i_1_n_0,
- S(2) => minusOp_carry_i_2_n_0,
- S(1) => minusOp_carry_i_3_n_0,
- S(0) => minusOp_carry_i_4_n_0
- );
-\minusOp_carry__0\: unisim.vcomponents.CARRY4
- port map (
- CI => minusOp_carry_n_0,
- CO(3) => \minusOp_carry__0_n_0\,
- CO(2) => \minusOp_carry__0_n_1\,
- CO(1) => \minusOp_carry__0_n_2\,
- CO(0) => \minusOp_carry__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => filter_cnt(8 downto 5),
- O(3) => \minusOp_carry__0_n_4\,
- O(2) => \minusOp_carry__0_n_5\,
- O(1) => \minusOp_carry__0_n_6\,
- O(0) => \minusOp_carry__0_n_7\,
- S(3) => \minusOp_carry__0_i_1_n_0\,
- S(2) => \minusOp_carry__0_i_2_n_0\,
- S(1) => \minusOp_carry__0_i_3_n_0\,
- S(0) => \minusOp_carry__0_i_4_n_0\
- );
-\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(8),
- O => \minusOp_carry__0_i_1_n_0\
- );
-\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(7),
- O => \minusOp_carry__0_i_2_n_0\
- );
-\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(6),
- O => \minusOp_carry__0_i_3_n_0\
- );
-\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(5),
- O => \minusOp_carry__0_i_4_n_0\
- );
-\minusOp_carry__1\: unisim.vcomponents.CARRY4
- port map (
- CI => \minusOp_carry__0_n_0\,
- CO(3) => \minusOp_carry__1_n_0\,
- CO(2) => \minusOp_carry__1_n_1\,
- CO(1) => \minusOp_carry__1_n_2\,
- CO(0) => \minusOp_carry__1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => filter_cnt(12 downto 9),
- O(3) => \minusOp_carry__1_n_4\,
- O(2) => \minusOp_carry__1_n_5\,
- O(1) => \minusOp_carry__1_n_6\,
- O(0) => \minusOp_carry__1_n_7\,
- S(3) => \minusOp_carry__1_i_1_n_0\,
- S(2) => \minusOp_carry__1_i_2_n_0\,
- S(1) => \minusOp_carry__1_i_3_n_0\,
- S(0) => \minusOp_carry__1_i_4_n_0\
- );
-\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(12),
- O => \minusOp_carry__1_i_1_n_0\
- );
-\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(11),
- O => \minusOp_carry__1_i_2_n_0\
- );
-\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(10),
- O => \minusOp_carry__1_i_3_n_0\
- );
-\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(9),
- O => \minusOp_carry__1_i_4_n_0\
- );
-\minusOp_carry__2\: unisim.vcomponents.CARRY4
- port map (
- CI => \minusOp_carry__1_n_0\,
- CO(3 downto 0) => \NLW_minusOp_carry__2_CO_UNCONNECTED\(3 downto 0),
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 1) => \NLW_minusOp_carry__2_O_UNCONNECTED\(3 downto 1),
- O(0) => \minusOp_carry__2_n_7\,
- S(3 downto 1) => B"000",
- S(0) => \minusOp_carry__2_i_1_n_0\
- );
-\minusOp_carry__2_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(13),
- O => \minusOp_carry__2_i_1_n_0\
- );
-minusOp_carry_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(4),
- O => minusOp_carry_i_1_n_0
- );
-minusOp_carry_i_2: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(3),
- O => minusOp_carry_i_2_n_0
- );
-minusOp_carry_i_3: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(2),
- O => minusOp_carry_i_3_n_0
- );
-minusOp_carry_i_4: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => filter_cnt(1),
- O => minusOp_carry_i_4_n_0
- );
-sda_chk_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000100000"
- )
- port map (
- I0 => c_state(4),
- I1 => c_state(1),
- I2 => c_state(3),
- I3 => c_state(0),
- I4 => c_state(2),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => sda_chk_i_1_n_0
- );
-sda_chk_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => \FSM_sequential_c_state[4]_i_1_n_0\,
- CLR => \^iscl_oen_reg_0\,
- D => sda_chk_i_1_n_0,
- Q => sda_chk_reg_n_0
- );
-slave_wait_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0F04"
- )
- port map (
- I0 => dscl_oen,
- I1 => scl_padoen_o,
- I2 => sSCL,
- I3 => slave_wait,
- O => slave_wait0
- );
-slave_wait_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg_0\,
- D => slave_wait0,
- Q => slave_wait
- );
-\sr[0]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_0\,
- I1 => core_rxd,
- I2 => \txr_reg[6]\(0),
- I3 => s00_axi_aresetn,
- O => \sr_reg[0]\(0)
- );
-\st_irq_block.al_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"AA08"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \st_irq_block.al_reg\,
- I2 => \cr_reg[7]\(3),
- I3 => i2c_al,
- O => al
- );
-\st_irq_block.irq_flag_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"55540000"
- )
- port map (
- I0 => \cr_reg[0]\,
- I1 => i2c_al,
- I2 => cmd_ack,
- I3 => irq_flag,
- I4 => s00_axi_aresetn,
- O => irq_flag1_out
- );
-\st_irq_block.wb_inta_o_i_2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s00_axi_aresetn,
- O => \^iscl_oen_reg_0\
- );
-\statemachine.ack_out_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"08FF0800"
- )
- port map (
- I0 => core_rxd,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- I3 => \statemachine.ack_out_i_2_n_0\,
- I4 => ack_out,
- O => \statemachine.ack_out_reg\
- );
-\statemachine.ack_out_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"DDDDDDDDDDFDDDDD"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => i2c_al,
- I2 => \out\(2),
- I3 => \out\(0),
- I4 => core_ack,
- I5 => \out\(1),
- O => \statemachine.ack_out_i_2_n_0\
- );
-\statemachine.core_cmd[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000000100000"
- )
- port map (
- I0 => \out\(2),
- I1 => \out\(0),
- I2 => \cr_reg[7]\(3),
- I3 => \out\(1),
- I4 => s00_axi_aresetn,
- I5 => i2c_al,
- O => \statemachine.core_cmd_reg[3]\(0)
- );
-\statemachine.core_cmd[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \FSM_sequential_statemachine.c_state_reg[1]_0\,
- I1 => \out\(2),
- I2 => \out\(1),
- I3 => \cr_reg[7]\(2),
- I4 => \out\(0),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \statemachine.core_cmd_reg[3]\(1)
- );
-\statemachine.core_cmd[2]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => core_cmd(0),
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- O => \statemachine.core_cmd_reg[3]\(2)
- );
-\statemachine.core_cmd[3]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0040"
- )
- port map (
- I0 => \out\(2),
- I1 => \FSM_sequential_statemachine.c_state_reg[1]\,
- I2 => s00_axi_aresetn,
- I3 => i2c_al,
- O => \statemachine.core_cmd_reg[3]\(3)
- );
-\statemachine.core_txd_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => core_txd,
- I1 => s00_axi_aresetn,
- I2 => i2c_al,
- O => \statemachine.core_txd_reg\
- );
-\statemachine.core_txd_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"5455FFFD10002220"
- )
- port map (
- I0 => \out\(2),
- I1 => \out\(0),
- I2 => ack_in,
- I3 => core_ack,
- I4 => \out\(1),
- I5 => \sr_reg[7]\(0),
- O => core_txd
- );
-\statemachine.host_ack_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000000000A020"
- )
- port map (
- I0 => \out\(2),
- I1 => \cr_reg[7]\(2),
- I2 => core_ack,
- I3 => \out\(0),
- I4 => \out\(1),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \statemachine.host_ack_reg\
- );
-\statemachine.ld_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00000400"
- )
- port map (
- I0 => \out\(2),
- I1 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
- I2 => \out\(1),
- I3 => s00_axi_aresetn,
- I4 => i2c_al,
- O => \statemachine.ld_reg\
- );
-\statemachine.shift_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000004440000"
- )
- port map (
- I0 => \out\(2),
- I1 => core_ack,
- I2 => \out\(0),
- I3 => cnt_done,
- I4 => \out\(1),
- I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
- O => \statemachine.shift_reg\
- );
-\wb_dat_o[6]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \cr_reg[7]\(2),
- I1 => wb_adr_o(1),
- I2 => \txr_reg[6]\(1),
- I3 => wb_adr_o(0),
- I4 => i2c_busy,
- O => \wb_dat_o[6]_i_3_n_0\
- );
-\wb_dat_o_reg[6]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \sr_reg[6]\,
- I1 => \wb_dat_o[6]_i_3_n_0\,
- O => D(0),
- S => wb_adr_o(2)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl is
- port (
- iscl_oen_reg : out STD_LOGIC;
- irq_flag1_out : out STD_LOGIC;
- rxack_0 : out STD_LOGIC;
- al : out STD_LOGIC;
- D : out STD_LOGIC_VECTOR ( 7 downto 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \cr_reg[0]\ : in STD_LOGIC;
- irq_flag : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
- \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
- \st_irq_block.al_reg\ : in STD_LOGIC;
- \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \cr_reg[0]_0\ : in STD_LOGIC;
- \cr_reg[1]\ : in STD_LOGIC;
- \cr_reg[2]\ : in STD_LOGIC;
- \txr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
- ack_in : in STD_LOGIC;
- \cr_reg[5]\ : in STD_LOGIC;
- \cr_reg[7]_0\ : in STD_LOGIC;
- iack_o_reg : in STD_LOGIC;
- wb_we_o : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl : entity is "i2c_master_byte_ctrl";
-end system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl is
- signal \FSM_sequential_statemachine.c_state[0]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_statemachine.c_state[1]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_statemachine.c_state[2]_i_4_n_0\ : STD_LOGIC;
- signal ack_out : STD_LOGIC;
- signal bit_ctrl_n_10 : STD_LOGIC;
- signal bit_ctrl_n_11 : STD_LOGIC;
- signal bit_ctrl_n_12 : STD_LOGIC;
- signal bit_ctrl_n_13 : STD_LOGIC;
- signal bit_ctrl_n_15 : STD_LOGIC;
- signal bit_ctrl_n_16 : STD_LOGIC;
- signal bit_ctrl_n_17 : STD_LOGIC;
- signal bit_ctrl_n_18 : STD_LOGIC;
- signal bit_ctrl_n_5 : STD_LOGIC;
- signal bit_ctrl_n_6 : STD_LOGIC;
- signal bit_ctrl_n_7 : STD_LOGIC;
- signal bit_ctrl_n_8 : STD_LOGIC;
- signal bit_ctrl_n_9 : STD_LOGIC;
- signal c_state : STD_LOGIC;
- signal \c_state__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute RTL_KEEP : string;
- attribute RTL_KEEP of \c_state__0\ : signal is "yes";
- signal cmd : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal cmd_ack : STD_LOGIC;
- signal cnt_done : STD_LOGIC;
- signal core_cmd : STD_LOGIC_VECTOR ( 2 to 2 );
- signal dcnt : STD_LOGIC;
- signal \dcnt[0]_i_1_n_0\ : STD_LOGIC;
- signal \dcnt[1]_i_1_n_0\ : STD_LOGIC;
- signal \dcnt[2]_i_1_n_0\ : STD_LOGIC;
- signal \dcnt_reg_n_0_[0]\ : STD_LOGIC;
- signal \dcnt_reg_n_0_[1]\ : STD_LOGIC;
- signal \dcnt_reg_n_0_[2]\ : STD_LOGIC;
- signal dout : STD_LOGIC_VECTOR ( 7 to 7 );
- signal \^iscl_oen_reg\ : STD_LOGIC;
- signal \sr[1]_i_1_n_0\ : STD_LOGIC;
- signal \sr[2]_i_1_n_0\ : STD_LOGIC;
- signal \sr[3]_i_1_n_0\ : STD_LOGIC;
- signal \sr[4]_i_1_n_0\ : STD_LOGIC;
- signal \sr[5]_i_1_n_0\ : STD_LOGIC;
- signal \sr[6]_i_1_n_0\ : STD_LOGIC;
- signal \sr[7]_i_2_n_0\ : STD_LOGIC;
- signal \sr_reg_n_0_[0]\ : STD_LOGIC;
- signal \sr_reg_n_0_[1]\ : STD_LOGIC;
- signal \sr_reg_n_0_[2]\ : STD_LOGIC;
- signal \sr_reg_n_0_[3]\ : STD_LOGIC;
- signal \sr_reg_n_0_[4]\ : STD_LOGIC;
- signal \sr_reg_n_0_[5]\ : STD_LOGIC;
- signal \sr_reg_n_0_[6]\ : STD_LOGIC;
- signal \statemachine.core_cmd[1]_i_2_n_0\ : STD_LOGIC;
- signal \statemachine.core_cmd[3]_i_2_n_0\ : STD_LOGIC;
- signal \statemachine.core_txd_reg_n_0\ : STD_LOGIC;
- signal \statemachine.ld_reg_n_0\ : STD_LOGIC;
- signal \statemachine.shift_reg_n_0\ : STD_LOGIC;
- signal \wb_dat_o[0]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[1]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[2]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[3]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[4]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[5]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[6]_i_2_n_0\ : STD_LOGIC;
- signal \wb_dat_o[7]_i_2_n_0\ : STD_LOGIC;
- attribute KEEP : string;
- attribute KEEP of \FSM_sequential_statemachine.c_state_reg[0]\ : label is "yes";
- attribute KEEP of \FSM_sequential_statemachine.c_state_reg[1]\ : label is "yes";
- attribute KEEP of \FSM_sequential_statemachine.c_state_reg[2]\ : label is "yes";
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair23";
-begin
- iscl_oen_reg <= \^iscl_oen_reg\;
-\FSM_sequential_statemachine.c_state[0]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"43407373"
- )
- port map (
- I0 => cnt_done,
- I1 => \c_state__0\(1),
- I2 => \c_state__0\(0),
- I3 => \cr_reg[7]\(3),
- I4 => \cr_reg[7]\(1),
- O => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\
- );
-\FSM_sequential_statemachine.c_state[1]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"01"
- )
- port map (
- I0 => \dcnt_reg_n_0_[1]\,
- I1 => \dcnt_reg_n_0_[0]\,
- I2 => \dcnt_reg_n_0_[2]\,
- O => cnt_done
- );
-\FSM_sequential_statemachine.c_state[1]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FF54"
- )
- port map (
- I0 => \cr_reg[7]\(3),
- I1 => \cr_reg[7]\(1),
- I2 => \cr_reg[7]\(0),
- I3 => \c_state__0\(0),
- O => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\
- );
-\FSM_sequential_statemachine.c_state[2]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"888888888888888B"
- )
- port map (
- I0 => cnt_done,
- I1 => \c_state__0\(1),
- I2 => \cr_reg[7]\(3),
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(1),
- I5 => \c_state__0\(0),
- O => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\
- );
-\FSM_sequential_statemachine.c_state_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_18,
- Q => \c_state__0\(0)
- );
-\FSM_sequential_statemachine.c_state_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_17,
- Q => \c_state__0\(1)
- );
-\FSM_sequential_statemachine.c_state_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_16,
- Q => \c_state__0\(2)
- );
-bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
- port map (
- D(0) => D(6),
- E(0) => c_state,
- \FSM_sequential_statemachine.c_state_reg[1]\ => \statemachine.core_cmd[3]_i_2_n_0\,
- \FSM_sequential_statemachine.c_state_reg[1]_0\ => \statemachine.core_cmd[1]_i_2_n_0\,
- \FSM_sequential_statemachine.c_state_reg[1]_1\ => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\,
- \FSM_sequential_statemachine.c_state_reg[1]_2\ => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\,
- \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_16,
- \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_17,
- \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_18,
- Q(15 downto 0) => Q(15 downto 0),
- ack_in => ack_in,
- ack_out => ack_out,
- al => al,
- cmd_ack => cmd_ack,
- cnt_done => cnt_done,
- core_cmd(0) => core_cmd(2),
- \cr_reg[0]\ => \cr_reg[0]\,
- \cr_reg[4]\(0) => E(0),
- \cr_reg[7]\(3 downto 0) => \cr_reg[7]\(3 downto 0),
- \cr_reg[7]_0\ => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\,
- \ctr_reg[7]\(0) => \ctr_reg[7]\(7),
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- iack_o_reg => iack_o_reg,
- iack_o_reg_0 => iack_o_reg_0,
- irq_flag => irq_flag,
- irq_flag1_out => irq_flag1_out,
- iscl_oen_reg_0 => \^iscl_oen_reg\,
- \out\(2 downto 0) => \c_state__0\(2 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- \sr_reg[0]\(0) => bit_ctrl_n_15,
- \sr_reg[6]\ => \wb_dat_o[6]_i_2_n_0\,
- \sr_reg[7]\(0) => dout(7),
- \st_irq_block.al_reg\ => \st_irq_block.al_reg\,
- \statemachine.ack_out_reg\ => bit_ctrl_n_13,
- \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_5,
- \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_6,
- \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_7,
- \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_8,
- \statemachine.core_cmd_reg[3]_0\(3 downto 0) => cmd(3 downto 0),
- \statemachine.core_txd_reg\ => bit_ctrl_n_10,
- \statemachine.core_txd_reg_0\ => \statemachine.core_txd_reg_n_0\,
- \statemachine.host_ack_reg\ => bit_ctrl_n_12,
- \statemachine.ld_reg\ => bit_ctrl_n_9,
- \statemachine.ld_reg_0\ => \statemachine.ld_reg_n_0\,
- \statemachine.shift_reg\ => bit_ctrl_n_11,
- \txr_reg[6]\(1) => \txr_reg[7]\(6),
- \txr_reg[6]\(0) => \txr_reg[7]\(0),
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_we_o => wb_we_o
- );
-\dcnt[0]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"8A"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \statemachine.ld_reg_n_0\,
- I2 => \dcnt_reg_n_0_[0]\,
- O => \dcnt[0]_i_1_n_0\
- );
-\dcnt[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"A88A"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \statemachine.ld_reg_n_0\,
- I2 => \dcnt_reg_n_0_[0]\,
- I3 => \dcnt_reg_n_0_[1]\,
- O => \dcnt[1]_i_1_n_0\
- );
-\dcnt[2]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AAA8888A"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => \statemachine.ld_reg_n_0\,
- I2 => \dcnt_reg_n_0_[1]\,
- I3 => \dcnt_reg_n_0_[0]\,
- I4 => \dcnt_reg_n_0_[2]\,
- O => \dcnt[2]_i_1_n_0\
- );
-\dcnt_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \dcnt[0]_i_1_n_0\,
- Q => \dcnt_reg_n_0_[0]\
- );
-\dcnt_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \dcnt[1]_i_1_n_0\,
- Q => \dcnt_reg_n_0_[1]\
- );
-\dcnt_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \dcnt[2]_i_1_n_0\,
- Q => \dcnt_reg_n_0_[2]\
- );
-\sr[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[0]\,
- I2 => \txr_reg[7]\(1),
- I3 => s00_axi_aresetn,
- O => \sr[1]_i_1_n_0\
- );
-\sr[2]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[1]\,
- I2 => \txr_reg[7]\(2),
- I3 => s00_axi_aresetn,
- O => \sr[2]_i_1_n_0\
- );
-\sr[3]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[2]\,
- I2 => \txr_reg[7]\(3),
- I3 => s00_axi_aresetn,
- O => \sr[3]_i_1_n_0\
- );
-\sr[4]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[3]\,
- I2 => \txr_reg[7]\(4),
- I3 => s00_axi_aresetn,
- O => \sr[4]_i_1_n_0\
- );
-\sr[5]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[4]\,
- I2 => \txr_reg[7]\(5),
- I3 => s00_axi_aresetn,
- O => \sr[5]_i_1_n_0\
- );
-\sr[6]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[5]\,
- I2 => \txr_reg[7]\(6),
- I3 => s00_axi_aresetn,
- O => \sr[6]_i_1_n_0\
- );
-\sr[7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"FB"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => s00_axi_aresetn,
- I2 => \statemachine.shift_reg_n_0\,
- O => dcnt
- );
-\sr[7]_i_2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"E400"
- )
- port map (
- I0 => \statemachine.ld_reg_n_0\,
- I1 => \sr_reg_n_0_[6]\,
- I2 => \txr_reg[7]\(7),
- I3 => s00_axi_aresetn,
- O => \sr[7]_i_2_n_0\
- );
-\sr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_15,
- Q => \sr_reg_n_0_[0]\
- );
-\sr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[1]_i_1_n_0\,
- Q => \sr_reg_n_0_[1]\
- );
-\sr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[2]_i_1_n_0\,
- Q => \sr_reg_n_0_[2]\
- );
-\sr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[3]_i_1_n_0\,
- Q => \sr_reg_n_0_[3]\
- );
-\sr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[4]_i_1_n_0\,
- Q => \sr_reg_n_0_[4]\
- );
-\sr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[5]_i_1_n_0\,
- Q => \sr_reg_n_0_[5]\
- );
-\sr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[6]_i_1_n_0\,
- Q => \sr_reg_n_0_[6]\
- );
-\sr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => dcnt,
- CLR => \^iscl_oen_reg\,
- D => \sr[7]_i_2_n_0\,
- Q => dout(7)
- );
-\st_irq_block.rxack_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => ack_out,
- O => rxack_0
- );
-\statemachine.ack_out_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_13,
- Q => ack_out
- );
-\statemachine.core_cmd[1]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00000001"
- )
- port map (
- I0 => \c_state__0\(1),
- I1 => \c_state__0\(0),
- I2 => \cr_reg[7]\(3),
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(1),
- O => \statemachine.core_cmd[1]_i_2_n_0\
- );
-\statemachine.core_cmd[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"00000000F0C40FC4"
- )
- port map (
- I0 => \cr_reg[7]\(3),
- I1 => \cr_reg[7]\(1),
- I2 => \c_state__0\(0),
- I3 => \c_state__0\(1),
- I4 => cnt_done,
- I5 => \c_state__0\(2),
- O => core_cmd(2)
- );
-\statemachine.core_cmd[3]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"4848484878787B78"
- )
- port map (
- I0 => cnt_done,
- I1 => \c_state__0\(1),
- I2 => \c_state__0\(0),
- I3 => \cr_reg[7]\(0),
- I4 => \cr_reg[7]\(3),
- I5 => \cr_reg[7]\(1),
- O => \statemachine.core_cmd[3]_i_2_n_0\
- );
-\statemachine.core_cmd_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_8,
- Q => cmd(0)
- );
-\statemachine.core_cmd_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_7,
- Q => cmd(1)
- );
-\statemachine.core_cmd_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_6,
- Q => cmd(2)
- );
-\statemachine.core_cmd_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => c_state,
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_5,
- Q => cmd(3)
- );
-\statemachine.core_txd_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_10,
- Q => \statemachine.core_txd_reg_n_0\
- );
-\statemachine.host_ack_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_12,
- Q => cmd_ack
- );
-\statemachine.ld_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_9,
- Q => \statemachine.ld_reg_n_0\
- );
-\statemachine.shift_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_11,
- Q => \statemachine.shift_reg_n_0\
- );
-\wb_dat_o[0]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[0]\,
- I1 => \ctr_reg[7]\(0),
- I2 => wb_adr_o(1),
- I3 => Q(8),
- I4 => wb_adr_o(0),
- I5 => Q(0),
- O => \wb_dat_o[0]_i_2_n_0\
- );
-\wb_dat_o[1]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[1]\,
- I1 => \ctr_reg[7]\(1),
- I2 => wb_adr_o(1),
- I3 => Q(9),
- I4 => wb_adr_o(0),
- I5 => Q(1),
- O => \wb_dat_o[1]_i_2_n_0\
- );
-\wb_dat_o[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"3808FFFF38080000"
- )
- port map (
- I0 => \cr_reg[2]\,
- I1 => wb_adr_o(1),
- I2 => wb_adr_o(0),
- I3 => \txr_reg[7]\(2),
- I4 => wb_adr_o(2),
- I5 => \wb_dat_o[2]_i_2_n_0\,
- O => D(2)
- );
-\wb_dat_o[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[2]\,
- I1 => \ctr_reg[7]\(2),
- I2 => wb_adr_o(1),
- I3 => Q(10),
- I4 => wb_adr_o(0),
- I5 => Q(2),
- O => \wb_dat_o[2]_i_2_n_0\
- );
-\wb_dat_o[3]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"3808FFFF38080000"
- )
- port map (
- I0 => ack_in,
- I1 => wb_adr_o(1),
- I2 => wb_adr_o(0),
- I3 => \txr_reg[7]\(3),
- I4 => wb_adr_o(2),
- I5 => \wb_dat_o[3]_i_2_n_0\,
- O => D(3)
- );
-\wb_dat_o[3]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[3]\,
- I1 => \ctr_reg[7]\(3),
- I2 => wb_adr_o(1),
- I3 => Q(11),
- I4 => wb_adr_o(0),
- I5 => Q(3),
- O => \wb_dat_o[3]_i_2_n_0\
- );
-\wb_dat_o[4]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"3808FFFF38080000"
- )
- port map (
- I0 => \cr_reg[7]\(0),
- I1 => wb_adr_o(1),
- I2 => wb_adr_o(0),
- I3 => \txr_reg[7]\(4),
- I4 => wb_adr_o(2),
- I5 => \wb_dat_o[4]_i_2_n_0\,
- O => D(4)
- );
-\wb_dat_o[4]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[4]\,
- I1 => \ctr_reg[7]\(4),
- I2 => wb_adr_o(1),
- I3 => Q(12),
- I4 => wb_adr_o(0),
- I5 => Q(4),
- O => \wb_dat_o[4]_i_2_n_0\
- );
-\wb_dat_o[5]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[5]\,
- I1 => \ctr_reg[7]\(5),
- I2 => wb_adr_o(1),
- I3 => Q(13),
- I4 => wb_adr_o(0),
- I5 => Q(5),
- O => \wb_dat_o[5]_i_2_n_0\
- );
-\wb_dat_o[6]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \sr_reg_n_0_[6]\,
- I1 => \ctr_reg[7]\(6),
- I2 => wb_adr_o(1),
- I3 => Q(14),
- I4 => wb_adr_o(0),
- I5 => Q(6),
- O => \wb_dat_o[6]_i_2_n_0\
- );
-\wb_dat_o[7]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => dout(7),
- I1 => \ctr_reg[7]\(7),
- I2 => wb_adr_o(1),
- I3 => Q(15),
- I4 => wb_adr_o(0),
- I5 => Q(7),
- O => \wb_dat_o[7]_i_2_n_0\
- );
-\wb_dat_o_reg[0]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[0]_i_2_n_0\,
- I1 => \cr_reg[0]_0\,
- O => D(0),
- S => wb_adr_o(2)
- );
-\wb_dat_o_reg[1]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[1]_i_2_n_0\,
- I1 => \cr_reg[1]\,
- O => D(1),
- S => wb_adr_o(2)
- );
-\wb_dat_o_reg[5]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[5]_i_2_n_0\,
- I1 => \cr_reg[5]\,
- O => D(5),
- S => wb_adr_o(2)
- );
-\wb_dat_o_reg[7]_i_1\: unisim.vcomponents.MUXF7
- port map (
- I0 => \wb_dat_o[7]_i_2_n_0\,
- I1 => \cr_reg[7]_0\,
- O => D(7),
- S => wb_adr_o(2)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_2_0_i2c_master_top is
- port (
- wb_ack_i : out STD_LOGIC;
- wb_rst_o : out STD_LOGIC;
- axi_int_o : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_stb_r_reg : out STD_LOGIC;
- \s_rdata_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \s_rdata_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
- s_stb_r_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
- wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_arvalid : in STD_LOGIC;
- wb_cyc_o : in STD_LOGIC;
- wb_we_o : in STD_LOGIC;
- iack_o_reg_0 : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_we_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
- s_we_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \s_addr_reg[4]\ : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_i2c_master_top : entity is "i2c_master_top";
-end system_design_axi_wb_i2c_master_2_0_i2c_master_top;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_top is
- signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal ack_in : STD_LOGIC;
- signal al : STD_LOGIC;
- signal byte_ctrl_n_12 : STD_LOGIC;
- signal \cr[0]_i_1_n_0\ : STD_LOGIC;
- signal \cr[1]_i_1_n_0\ : STD_LOGIC;
- signal \cr[2]_i_1_n_0\ : STD_LOGIC;
- signal \cr[3]_i_1_n_0\ : STD_LOGIC;
- signal \cr_reg_n_0_[0]\ : STD_LOGIC;
- signal \cr_reg_n_0_[1]\ : STD_LOGIC;
- signal \cr_reg_n_0_[2]\ : STD_LOGIC;
- signal ctr : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \ctr_reg_n_0_[0]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[1]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[2]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[3]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[4]\ : STD_LOGIC;
- signal \ctr_reg_n_0_[5]\ : STD_LOGIC;
- signal data0 : STD_LOGIC_VECTOR ( 13 downto 0 );
- signal ien : STD_LOGIC;
- signal irq_flag : STD_LOGIC;
- signal irq_flag1_out : STD_LOGIC;
- signal \prer[10]_i_1_n_0\ : STD_LOGIC;
- signal \prer[11]_i_1_n_0\ : STD_LOGIC;
- signal \prer[12]_i_1_n_0\ : STD_LOGIC;
- signal \prer[13]_i_1_n_0\ : STD_LOGIC;
- signal \prer[14]_i_1_n_0\ : STD_LOGIC;
- signal \prer[15]_i_2_n_0\ : STD_LOGIC;
- signal \prer[8]_i_1_n_0\ : STD_LOGIC;
- signal \prer[9]_i_1_n_0\ : STD_LOGIC;
- signal \prer_reg_n_0_[0]\ : STD_LOGIC;
- signal \prer_reg_n_0_[1]\ : STD_LOGIC;
- signal read : STD_LOGIC;
- signal rxack : STD_LOGIC;
- signal rxack_0 : STD_LOGIC;
- signal \st_irq_block.al_reg_n_0\ : STD_LOGIC;
- signal \st_irq_block.wb_inta_o_i_1_n_0\ : STD_LOGIC;
- signal start : STD_LOGIC;
- signal stop : STD_LOGIC;
- signal tip : STD_LOGIC;
- signal tip_1 : STD_LOGIC;
- signal txr : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \^wb_ack_i\ : STD_LOGIC;
- signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \wb_dat_o[0]_i_3_n_0\ : STD_LOGIC;
- signal \wb_dat_o[1]_i_3_n_0\ : STD_LOGIC;
- signal \wb_dat_o[5]_i_3_n_0\ : STD_LOGIC;
- signal \wb_dat_o[7]_i_3_n_0\ : STD_LOGIC;
- signal \^wb_rst_o\ : STD_LOGIC;
- signal write : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair26";
-begin
- Q(0) <= \^q\(0);
- wb_ack_i <= \^wb_ack_i\;
- wb_rst_o <= \^wb_rst_o\;
-byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
- port map (
- D(7 downto 0) => wb_dat_o(7 downto 0),
- E(0) => byte_ctrl_n_12,
- Q(15 downto 2) => data0(13 downto 0),
- Q(1) => \prer_reg_n_0_[1]\,
- Q(0) => \prer_reg_n_0_[0]\,
- ack_in => ack_in,
- al => al,
- \cr_reg[0]\ => \cr_reg_n_0_[0]\,
- \cr_reg[0]_0\ => \wb_dat_o[0]_i_3_n_0\,
- \cr_reg[1]\ => \wb_dat_o[1]_i_3_n_0\,
- \cr_reg[2]\ => \cr_reg_n_0_[2]\,
- \cr_reg[5]\ => \wb_dat_o[5]_i_3_n_0\,
- \cr_reg[7]\(3) => start,
- \cr_reg[7]\(2) => stop,
- \cr_reg[7]\(1) => read,
- \cr_reg[7]\(0) => write,
- \cr_reg[7]_0\ => \wb_dat_o[7]_i_3_n_0\,
- \ctr_reg[7]\(7) => \^q\(0),
- \ctr_reg[7]\(6) => ien,
- \ctr_reg[7]\(5) => \ctr_reg_n_0_[5]\,
- \ctr_reg[7]\(4) => \ctr_reg_n_0_[4]\,
- \ctr_reg[7]\(3) => \ctr_reg_n_0_[3]\,
- \ctr_reg[7]\(2) => \ctr_reg_n_0_[2]\,
- \ctr_reg[7]\(1) => \ctr_reg_n_0_[1]\,
- \ctr_reg[7]\(0) => \ctr_reg_n_0_[0]\,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- iack_o_reg => \^wb_ack_i\,
- iack_o_reg_0 => iack_o_reg_0,
- irq_flag => irq_flag,
- irq_flag1_out => irq_flag1_out,
- iscl_oen_reg => \^wb_rst_o\,
- rxack_0 => rxack_0,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- \st_irq_block.al_reg\ => \st_irq_block.al_reg_n_0\,
- \txr_reg[7]\(7 downto 0) => txr(7 downto 0),
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_we_o => wb_we_o
- );
-\cr[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8000FFFF80000000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(0),
- I2 => wb_we_o,
- I3 => \^wb_ack_i\,
- I4 => \s_addr_reg[4]\,
- I5 => \cr_reg_n_0_[0]\,
- O => \cr[0]_i_1_n_0\
- );
-\cr[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8000FFFF80000000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(1),
- I2 => wb_we_o,
- I3 => \^wb_ack_i\,
- I4 => \s_addr_reg[4]\,
- I5 => \cr_reg_n_0_[1]\,
- O => \cr[1]_i_1_n_0\
- );
-\cr[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8000FFFF80000000"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(2),
- I2 => wb_we_o,
- I3 => \^wb_ack_i\,
- I4 => \s_addr_reg[4]\,
- I5 => \cr_reg_n_0_[2]\,
- O => \cr[2]_i_1_n_0\
- );
-\cr[3]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"C808"
- )
- port map (
- I0 => s00_axi_wdata(3),
- I1 => s00_axi_aresetn,
- I2 => iack_o_reg_0,
- I3 => ack_in,
- O => \cr[3]_i_1_n_0\
- );
-\cr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[0]_i_1_n_0\,
- Q => \cr_reg_n_0_[0]\
- );
-\cr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[1]_i_1_n_0\,
- Q => \cr_reg_n_0_[1]\
- );
-\cr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[2]_i_1_n_0\,
- Q => \cr_reg_n_0_[2]\
- );
-\cr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \cr[3]_i_1_n_0\,
- Q => ack_in
- );
-\cr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(0),
- Q => write
- );
-\cr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(1),
- Q => read
- );
-\cr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(2),
- Q => stop
- );
-\cr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
- CLR => \^wb_rst_o\,
- D => D(3),
- Q => start
- );
-\ctr[0]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(0),
- O => ctr(0)
- );
-\ctr[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(1),
- O => ctr(1)
- );
-\ctr[2]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(2),
- O => ctr(2)
- );
-\ctr[3]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(3),
- O => ctr(3)
- );
-\ctr[4]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(4),
- O => ctr(4)
- );
-\ctr[5]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(5),
- O => ctr(5)
- );
-\ctr[6]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(6),
- O => ctr(6)
- );
-\ctr[7]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s00_axi_wdata(7),
- O => ctr(7)
- );
-\ctr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(0),
- Q => \ctr_reg_n_0_[0]\
- );
-\ctr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(1),
- Q => \ctr_reg_n_0_[1]\
- );
-\ctr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(2),
- Q => \ctr_reg_n_0_[2]\
- );
-\ctr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(3),
- Q => \ctr_reg_n_0_[3]\
- );
-\ctr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(4),
- Q => \ctr_reg_n_0_[4]\
- );
-\ctr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(5),
- Q => \ctr_reg_n_0_[5]\
- );
-\ctr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(6),
- Q => ien
- );
-\ctr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg(0),
- CLR => \^wb_rst_o\,
- D => ctr(7),
- Q => \^q\(0)
- );
-iack_o_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_stb_r_reg_0,
- Q => \^wb_ack_i\,
- R => '0'
- );
-\prer[10]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(2),
- I1 => s00_axi_aresetn,
- O => \prer[10]_i_1_n_0\
- );
-\prer[11]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(3),
- I1 => s00_axi_aresetn,
- O => \prer[11]_i_1_n_0\
- );
-\prer[12]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(4),
- I1 => s00_axi_aresetn,
- O => \prer[12]_i_1_n_0\
- );
-\prer[13]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(5),
- I1 => s00_axi_aresetn,
- O => \prer[13]_i_1_n_0\
- );
-\prer[14]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(6),
- I1 => s00_axi_aresetn,
- O => \prer[14]_i_1_n_0\
- );
-\prer[15]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(7),
- I1 => s00_axi_aresetn,
- O => \prer[15]_i_2_n_0\
- );
-\prer[8]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(0),
- I1 => s00_axi_aresetn,
- O => \prer[8]_i_1_n_0\
- );
-\prer[9]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s00_axi_wdata(1),
- I1 => s00_axi_aresetn,
- O => \prer[9]_i_1_n_0\
- );
-\prer_reg[0]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[8]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => \prer_reg_n_0_[0]\
- );
-\prer_reg[10]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[10]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(8)
- );
-\prer_reg[11]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[11]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(9)
- );
-\prer_reg[12]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[12]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(10)
- );
-\prer_reg[13]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[13]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(11)
- );
-\prer_reg[14]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[14]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(12)
- );
-\prer_reg[15]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[15]_i_2_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(13)
- );
-\prer_reg[1]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[9]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => \prer_reg_n_0_[1]\
- );
-\prer_reg[2]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[10]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(0)
- );
-\prer_reg[3]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[11]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(1)
- );
-\prer_reg[4]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[12]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(2)
- );
-\prer_reg[5]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[13]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(3)
- );
-\prer_reg[6]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[14]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(4)
- );
-\prer_reg[7]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(0),
- D => \prer[15]_i_2_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(5)
- );
-\prer_reg[8]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[8]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(6)
- );
-\prer_reg[9]\: unisim.vcomponents.FDPE
- port map (
- C => s00_axi_aclk,
- CE => E(1),
- D => \prer[9]_i_1_n_0\,
- PRE => \^wb_rst_o\,
- Q => data0(7)
- );
-\s_rdata[7]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \^wb_ack_i\,
- I1 => wb_we_o,
- O => \s_rdata_reg[0]\(0)
- );
-s_stb_r_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"EFEE"
- )
- port map (
- I0 => s00_axi_awvalid,
- I1 => s00_axi_arvalid,
- I2 => \^wb_ack_i\,
- I3 => wb_cyc_o,
- O => s_stb_r_reg
- );
-\st_irq_block.al_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => al,
- Q => \st_irq_block.al_reg_n_0\
- );
-\st_irq_block.irq_flag_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => irq_flag1_out,
- Q => irq_flag
- );
-\st_irq_block.rxack_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => rxack_0,
- Q => rxack
- );
-\st_irq_block.tip_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"A8"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => write,
- I2 => read,
- O => tip_1
- );
-\st_irq_block.tip_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => tip_1,
- Q => tip
- );
-\st_irq_block.wb_inta_o_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"80"
- )
- port map (
- I0 => irq_flag,
- I1 => s00_axi_aresetn,
- I2 => ien,
- O => \st_irq_block.wb_inta_o_i_1_n_0\
- );
-\st_irq_block.wb_inta_o_reg\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => \^wb_rst_o\,
- D => \st_irq_block.wb_inta_o_i_1_n_0\,
- Q => axi_int_o
- );
-\txr_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(0),
- Q => txr(0)
- );
-\txr_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(1),
- Q => txr(1)
- );
-\txr_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(2),
- Q => txr(2)
- );
-\txr_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(3),
- Q => txr(3)
- );
-\txr_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(4),
- Q => txr(4)
- );
-\txr_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(5),
- Q => txr(5)
- );
-\txr_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(6),
- Q => txr(6)
- );
-\txr_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_we_r_reg_0(0),
- CLR => \^wb_rst_o\,
- D => ctr(7),
- Q => txr(7)
- );
-\wb_dat_o[0]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \cr_reg_n_0_[0]\,
- I1 => wb_adr_o(1),
- I2 => txr(0),
- I3 => wb_adr_o(0),
- I4 => irq_flag,
- O => \wb_dat_o[0]_i_3_n_0\
- );
-\wb_dat_o[1]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \cr_reg_n_0_[1]\,
- I1 => wb_adr_o(1),
- I2 => txr(1),
- I3 => wb_adr_o(0),
- I4 => tip,
- O => \wb_dat_o[1]_i_3_n_0\
- );
-\wb_dat_o[5]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => read,
- I1 => wb_adr_o(1),
- I2 => txr(5),
- I3 => wb_adr_o(0),
- I4 => \st_irq_block.al_reg_n_0\,
- O => \wb_dat_o[5]_i_3_n_0\
- );
-\wb_dat_o[7]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => start,
- I1 => wb_adr_o(1),
- I2 => txr(7),
- I3 => wb_adr_o(0),
- I4 => rxack,
- O => \wb_dat_o[7]_i_3_n_0\
- );
-\wb_dat_o_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(0),
- Q => \s_rdata_reg[7]\(0),
- R => '0'
- );
-\wb_dat_o_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(1),
- Q => \s_rdata_reg[7]\(1),
- R => '0'
- );
-\wb_dat_o_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(2),
- Q => \s_rdata_reg[7]\(2),
- R => '0'
- );
-\wb_dat_o_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(3),
- Q => \s_rdata_reg[7]\(3),
- R => '0'
- );
-\wb_dat_o_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(4),
- Q => \s_rdata_reg[7]\(4),
- R => '0'
- );
-\wb_dat_o_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(5),
- Q => \s_rdata_reg[7]\(5),
- R => '0'
- );
-\wb_dat_o_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(6),
- Q => \s_rdata_reg[7]\(6),
- R => '0'
- );
-\wb_dat_o_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => wb_dat_o(7),
- Q => \s_rdata_reg[7]\(7),
- R => '0'
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master is
- port (
- i2c_scl_io : inout STD_LOGIC;
- i2c_sda_io : inout STD_LOGIC;
- axi_int_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_bvalid : out STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_rvalid : out STD_LOGIC;
- s00_axi_rready : in STD_LOGIC
- );
- attribute C_S00_AXI_ADDR_WIDTH : integer;
- attribute C_S00_AXI_ADDR_WIDTH of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master : entity is 32;
- attribute C_S00_AXI_DATA_WIDTH : integer;
- attribute C_S00_AXI_DATA_WIDTH of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master : entity is 32;
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master : entity is "axi_wb_i2c_master";
-end system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master is
- signal \<const0>\ : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_11 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_12 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_13 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_14 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_15 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_16 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_17 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_18 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_19 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_21 : STD_LOGIC;
- signal cmp_axis_wbm_bridge_n_7 : STD_LOGIC;
- signal cmp_i2c_master_top_n_4 : STD_LOGIC;
- signal cmp_i2c_master_top_n_5 : STD_LOGIC;
- signal ena : STD_LOGIC;
- signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \^s00_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal wb_ack_i : STD_LOGIC;
- signal wb_adr_o : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal wb_cyc_o : STD_LOGIC;
- signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal wb_rst_o : STD_LOGIC;
- signal wb_we_o : STD_LOGIC;
-begin
- s00_axi_bresp(1) <= \^s00_axi_bresp\(1);
- s00_axi_bresp(0) <= \<const0>\;
- s00_axi_rdata(31) <= \<const0>\;
- s00_axi_rdata(30) <= \<const0>\;
- s00_axi_rdata(29) <= \<const0>\;
- s00_axi_rdata(28) <= \<const0>\;
- s00_axi_rdata(27) <= \<const0>\;
- s00_axi_rdata(26) <= \<const0>\;
- s00_axi_rdata(25) <= \<const0>\;
- s00_axi_rdata(24) <= \<const0>\;
- s00_axi_rdata(23) <= \<const0>\;
- s00_axi_rdata(22) <= \<const0>\;
- s00_axi_rdata(21) <= \<const0>\;
- s00_axi_rdata(20) <= \<const0>\;
- s00_axi_rdata(19) <= \<const0>\;
- s00_axi_rdata(18) <= \<const0>\;
- s00_axi_rdata(17) <= \<const0>\;
- s00_axi_rdata(16) <= \<const0>\;
- s00_axi_rdata(15) <= \<const0>\;
- s00_axi_rdata(14) <= \<const0>\;
- s00_axi_rdata(13) <= \<const0>\;
- s00_axi_rdata(12) <= \<const0>\;
- s00_axi_rdata(11) <= \<const0>\;
- s00_axi_rdata(10) <= \<const0>\;
- s00_axi_rdata(9) <= \<const0>\;
- s00_axi_rdata(8) <= \<const0>\;
- s00_axi_rdata(7 downto 0) <= \^s00_axi_rdata\(7 downto 0);
- s00_axi_rresp(1) <= \<const0>\;
- s00_axi_rresp(0) <= \<const0>\;
-GND: unisim.vcomponents.GND
- port map (
- G => \<const0>\
- );
-cmp_axis_wbm_bridge: entity work.system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge
- port map (
- D(3) => cmp_axis_wbm_bridge_n_12,
- D(2) => cmp_axis_wbm_bridge_n_13,
- D(1) => cmp_axis_wbm_bridge_n_14,
- D(0) => cmp_axis_wbm_bridge_n_15,
- E(0) => cmp_axis_wbm_bridge_n_11,
- Q(0) => ena,
- \cr_reg[2]\ => cmp_axis_wbm_bridge_n_7,
- \cr_reg[4]\ => cmp_axis_wbm_bridge_n_16,
- \ctr_reg[0]\(0) => cmp_axis_wbm_bridge_n_19,
- iack_o_reg => cmp_axis_wbm_bridge_n_21,
- iack_o_reg_0 => cmp_i2c_master_top_n_4,
- iack_o_reg_1(0) => cmp_i2c_master_top_n_5,
- \prer_reg[8]\(1) => cmp_axis_wbm_bridge_n_17,
- \prer_reg[8]\(0) => cmp_axis_wbm_bridge_n_18,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_araddr(2 downto 0) => s00_axi_araddr(4 downto 2),
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arready => s00_axi_arready,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awaddr(2 downto 0) => s00_axi_awaddr(4 downto 2),
- s00_axi_awready => s00_axi_awready,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_bready => s00_axi_bready,
- s00_axi_bresp(0) => \^s00_axi_bresp\(1),
- s00_axi_bvalid => s00_axi_bvalid,
- s00_axi_rdata(7 downto 0) => \^s00_axi_rdata\(7 downto 0),
- s00_axi_rready => s00_axi_rready,
- s00_axi_rvalid => s00_axi_rvalid,
- s00_axi_wdata(3 downto 0) => s00_axi_wdata(7 downto 4),
- s00_axi_wready => s00_axi_wready,
- s00_axi_wvalid => s00_axi_wvalid,
- wb_ack_i => wb_ack_i,
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_cyc_o => wb_cyc_o,
- \wb_dat_o_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
- wb_rst_o => wb_rst_o,
- wb_we_o => wb_we_o
- );
-cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_top
- port map (
- D(3) => cmp_axis_wbm_bridge_n_12,
- D(2) => cmp_axis_wbm_bridge_n_13,
- D(1) => cmp_axis_wbm_bridge_n_14,
- D(0) => cmp_axis_wbm_bridge_n_15,
- E(1) => cmp_axis_wbm_bridge_n_17,
- E(0) => cmp_axis_wbm_bridge_n_18,
- Q(0) => ena,
- axi_int_o => axi_int_o,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- iack_o_reg_0 => cmp_axis_wbm_bridge_n_16,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_wdata(7 downto 0) => s00_axi_wdata(7 downto 0),
- \s_addr_reg[4]\ => cmp_axis_wbm_bridge_n_7,
- \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_5,
- \s_rdata_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
- s_stb_r_reg => cmp_i2c_master_top_n_4,
- s_stb_r_reg_0 => cmp_axis_wbm_bridge_n_21,
- s_we_r_reg(0) => cmp_axis_wbm_bridge_n_19,
- s_we_r_reg_0(0) => cmp_axis_wbm_bridge_n_11,
- wb_ack_i => wb_ack_i,
- wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
- wb_cyc_o => wb_cyc_o,
- wb_rst_o => wb_rst_o,
- wb_we_o => wb_we_o
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_axi_wb_i2c_master_2_0 is
- port (
- i2c_scl_io : inout STD_LOGIC;
- i2c_sda_io : inout STD_LOGIC;
- axi_int_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_bvalid : out STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_rvalid : out STD_LOGIC;
- s00_axi_rready : in STD_LOGIC
- );
- attribute NotValidForBitStream : boolean;
- attribute NotValidForBitStream of system_design_axi_wb_i2c_master_2_0 : entity is true;
- attribute CHECK_LICENSE_TYPE : string;
- attribute CHECK_LICENSE_TYPE of system_design_axi_wb_i2c_master_2_0 : entity is "system_design_axi_wb_i2c_master_2_0,axi_wb_i2c_master,{}";
- attribute downgradeipidentifiedwarnings : string;
- attribute downgradeipidentifiedwarnings of system_design_axi_wb_i2c_master_2_0 : entity is "yes";
- attribute x_core_info : string;
- attribute x_core_info of system_design_axi_wb_i2c_master_2_0 : entity is "axi_wb_i2c_master,Vivado 2016.2";
-end system_design_axi_wb_i2c_master_2_0;
-
-architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0 is
- attribute C_S00_AXI_ADDR_WIDTH : integer;
- attribute C_S00_AXI_ADDR_WIDTH of U0 : label is 32;
- attribute C_S00_AXI_DATA_WIDTH : integer;
- attribute C_S00_AXI_DATA_WIDTH of U0 : label is 32;
-begin
-U0: entity work.system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
- port map (
- axi_int_o => axi_int_o,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_araddr(31 downto 0) => s00_axi_araddr(31 downto 0),
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arprot(2 downto 0) => s00_axi_arprot(2 downto 0),
- s00_axi_arready => s00_axi_arready,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awaddr(31 downto 0) => s00_axi_awaddr(31 downto 0),
- s00_axi_awprot(2 downto 0) => s00_axi_awprot(2 downto 0),
- s00_axi_awready => s00_axi_awready,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_bready => s00_axi_bready,
- s00_axi_bresp(1 downto 0) => s00_axi_bresp(1 downto 0),
- s00_axi_bvalid => s00_axi_bvalid,
- s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
- s00_axi_rready => s00_axi_rready,
- s00_axi_rresp(1 downto 0) => s00_axi_rresp(1 downto 0),
- s00_axi_rvalid => s00_axi_rvalid,
- s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
- s00_axi_wready => s00_axi_wready,
- s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
- s00_axi_wvalid => s00_axi_wvalid
- );
-end STRUCTURE;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd
similarity index 90%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd
index be34fac6ed5b7e38ecaae245ab14efeb592f2401..3b740503da23003c388ccda78085cd903c84d15c 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd
@@ -5,7 +5,7 @@
-- Author : Pieter Van Trappen
-- Company : CERN TE-ABT-EC
-- Created : 2016-08-19
--- Last update: 2017-03-23
+-- Last update: 2017-10-11
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -36,6 +36,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
library hdl_lib;
use hdl_lib.main_pkg.all;
@@ -125,10 +128,10 @@ begin
-- Instantiation of components
cmp_axis_wbm_bridge : axis_wbm_bridge
generic map (
- g_AXI_AWIDTH => C_S00_AXI_ADDR_WIDTH,
- g_WB_AWIDTH => c_WB_AWIDTH,
- g_AXI_DWIDTH => C_S00_AXI_DATA_WIDTH,
- g_WB_DWIDTH => c_WB_DWIDTH,
+ g_AXI_AWIDTH => C_S00_AXI_ADDR_WIDTH,
+ g_WB_AWIDTH => c_WB_AWIDTH,
+ g_AXI_DWIDTH => C_S00_AXI_DATA_WIDTH,
+ g_WB_DWIDTH => c_WB_DWIDTH,
g_WB_BYTEADDR => true)
port map (
wb_clk_o => wb_clk_o,
@@ -194,9 +197,25 @@ begin
wb_rty_i <= '0';
-- I2C signals (signals have external pull-ups)
- i2c_scl_io <= 'Z' when scl_padoen_o = '1' else scl_pad_o;
- scl_pad_i <= i2c_scl_io;
- i2c_sda_io <= 'Z' when sda_padoen_o = '1' else sda_pad_o;
- sda_pad_i <= i2c_sda_io;
-
+ -- hard instantiation needed cause Vivado OOC run!
+ iobuf_i2c_scl : IOBUF
+ generic map (
+ DRIVE => 12,
+ IOSTANDARD => "DEFAULT",
+ SLEW => "FAST")
+ port map (
+ O => scl_pad_i,
+ IO => i2c_scl_io,
+ I => scl_pad_o,
+ T => scl_padoen_o);
+ iobuf_i2c_sda : IOBUF
+ generic map (
+ DRIVE => 12,
+ IOSTANDARD => "DEFAULT",
+ SLEW => "FAST")
+ port map (
+ O => sda_pad_i,
+ IO => i2c_sda_io,
+ I => sda_pad_o,
+ T => sda_padoen_o);
end rtl;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd
similarity index 99%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd
index 6a42dfb18e832a01ab6e4456cb6e446ed0ee32eb..276cbb5411b377d10b5b897a24a89d41d47da0c9 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Pieter Van Trappen <pieter@>
-- Company :
-- Created : 2016-08-22
--- Last update: 2016-08-26
+-- Last update: 2017-08-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -312,7 +312,7 @@ begin -- architecture behavioural
end if;
v_bvalid_r := s00_axi_bvalid;
end process axi_slave_test_writeResponse;
-
+
end architecture behavioural;
-------------------------------------------------------------------------------
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
index 49617da42aa3ec46c25a7c0623e392f4fa5b39b0..c4d875f3a7dc4fccfa47f89b7937cec1d7bb8114 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Jun 21 08:28:46 CEST 2017
+# Generated by export_simulation on Wed Oct 11 12:10:30 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
index 89d12fdc4e6a57f40f6cbc92bde45919adff365e..534b1eea17fb5358ec5dd1b28f76cc38c80d336b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
@@ -568,11 +568,11 @@ vcom -work axi_uartlite_v2_0_13 -93 \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd" \
"../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
index cec3e1ef4a90ed208ab3207163471e8eb6c9a01d..8b0cfd2d2694f33a51c4b39910d128e1c5049997 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
@@ -392,11 +392,11 @@ uartlite_core.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/
axi_uartlite.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_xlconstant_6_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
index 6181ccce40782da020c3568132a7d2d5b4533691..aeae6db74a582e972a531ea5e35f1f67ac77cb11 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Jun 21 08:28:46 CEST 2017
+# Generated by Vivado on Wed Oct 11 12:10:30 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
index 49617da42aa3ec46c25a7c0623e392f4fa5b39b0..c4d875f3a7dc4fccfa47f89b7937cec1d7bb8114 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Jun 21 08:28:46 CEST 2017
+# Generated by export_simulation on Wed Oct 11 12:10:30 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
index c5dfceead5152df83a47cd350723fe2c5449d243..945990dc0ff91fe24cf520350cb3fa58f634fc89 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
@@ -392,11 +392,11 @@ uartlite_core.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/
axi_uartlite.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_xlconstant_6_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
index d21352badd2d19ba3dcae90d3562695383bf725a..306b9e095e1c47650307820033d024b8f3c9cd99 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
@@ -517,11 +517,11 @@
-makelib ies/xil_defaultlib \
"../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd" \
"../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd" \
- "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd" \
- "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd" \
- "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd" \
- "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd" \
- "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd" \
+ "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd" \
+ "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd" \
+ "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd" \
+ "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd" \
+ "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
index ba89a30c0354c92a10eafa9ade613ed35ae2853f..1060afe54fc6be67de089b32a92c8e6cd9e68382 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Jun 21 08:28:46 CEST 2017
+# Generated by Vivado on Wed Oct 11 12:10:30 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
index 49617da42aa3ec46c25a7c0623e392f4fa5b39b0..c4d875f3a7dc4fccfa47f89b7937cec1d7bb8114 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Jun 21 08:28:46 CEST 2017
+# Generated by export_simulation on Wed Oct 11 12:10:30 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
index aa9f8ec1ac0a04ecbe6b39408ecc8ccf0843638a..f5eca5ec09cf80048780d9219c14afa86aed8b9d 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
@@ -568,11 +568,11 @@ vcom -work axi_uartlite_v2_0_13 -64 -93 \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd" \
"../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
index cec3e1ef4a90ed208ab3207163471e8eb6c9a01d..8b0cfd2d2694f33a51c4b39910d128e1c5049997 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
@@ -392,11 +392,11 @@ uartlite_core.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/
axi_uartlite.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_xlconstant_6_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
index 6ed7ca900dd644ef150024045fa7011f7f552846..f9ef0b16570b14bd624fda4f49f939cada412da6 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Jun 21 08:28:46 CEST 2017
+# Generated by Vivado on Wed Oct 11 12:10:30 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
index 49617da42aa3ec46c25a7c0623e392f4fa5b39b0..c4d875f3a7dc4fccfa47f89b7937cec1d7bb8114 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Jun 21 08:28:46 CEST 2017
+# Generated by export_simulation on Wed Oct 11 12:10:30 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
index e399ef267b9c78556636368fc6f83c2e8f289d44..aa2a206f25f11fa0b3a67ab1302fd1b5dd110b93 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
@@ -568,11 +568,11 @@ vcom -work axi_uartlite_v2_0_13 -64 \
vcom -work xil_defaultlib -64 \
"../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd" \
"../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
index cec3e1ef4a90ed208ab3207163471e8eb6c9a01d..8b0cfd2d2694f33a51c4b39910d128e1c5049997 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
@@ -392,11 +392,11 @@ uartlite_core.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/
axi_uartlite.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_xlconstant_6_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
index 2d888609625e1b183015d80e5198758a99feaf13..ed4f783f0e48f9a8b664459ef489c34b9bffd7cf 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Jun 21 08:28:46 CEST 2017
+# Generated by Vivado on Wed Oct 11 12:10:30 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
index 49617da42aa3ec46c25a7c0623e392f4fa5b39b0..c4d875f3a7dc4fccfa47f89b7937cec1d7bb8114 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Jun 21 08:28:46 CEST 2017
+# Generated by export_simulation on Wed Oct 11 12:10:30 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
index 4d7a9e6c54fbeb3f34c0dec9f09d22589d3d871c..dfa823e632bd9cc05be4e86eff569034f8209fde 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
@@ -568,11 +568,11 @@ vcom -work axi_uartlite_v2_0_13 -93 \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd" \
"../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd" \
-"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd" \
+"../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
index cec3e1ef4a90ed208ab3207163471e8eb6c9a01d..8b0cfd2d2694f33a51c4b39910d128e1c5049997 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
@@ -392,11 +392,11 @@ uartlite_core.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/
axi_uartlite.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_xlconstant_6_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
index cc2925e94a1f5a4bcb57f0071d1ddc4b78b4cc7d..9641d01fbed5e0ecccacbf456a1c7a991871aee9 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Jun 21 08:28:46 CEST 2017
+# Generated by Vivado on Wed Oct 11 12:10:30 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
index 49617da42aa3ec46c25a7c0623e392f4fa5b39b0..c4d875f3a7dc4fccfa47f89b7937cec1d7bb8114 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Jun 21 08:28:46 CEST 2017
+# Generated by export_simulation on Wed Oct 11 12:10:30 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
index c5dfceead5152df83a47cd350723fe2c5449d243..945990dc0ff91fe24cf520350cb3fa58f634fc89 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
@@ -392,11 +392,11 @@ uartlite_core.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/
axi_uartlite.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_xlconstant_6_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
index 4c9d0b04c82effe283e75866277b58543564f245..88041d83424a7ee55c990bb585e80af792462a40 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Jun 21 08:28:46 CEST 2017
+# Generated by Vivado on Wed Oct 11 12:10:30 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
@@ -648,11 +648,11 @@ compile()
vhdlan -work xil_defaultlib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
index 49617da42aa3ec46c25a7c0623e392f4fa5b39b0..c4d875f3a7dc4fccfa47f89b7937cec1d7bb8114 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Jun 21 08:28:46 CEST 2017
+# Generated by export_simulation on Wed Oct 11 12:10:30 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
index c5dfceead5152df83a47cd350723fe2c5449d243..945990dc0ff91fe24cf520350cb3fa58f634fc89 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
@@ -392,11 +392,11 @@ uartlite_core.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/
axi_uartlite.vhd,vhdl,axi_uartlite_v2_0_13,../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_xlconstant_6_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_bit_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_byte_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+i2c_master_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
index dd688259a8e8c760a78d959bb174aab057701d0d..b13e1d133cafd15ac02e0774be77a4746d3d15fa 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Jun 21 08:28:46 CEST 2017
+# Generated by Vivado on Wed Oct 11 12:10:30 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
index 8f480f580a89e978c6487e37d8ef6a7bdbc85f0c..7c82647908db962e103be77806d033805f77ee99 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
@@ -301,11 +301,11 @@ vhdl axi_uartlite_v2_0_13 "../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/uart
vhdl axi_uartlite_v2_0_13 "../../../ipstatic/axi_uartlite_v2_0/hdl/src/vhdl/axi_uartlite.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_axi_uartlite_0_0/sim/system_design_axi_uartlite_0_0.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_xlconstant_6_0/sim/system_design_xlconstant_6_0.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd"
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef
index 0f1cc16acd7a69e4ec7f127eae869571adf3bf2c..69fb9dabcb5cfa987b80ce03446b4d6ff95125dc 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef and b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
index 82ecd47d8f2dfb3567505e0961043a14b53cd094..5808333c6137546b8eb38e9e3fbdb15653830107 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Jun 21 08:28:38 2017
+--Date : Wed Oct 11 12:10:21 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design.bd
--Design : system_design
@@ -4009,12 +4009,46 @@ architecture STRUCTURE of system_design is
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_design_rst_wrc_1p_kintex7_0_62M_0;
- component system_design_axi_wb_i2c_master_0_1 is
+ component system_design_wrc_1p_kintex7_0_0 is
port (
- i2c_scl_io : inout STD_LOGIC;
- i2c_sda_io : inout STD_LOGIC;
+ clk_20m_vcxo_i : in STD_LOGIC;
+ gtp_dedicated_clk_p_i : in STD_LOGIC;
+ gtp_dedicated_clk_n_i : in STD_LOGIC;
+ clk_dmtd_o : out STD_LOGIC;
+ clk_ref_o : out STD_LOGIC;
+ clk_rx_rbclk_o : out STD_LOGIC;
+ gtp0_activity_led_o : out STD_LOGIC;
+ gtp0_synced_led_o : out STD_LOGIC;
+ gtp0_link_led_o : out STD_LOGIC;
+ gtp0_wrmode_led_o : out STD_LOGIC;
+ dac_sclk_o : out STD_LOGIC;
+ dac_din_o : out STD_LOGIC;
+ dac_cs1_n_o : out STD_LOGIC;
+ dac_cs2_n_o : out STD_LOGIC;
+ fpga_scl_b : inout STD_LOGIC;
+ fpga_sda_b : inout STD_LOGIC;
+ button_rst_n_i : in STD_LOGIC;
+ thermo_id : inout STD_LOGIC;
+ gtp0_txp_o : out STD_LOGIC;
+ gtp0_txn_o : out STD_LOGIC;
+ gtp0_rxp_i : in STD_LOGIC;
+ gtp0_rxn_i : in STD_LOGIC;
+ gtp0_mod_def0_b : in STD_LOGIC;
+ gtp0_mod_def1_b : inout STD_LOGIC;
+ gtp0_mod_def2_b : inout STD_LOGIC;
+ gtp0_rate_select_b : inout STD_LOGIC;
+ gtp0_tx_fault_i : in STD_LOGIC;
+ gtp0_tx_disable_o : out STD_LOGIC;
+ gtp0_los_i : in STD_LOGIC;
+ uart_rxd_i : in STD_LOGIC;
+ uart_txd_o : out STD_LOGIC;
+ ext_clk_i : in STD_LOGIC;
+ pps_i : in STD_LOGIC;
+ pps_ctrl_o : out STD_LOGIC;
+ term_en_o : out STD_LOGIC;
+ pps_o : out STD_LOGIC;
axi_int_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aclk_o : out STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -4036,8 +4070,8 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_0_1;
- component system_design_axi_wb_i2c_master_2_0 is
+ end component system_design_wrc_1p_kintex7_0_0;
+ component system_design_axi_wb_i2c_master_0_1 is
port (
i2c_scl_io : inout STD_LOGIC;
i2c_sda_io : inout STD_LOGIC;
@@ -4064,47 +4098,13 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_2_0;
- component system_design_wrc_1p_kintex7_0_0 is
+ end component system_design_axi_wb_i2c_master_0_1;
+ component system_design_axi_wb_i2c_master_2_0 is
port (
- clk_20m_vcxo_i : in STD_LOGIC;
- gtp_dedicated_clk_p_i : in STD_LOGIC;
- gtp_dedicated_clk_n_i : in STD_LOGIC;
- clk_dmtd_o : out STD_LOGIC;
- clk_ref_o : out STD_LOGIC;
- clk_rx_rbclk_o : out STD_LOGIC;
- gtp0_activity_led_o : out STD_LOGIC;
- gtp0_synced_led_o : out STD_LOGIC;
- gtp0_link_led_o : out STD_LOGIC;
- gtp0_wrmode_led_o : out STD_LOGIC;
- dac_sclk_o : out STD_LOGIC;
- dac_din_o : out STD_LOGIC;
- dac_cs1_n_o : out STD_LOGIC;
- dac_cs2_n_o : out STD_LOGIC;
- fpga_scl_b : inout STD_LOGIC;
- fpga_sda_b : inout STD_LOGIC;
- button_rst_n_i : in STD_LOGIC;
- thermo_id : inout STD_LOGIC;
- gtp0_txp_o : out STD_LOGIC;
- gtp0_txn_o : out STD_LOGIC;
- gtp0_rxp_i : in STD_LOGIC;
- gtp0_rxn_i : in STD_LOGIC;
- gtp0_mod_def0_b : in STD_LOGIC;
- gtp0_mod_def1_b : inout STD_LOGIC;
- gtp0_mod_def2_b : inout STD_LOGIC;
- gtp0_rate_select_b : inout STD_LOGIC;
- gtp0_tx_fault_i : in STD_LOGIC;
- gtp0_tx_disable_o : out STD_LOGIC;
- gtp0_los_i : in STD_LOGIC;
- uart_rxd_i : in STD_LOGIC;
- uart_txd_o : out STD_LOGIC;
- ext_clk_i : in STD_LOGIC;
- pps_i : in STD_LOGIC;
- pps_ctrl_o : out STD_LOGIC;
- term_en_o : out STD_LOGIC;
- pps_o : out STD_LOGIC;
+ i2c_scl_io : inout STD_LOGIC;
+ i2c_sda_io : inout STD_LOGIC;
axi_int_o : out STD_LOGIC;
- s00_axi_aclk_o : out STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -4126,7 +4126,7 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_wrc_1p_kintex7_0_0;
+ end component system_design_axi_wb_i2c_master_2_0;
component system_design_fasec_hwtest_0_0 is
port (
ps_clk_i : in STD_LOGIC;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
index f8fda8cc5fcc86bbce5854c4f85cd08e21921cf8..534783641da5f59a5dc9931528457b739980f5cc 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Jun 21 08:28:38 2017
+--Date : Wed Oct 11 12:10:21 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
index 13f99d33df24308eadfcdd2bcda92f93ece213ff..ec1637d74fa583a5dceddddb947c13b2c00a4b38 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Jun 21 08:28:39 2017" VIVADOVERSION="2016.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Oct 11 12:10:22 2017" VIVADOVERSION="2016.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
@@ -3325,7 +3325,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE FULLNAME="/axi_wb_i2c_master_0" HWVERSION="3.1.1" INSTANCE="axi_wb_i2c_master_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_wb_i2c_master" VLNV="cern.ch:ip:axi_wb_i2c_master:3.1.1">
+ <MODULE FULLNAME="/axi_wb_i2c_master_0" HWVERSION="3.1.2" INSTANCE="axi_wb_i2c_master_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_wb_i2c_master" VLNV="cern.ch:ip:axi_wb_i2c_master:3.1.2">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="C_S00_AXI_DATA_WIDTH" VALUE="32"/>
@@ -3501,7 +3501,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE FULLNAME="/axi_wb_i2c_master_2" HWVERSION="3.1.1" INSTANCE="axi_wb_i2c_master_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_wb_i2c_master" VLNV="cern.ch:ip:axi_wb_i2c_master:3.1.1">
+ <MODULE FULLNAME="/axi_wb_i2c_master_2" HWVERSION="3.1.2" INSTANCE="axi_wb_i2c_master_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_wb_i2c_master" VLNV="cern.ch:ip:axi_wb_i2c_master:3.1.2">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="C_S00_AXI_DATA_WIDTH" VALUE="32"/>
@@ -5585,8 +5585,6 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
<CONNECTION INSTANCE="xadc_wiz_0" PORT="s_axis_aclk"/>
<CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ACLK"/>
@@ -5600,6 +5598,8 @@
<CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ACLK"/>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ACLK"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="ps_clk_i"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aclk"/>
</CONNECTIONS>
@@ -7423,8 +7423,6 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
<CONNECTION INSTANCE="xadc_axis_fifo_adapter_0" PORT="AXIS_RESET_N"/>
<CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M05_ARESETN"/>
@@ -7437,6 +7435,8 @@
<CONNECTION INSTANCE="axi_interconnect_0" PORT="ARESETN"/>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ARESETN"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aresetn"/>
</CONNECTIONS>
</PORT>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
index df3d9373174b3395a1e7b348281098c63f23020c..74e9e14d592f2d3108b64260e7f4c87d6419aabc 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
@@ -241,10 +241,10 @@ CONFIG.C_S_AXI_ACLK_FREQ_HZ.VALUE_SRC {DEFAULT} \
] $axi_uartlite_0
# Create instance: axi_wb_i2c_master_0, and set properties
- set axi_wb_i2c_master_0 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.1 axi_wb_i2c_master_0 ]
+ set axi_wb_i2c_master_0 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.2 axi_wb_i2c_master_0 ]
# Create instance: axi_wb_i2c_master_2, and set properties
- set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.1 axi_wb_i2c_master_2 ]
+ set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.2 axi_wb_i2c_master_2 ]
# Create instance: fasec_hwtest_0, and set properties
set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.6 fasec_hwtest_0 ]
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp
index 5287df61f5db84aca4c63e78d3237929066a231b..a62c52a6bcc8046fab1fd5e9d79836d328d3351a 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
index 5d6087192ceb1f28d1424608f71e6d762ff591a3..ad62d951175f3f9888d226b1fe53982816239d6d 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:31:04 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:12:58 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
index 558528064191970e093c3411bd1d620278a8a958..e311ba4a471a1ba48f936a5a8fec52916eae3923 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:31:04 2017
+// Date : Wed Oct 11 12:12:57 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
index 1df42fbcd73731c115a61c321b09fdf1d6b6f894..75d35e9765624ec9123951b649a974d8dc8e1362 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:31:04 2017
+-- Date : Wed Oct 11 12:12:58 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
index 680442160c7873beba318c2d3a0ff0cf93d75f6a..af952f035054afa8e14bf22a91d02d25df344b28 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:31:03 2017
+// Date : Wed Oct 11 12:12:57 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
index a4ff5339d707bd4c4541cf5a28fae5fabaedd6d9..0a4bc7c46aff2dd8702512fc3fc1f59580889623 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:31:03 2017
+-- Date : Wed Oct 11 12:12:57 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp
index 36b707b7a48bffaaea4f6d86bb8854851e44ee68..6df33b46ddae233a42e67984b783263bf91ba83b 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
index a08c555444ddce17c536249acf5457bd344776f7..7c88c8eaec212a9abaa7ea56c2b8944ca5156486 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:31:05 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:13:55 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
index 684f4b75d626db846fde8a7bd344a319d3c046b9..27c2b32218104e538aa57d2efcfcc0b27de36a0c 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:31:05 2017
+// Date : Wed Oct 11 12:13:55 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
index 407afaca9f39a2c74e3f20638f0ae40cc78a3cfb..dc908c5ad4377d0d79a7544d0e475255d2fef359 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:31:05 2017
+-- Date : Wed Oct 11 12:13:55 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
index 9a4827369b5f67f79f6d888639472a22a525d292..6bfe59a711451407e89fc8fb9619f524c1213e1c 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:31:05 2017
+// Date : Wed Oct 11 12:13:55 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
index bc76f2dcca5d9760cb77ff35f49dff2aa64332a6..99e491d3eb822257ccdb0e4b935b7fe91de85151 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:31:05 2017
+-- Date : Wed Oct 11 12:13:55 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp
index 3a02a4392994867c30ec21d270cc3dc78abe0097..2c5a520c7d0d3e83f0ab475074d94ca5d888c6e6 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
index 0afc43e931c249f30e519268d88cece88bfd469a..86bacb9a0875b69288d01bd3c48e1bb3ddcec439 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:39 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:31:07 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:13:53 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
index 098d8675f38142fd35082dc719ce1aa82526e575..def2e2dcd3d32a2a41cb5a3ef2ddf85b2f656b3e 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:31:07 2017
+// Date : Wed Oct 11 12:13:53 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
index 87c353c29b8875a05dfdfd8b39ce8517c15bafbf..b37e8a4b494dee776f523e32abfc7833a0bebda9 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:31:07 2017
+-- Date : Wed Oct 11 12:13:53 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
index c1eb02ad68bf53b91f91c2c9265fc932b439748d..21ed452983319d782c5d2b2d83661601be4e07f0 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:31:07 2017
+// Date : Wed Oct 11 12:13:53 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
index b9e27f43fcf063b2c99ec874aa396d5ef0f87daf..8de6d7e061ae589daffc32164877246f45db15b7 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:31:07 2017
+-- Date : Wed Oct 11 12:13:53 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd
index 4657c9fc3a8d73bc4ce1b6f609db701a92eb1466..14acdc5e54dcb294788c6e66ea473c07d125cc94 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.1
--- IP Revision: 5
+-- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.2
+-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/synth/system_design_axi_wb_i2c_master_0_1.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/synth/system_design_axi_wb_i2c_master_0_1.vhd
index 3cf8f65ce5db86fe7244e105a7a5d5828d7a6eaf..18422dc74a4ecc0ce9fc977e9d9c916179c3993a 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/synth/system_design_axi_wb_i2c_master_0_1.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/synth/system_design_axi_wb_i2c_master_0_1.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.1
--- IP Revision: 5
+-- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.2
+-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.dcp
index 10ff6c5e58d327fd0dc5a8b62d6bdcd47fdbe6c6..8de2b69afa6769ca33df174d5f468056dbac5410 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci
index 003efdbc979c045eae7ffa65b0c2f931ca284cdd..0674b07e6145f08a63eff3d50f313f72c231d256 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci
@@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_axi_wb_i2c_master_0_1</spirit:instanceName>
- <spirit:componentRef spirit:vendor="cern.ch" spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:version="3.1.1"/>
+ <spirit:componentRef spirit:vendor="cern.ch" spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:version="3.1.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
@@ -55,7 +55,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
index 345e9e5f3ac3ccb2ff9e762267294acce517090b..e95191fa67c2a6c43f56da0f781a0815736d6782 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
@@ -344,7 +344,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -356,7 +356,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>342d0b43</spirit:value>
+ <spirit:value>a1a0d50a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -375,7 +375,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -387,7 +387,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>342d0b43</spirit:value>
+ <spirit:value>a1a0d50a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -405,7 +405,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -417,7 +417,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>66f9670f</spirit:value>
+ <spirit:value>ce412196</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -436,7 +436,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -448,7 +448,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>66f9670f</spirit:value>
+ <spirit:value>ce412196</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -466,7 +466,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Jun 20 18:06:19 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:12:04 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -478,7 +478,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>342d0b43</spirit:value>
+ <spirit:value>a1a0d50a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -897,68 +897,68 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
@@ -974,72 +974,72 @@
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
@@ -1109,7 +1109,7 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>axi_wb_i2c_master</xilinx:displayName>
- <xilinx:coreRevision>5</xilinx:coreRevision>
+ <xilinx:coreRevision>6</xilinx:coreRevision>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:axi_wb_i2c_master:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
<xilinx:tag xilinx:name="cern.ch:user:axi_wb_i2c_master:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
@@ -1117,6 +1117,7 @@
<xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
<xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
<xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.1.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
+ <xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.1.2_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
</xilinx:tags>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="user"/>
@@ -1151,7 +1152,7 @@
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2951d2ef"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e9d260ec"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af3e2a36"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="1a573fc4"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="15a214e0"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="675c1650"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
index a4bceb7fe25adae9e77849d7793a202974eb2728..81286535ebb71c2d72de6c89014ba97e4a79abf8 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Tue Jun 20 20:06:19 2017
+// Date : Wed Oct 11 12:12:03 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
@@ -65,8 +65,8 @@ module system_design_axi_wb_i2c_master_0_1
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *) input s00_axi_rready;
wire axi_int_o;
- wire i2c_scl_io;
- wire i2c_sda_io;
+ (* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "FAST" *) wire i2c_scl_io;
+ (* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "FAST" *) wire i2c_sda_io;
wire s00_axi_aclk;
wire [31:0]s00_axi_araddr;
wire s00_axi_aresetn;
@@ -82,7 +82,7 @@ module system_design_axi_wb_i2c_master_0_1
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
- wire [1:0]s00_axi_rresp;
+ (* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "FAST" *) wire [1:0]s00_axi_rresp;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire s00_axi_wready;
@@ -182,8 +182,8 @@ module system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
wire cmp_axis_wbm_bridge_n_19;
wire cmp_axis_wbm_bridge_n_21;
wire cmp_axis_wbm_bridge_n_7;
- wire cmp_i2c_master_top_n_4;
- wire cmp_i2c_master_top_n_5;
+ wire cmp_i2c_master_top_n_6;
+ wire cmp_i2c_master_top_n_7;
wire ena;
wire i2c_scl_io;
wire i2c_sda_io;
@@ -204,6 +204,10 @@ module system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
wire [31:0]s00_axi_wdata;
wire s00_axi_wready;
wire s00_axi_wvalid;
+ wire scl_pad_i;
+ wire scl_padoen_o;
+ wire sda_pad_i;
+ wire sda_padoen_o;
wire wb_ack_i;
wire [2:0]wb_adr_o;
wire wb_cyc_o;
@@ -250,8 +254,8 @@ module system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
.\cr_reg[4] (cmp_axis_wbm_bridge_n_16),
.\ctr_reg[0] (cmp_axis_wbm_bridge_n_19),
.iack_o_reg(cmp_axis_wbm_bridge_n_21),
- .iack_o_reg_0(cmp_i2c_master_top_n_4),
- .iack_o_reg_1(cmp_i2c_master_top_n_5),
+ .iack_o_reg_0(cmp_i2c_master_top_n_6),
+ .iack_o_reg_1(cmp_i2c_master_top_n_7),
.\prer_reg[8] ({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_araddr(s00_axi_araddr[4:2]),
@@ -281,8 +285,6 @@ module system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
.E({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
.Q(ena),
.axi_int_o(axi_int_o),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
.iack_o_reg_0(cmp_axis_wbm_bridge_n_16),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
@@ -290,17 +292,37 @@ module system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_wdata(s00_axi_wdata[7:0]),
.\s_addr_reg[4] (cmp_axis_wbm_bridge_n_7),
- .\s_rdata_reg[0] (cmp_i2c_master_top_n_5),
+ .\s_rdata_reg[0] (cmp_i2c_master_top_n_7),
.\s_rdata_reg[7] (wb_dat_o),
- .s_stb_r_reg(cmp_i2c_master_top_n_4),
+ .s_stb_r_reg(cmp_i2c_master_top_n_6),
.s_stb_r_reg_0(cmp_axis_wbm_bridge_n_21),
.s_we_r_reg(cmp_axis_wbm_bridge_n_19),
.s_we_r_reg_0(cmp_axis_wbm_bridge_n_11),
+ .scl_pad_i(scl_pad_i),
+ .scl_padoen_o(scl_padoen_o),
+ .sda_pad_i(sda_pad_i),
+ .sda_padoen_o(sda_padoen_o),
.wb_ack_i(wb_ack_i),
.wb_adr_o(wb_adr_o),
.wb_cyc_o(wb_cyc_o),
.wb_rst_o(wb_rst_o),
.wb_we_o(wb_we_o));
+ (* box_type = "PRIMITIVE" *)
+ IOBUF #(
+ .IOSTANDARD("DEFAULT"))
+ iobuf_i2c_scl
+ (.I(1'b0),
+ .IO(i2c_scl_io),
+ .O(scl_pad_i),
+ .T(scl_padoen_o));
+ (* box_type = "PRIMITIVE" *)
+ IOBUF #(
+ .IOSTANDARD("DEFAULT"))
+ iobuf_i2c_sda
+ (.I(1'b0),
+ .IO(i2c_sda_io),
+ .O(sda_pad_i),
+ .T(sda_padoen_o));
endmodule
(* ORIG_REF_NAME = "axis_wbm_bridge" *)
@@ -771,6 +793,8 @@ endmodule
(* ORIG_REF_NAME = "i2c_master_bit_ctrl" *)
module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
(iscl_oen_reg_0,
+ dscl_oen_reg_0,
+ sda_padoen_o,
E,
irq_flag1_out,
al,
@@ -784,8 +808,6 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
\cr_reg[4] ,
\sr_reg[0] ,
\FSM_sequential_statemachine.c_state_reg[2] ,
- i2c_sda_io,
- i2c_scl_io,
s00_axi_aclk,
s00_axi_aresetn,
out,
@@ -794,6 +816,8 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
irq_flag,
Q,
\ctr_reg[7] ,
+ sda_pad_i,
+ scl_pad_i,
\statemachine.core_cmd_reg[3]_0 ,
\st_irq_block.al_reg ,
\cr_reg[7] ,
@@ -816,6 +840,8 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
\cr_reg[7]_0 ,
\statemachine.core_txd_reg_0 );
output iscl_oen_reg_0;
+ output dscl_oen_reg_0;
+ output sda_padoen_o;
output [0:0]E;
output irq_flag1_out;
output al;
@@ -829,8 +855,6 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
output [0:0]\cr_reg[4] ;
output [0:0]\sr_reg[0] ;
output [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
input s00_axi_aclk;
input s00_axi_aresetn;
input [2:0]out;
@@ -839,6 +863,8 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
input irq_flag;
input [15:0]Q;
input [0:0]\ctr_reg[7] ;
+ input sda_pad_i;
+ input scl_pad_i;
input [3:0]\statemachine.core_cmd_reg[3]_0 ;
input \st_irq_block.al_reg ;
input [3:0]\cr_reg[7] ;
@@ -1019,13 +1045,10 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
wire dSCL;
wire dSDA;
wire dscl_oen;
+ wire dscl_oen_reg_0;
wire [13:0]filter_cnt;
wire i2c_al;
wire i2c_busy;
- wire i2c_scl_io;
- wire i2c_scl_io_INST_0_i_1_n_0;
- wire i2c_sda_io;
- wire i2c_sda_io_INST_0_i_1_n_0;
wire iack_o_reg;
wire iack_o_reg_0;
wire ial;
@@ -1085,9 +1108,10 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
wire s00_axi_aresetn;
wire sSCL;
wire sSDA;
- wire scl_padoen_o;
+ wire scl_pad_i;
wire sda_chk_i_1_n_0;
wire sda_chk_reg_n_0;
+ wire sda_pad_i;
wire sda_padoen_o;
wire slave_wait;
wire slave_wait0;
@@ -1319,13 +1343,14 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.I4(\cr_reg[7] [1]),
.I5(\cr_reg[7] [2]),
.O(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSCL[0]_i_1
(.I0(s00_axi_aresetn),
- .I1(i2c_scl_io),
+ .I1(scl_pad_i),
.O(\bus_status_ctrl.cSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSCL[1]_i_1
@@ -1344,13 +1369,14 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(\bus_status_ctrl.cSCL[1]_i_1_n_0 ),
.Q(p_0_in__1[0]));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSDA[0]_i_1
(.I0(s00_axi_aresetn),
- .I1(i2c_sda_io),
+ .I1(sda_pad_i),
.O(\bus_status_ctrl.cSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSDA[1]_i_1
@@ -1404,7 +1430,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.D(\bus_status_ctrl.dSCL_i_1_n_0 ),
.PRE(iscl_oen_reg_0),
.Q(dSCL));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.dSDA_i_1
@@ -1431,21 +1457,21 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(\bus_status_ctrl.dout_i_1_n_0 ),
.Q(core_rxd));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSCL[0]_i_1
(.I0(p_0_in__1[0]),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSCL[1]_i_1
(.I0(p_0_in__1[1]),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSCL[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSCL[2]_i_1
@@ -1470,14 +1496,14 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.D(\bus_status_ctrl.fSCL[2]_i_1_n_0 ),
.PRE(iscl_oen_reg_0),
.Q(\bus_status_ctrl.fSCL_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSDA[0]_i_1
(.I0(\bus_status_ctrl.cSDA_reg_n_0_[1] ),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSDA[1]_i_1
@@ -1490,7 +1516,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
(.I0(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSDA[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSDA[2]_i_2
@@ -1784,7 +1810,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(ial),
.Q(i2c_al));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h5400))
\bus_status_ctrl.ibusy_i_1
@@ -1799,7 +1825,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(ibusy),
.Q(i2c_busy));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hE8FF))
\bus_status_ctrl.sSCL_i_1
@@ -1828,7 +1854,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.D(\bus_status_ctrl.sSDA_i_1_n_0 ),
.PRE(iscl_oen_reg_0),
.Q(sSDA));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h2000))
\bus_status_ctrl.sta_condition_i_1
@@ -1843,7 +1869,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(sta_condition),
.Q(\bus_status_ctrl.sta_condition_reg_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h4000))
\bus_status_ctrl.sto_condition_i_1
@@ -1873,7 +1899,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
clk_en_i_2
(.I0(\ctr_reg[7] ),
.I1(sSCL),
- .I2(scl_padoen_o),
+ .I2(dscl_oen_reg_0),
.I3(dSCL),
.I4(s00_axi_aresetn),
.O(clk_en_i_2_n_0));
@@ -2299,41 +2325,8 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg_0),
- .D(scl_padoen_o),
+ .D(dscl_oen_reg_0),
.Q(dscl_oen));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_scl_io_INST_0
- (.I0(1'b0),
- .I1(i2c_scl_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_scl_io));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_scl_io_INST_0_i_1
- (.I0(scl_padoen_o),
- .O(i2c_scl_io_INST_0_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_sda_io_INST_0
- (.I0(1'b0),
- .I1(i2c_sda_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_sda_io));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_sda_io_INST_0_i_1
- (.I0(sda_padoen_o),
- .O(i2c_sda_io_INST_0_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFBFFFBF3))
iscl_oen_i_1
@@ -2341,7 +2334,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.I1(s00_axi_aresetn),
.I2(i2c_al),
.I3(iscl_oen9_out__0),
- .I4(scl_padoen_o),
+ .I4(dscl_oen_reg_0),
.O(iscl_oen_i_1_n_0));
LUT5 #(
.INIT(32'h00F3011F))
@@ -2366,8 +2359,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.CE(1'b1),
.D(iscl_oen_i_1_n_0),
.PRE(iscl_oen_reg_0),
- .Q(scl_padoen_o));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
+ .Q(dscl_oen_reg_0));
LUT5 #(
.INIT(32'hFBFFFBF3))
isda_oen_i_1
@@ -2516,7 +2508,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.INIT(16'h0F04))
slave_wait_i_1
(.I0(dscl_oen),
- .I1(scl_padoen_o),
+ .I1(dscl_oen_reg_0),
.I2(sSCL),
.I3(slave_wait),
.O(slave_wait0));
@@ -2526,7 +2518,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(slave_wait0),
.Q(slave_wait));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hE400))
\sr[0]_i_1
@@ -2535,7 +2527,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.I2(\txr_reg[6] [0]),
.I3(s00_axi_aresetn),
.O(\sr_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hAA08))
\st_irq_block.al_i_1
@@ -2598,7 +2590,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.I4(out[0]),
.I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
.O(\statemachine.core_cmd_reg[3] [1]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h08))
\statemachine.core_cmd[2]_i_1
@@ -2606,7 +2598,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.I1(s00_axi_aresetn),
.I2(i2c_al),
.O(\statemachine.core_cmd_reg[3] [2]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0040))
\statemachine.core_cmd[3]_i_1
@@ -2615,7 +2607,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
.I2(s00_axi_aresetn),
.I3(i2c_al),
.O(\statemachine.core_cmd_reg[3] [3]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h08))
\statemachine.core_txd_i_1
@@ -2681,19 +2673,21 @@ endmodule
(* ORIG_REF_NAME = "i2c_master_byte_ctrl" *)
module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
(iscl_oen_reg,
+ dscl_oen_reg,
+ sda_padoen_o,
irq_flag1_out,
rxack_0,
al,
D,
E,
- i2c_sda_io,
- i2c_scl_io,
s00_axi_aclk,
s00_axi_aresetn,
\cr_reg[0] ,
irq_flag,
Q,
\ctr_reg[7] ,
+ sda_pad_i,
+ scl_pad_i,
\st_irq_block.al_reg ,
\cr_reg[7] ,
wb_adr_o,
@@ -2708,19 +2702,21 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
wb_we_o,
iack_o_reg_0);
output iscl_oen_reg;
+ output dscl_oen_reg;
+ output sda_padoen_o;
output irq_flag1_out;
output rxack_0;
output al;
output [7:0]D;
output [0:0]E;
- inout i2c_sda_io;
- inout i2c_scl_io;
input s00_axi_aclk;
input s00_axi_aresetn;
input \cr_reg[0] ;
input irq_flag;
input [15:0]Q;
input [7:0]\ctr_reg[7] ;
+ input sda_pad_i;
+ input scl_pad_i;
input \st_irq_block.al_reg ;
input [3:0]\cr_reg[7] ;
input [2:0]wb_adr_o;
@@ -2748,12 +2744,12 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
wire bit_ctrl_n_11;
wire bit_ctrl_n_12;
wire bit_ctrl_n_13;
+ wire bit_ctrl_n_14;
wire bit_ctrl_n_15;
- wire bit_ctrl_n_16;
wire bit_ctrl_n_17;
wire bit_ctrl_n_18;
- wire bit_ctrl_n_5;
- wire bit_ctrl_n_6;
+ wire bit_ctrl_n_19;
+ wire bit_ctrl_n_20;
wire bit_ctrl_n_7;
wire bit_ctrl_n_8;
wire bit_ctrl_n_9;
@@ -2779,8 +2775,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
wire \dcnt_reg_n_0_[1] ;
wire \dcnt_reg_n_0_[2] ;
wire [7:7]dout;
- wire i2c_scl_io;
- wire i2c_sda_io;
+ wire dscl_oen_reg;
wire iack_o_reg;
wire iack_o_reg_0;
wire irq_flag;
@@ -2789,6 +2784,9 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
wire rxack_0;
wire s00_axi_aclk;
wire s00_axi_aresetn;
+ wire scl_pad_i;
+ wire sda_pad_i;
+ wire sda_padoen_o;
wire \sr[1]_i_1_n_0 ;
wire \sr[2]_i_1_n_0 ;
wire \sr[3]_i_1_n_0 ;
@@ -2860,21 +2858,21 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_18),
+ .D(bit_ctrl_n_20),
.Q(c_state__0[0]));
(* KEEP = "yes" *)
FDCE \FSM_sequential_statemachine.c_state_reg[1]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_17),
+ .D(bit_ctrl_n_19),
.Q(c_state__0[1]));
(* KEEP = "yes" *)
FDCE \FSM_sequential_statemachine.c_state_reg[2]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_16),
+ .D(bit_ctrl_n_18),
.Q(c_state__0[2]));
system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl bit_ctrl
(.D(D[6]),
@@ -2883,7 +2881,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.\FSM_sequential_statemachine.c_state_reg[1]_0 (\statemachine.core_cmd[1]_i_2_n_0 ),
.\FSM_sequential_statemachine.c_state_reg[1]_1 (\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ),
.\FSM_sequential_statemachine.c_state_reg[1]_2 (\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_16,bit_ctrl_n_17,bit_ctrl_n_18}),
+ .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_18,bit_ctrl_n_19,bit_ctrl_n_20}),
.Q(Q),
.ack_in(ack_in),
.ack_out(ack_out),
@@ -2896,8 +2894,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.\cr_reg[7] (\cr_reg[7] ),
.\cr_reg[7]_0 (\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ),
.\ctr_reg[7] (\ctr_reg[7] [7]),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
+ .dscl_oen_reg_0(dscl_oen_reg),
.iack_o_reg(iack_o_reg),
.iack_o_reg_0(iack_o_reg_0),
.irq_flag(irq_flag),
@@ -2906,23 +2903,26 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.out(c_state__0),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
- .\sr_reg[0] (bit_ctrl_n_15),
+ .scl_pad_i(scl_pad_i),
+ .sda_pad_i(sda_pad_i),
+ .sda_padoen_o(sda_padoen_o),
+ .\sr_reg[0] (bit_ctrl_n_17),
.\sr_reg[6] (\wb_dat_o[6]_i_2_n_0 ),
.\sr_reg[7] (dout),
.\st_irq_block.al_reg (\st_irq_block.al_reg ),
- .\statemachine.ack_out_reg (bit_ctrl_n_13),
- .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_5,bit_ctrl_n_6,bit_ctrl_n_7,bit_ctrl_n_8}),
+ .\statemachine.ack_out_reg (bit_ctrl_n_15),
+ .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_7,bit_ctrl_n_8,bit_ctrl_n_9,bit_ctrl_n_10}),
.\statemachine.core_cmd_reg[3]_0 (cmd),
- .\statemachine.core_txd_reg (bit_ctrl_n_10),
+ .\statemachine.core_txd_reg (bit_ctrl_n_12),
.\statemachine.core_txd_reg_0 (\statemachine.core_txd_reg_n_0 ),
- .\statemachine.host_ack_reg (bit_ctrl_n_12),
- .\statemachine.ld_reg (bit_ctrl_n_9),
+ .\statemachine.host_ack_reg (bit_ctrl_n_14),
+ .\statemachine.ld_reg (bit_ctrl_n_11),
.\statemachine.ld_reg_0 (\statemachine.ld_reg_n_0 ),
- .\statemachine.shift_reg (bit_ctrl_n_11),
+ .\statemachine.shift_reg (bit_ctrl_n_13),
.\txr_reg[6] ({\txr_reg[7] [6],\txr_reg[7] [0]}),
.wb_adr_o(wb_adr_o),
.wb_we_o(wb_we_o));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h8A))
\dcnt[0]_i_1
@@ -2930,7 +2930,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.I1(\statemachine.ld_reg_n_0 ),
.I2(\dcnt_reg_n_0_[0] ),
.O(\dcnt[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hA88A))
\dcnt[1]_i_1
@@ -2939,7 +2939,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.I2(\dcnt_reg_n_0_[0] ),
.I3(\dcnt_reg_n_0_[1] ),
.O(\dcnt[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hAAA8888A))
\dcnt[2]_i_1
@@ -2967,7 +2967,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.CLR(iscl_oen_reg),
.D(\dcnt[2]_i_1_n_0 ),
.Q(\dcnt_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hE400))
\sr[1]_i_1
@@ -2976,7 +2976,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.I2(\txr_reg[7] [1]),
.I3(s00_axi_aresetn),
.O(\sr[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hE400))
\sr[2]_i_1
@@ -3036,7 +3036,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(dcnt),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_15),
+ .D(bit_ctrl_n_17),
.Q(\sr_reg_n_0_[0] ));
FDCE \sr_reg[1]
(.C(s00_axi_aclk),
@@ -3080,7 +3080,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
.CLR(iscl_oen_reg),
.D(\sr[7]_i_2_n_0 ),
.Q(dout));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\st_irq_block.rxack_i_1
@@ -3091,7 +3091,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_13),
+ .D(bit_ctrl_n_15),
.Q(ack_out));
LUT5 #(
.INIT(32'h00000001))
@@ -3126,49 +3126,49 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_8),
+ .D(bit_ctrl_n_10),
.Q(cmd[0]));
FDCE \statemachine.core_cmd_reg[1]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_7),
+ .D(bit_ctrl_n_9),
.Q(cmd[1]));
FDCE \statemachine.core_cmd_reg[2]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_6),
+ .D(bit_ctrl_n_8),
.Q(cmd[2]));
FDCE \statemachine.core_cmd_reg[3]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_5),
+ .D(bit_ctrl_n_7),
.Q(cmd[3]));
FDCE \statemachine.core_txd_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_10),
+ .D(bit_ctrl_n_12),
.Q(\statemachine.core_txd_reg_n_0 ));
FDCE \statemachine.host_ack_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_12),
+ .D(bit_ctrl_n_14),
.Q(cmd_ack));
FDCE \statemachine.ld_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_9),
+ .D(bit_ctrl_n_11),
.Q(\statemachine.ld_reg_n_0 ));
FDCE \statemachine.shift_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_11),
+ .D(bit_ctrl_n_13),
.Q(\statemachine.shift_reg_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
@@ -3306,16 +3306,18 @@ endmodule
module system_design_axi_wb_i2c_master_0_1_i2c_master_top
(wb_ack_i,
wb_rst_o,
+ scl_padoen_o,
axi_int_o,
+ sda_padoen_o,
Q,
s_stb_r_reg,
\s_rdata_reg[0] ,
\s_rdata_reg[7] ,
- i2c_sda_io,
- i2c_scl_io,
s_stb_r_reg_0,
s00_axi_aclk,
s00_axi_aresetn,
+ sda_pad_i,
+ scl_pad_i,
s00_axi_wdata,
wb_adr_o,
s00_axi_awvalid,
@@ -3330,16 +3332,18 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
\s_addr_reg[4] );
output wb_ack_i;
output wb_rst_o;
+ output scl_padoen_o;
output axi_int_o;
+ output sda_padoen_o;
output [0:0]Q;
output s_stb_r_reg;
output [0:0]\s_rdata_reg[0] ;
output [7:0]\s_rdata_reg[7] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
input s_stb_r_reg_0;
input s00_axi_aclk;
input s00_axi_aresetn;
+ input sda_pad_i;
+ input scl_pad_i;
input [7:0]s00_axi_wdata;
input [2:0]wb_adr_o;
input s00_axi_awvalid;
@@ -3359,7 +3363,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
wire ack_in;
wire al;
wire axi_int_o;
- wire byte_ctrl_n_12;
+ wire byte_ctrl_n_14;
wire \cr[0]_i_1_n_0 ;
wire \cr[1]_i_1_n_0 ;
wire \cr[2]_i_1_n_0 ;
@@ -3375,8 +3379,6 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
wire \ctr_reg_n_0_[4] ;
wire \ctr_reg_n_0_[5] ;
wire [13:0]data0;
- wire i2c_scl_io;
- wire i2c_sda_io;
wire iack_o_reg_0;
wire ien;
wire irq_flag;
@@ -3406,6 +3408,10 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
wire s_stb_r_reg_0;
wire [0:0]s_we_r_reg;
wire [0:0]s_we_r_reg_0;
+ wire scl_pad_i;
+ wire scl_padoen_o;
+ wire sda_pad_i;
+ wire sda_padoen_o;
wire \st_irq_block.al_reg_n_0 ;
wire \st_irq_block.wb_inta_o_i_1_n_0 ;
wire start;
@@ -3427,7 +3433,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl byte_ctrl
(.D(wb_dat_o),
- .E(byte_ctrl_n_12),
+ .E(byte_ctrl_n_14),
.Q({data0,\prer_reg_n_0_[1] ,\prer_reg_n_0_[0] }),
.ack_in(ack_in),
.al(al),
@@ -3439,8 +3445,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.\cr_reg[7] ({start,stop,read,write}),
.\cr_reg[7]_0 (\wb_dat_o[7]_i_3_n_0 ),
.\ctr_reg[7] ({Q,ien,\ctr_reg_n_0_[5] ,\ctr_reg_n_0_[4] ,\ctr_reg_n_0_[3] ,\ctr_reg_n_0_[2] ,\ctr_reg_n_0_[1] ,\ctr_reg_n_0_[0] }),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
+ .dscl_oen_reg(scl_padoen_o),
.iack_o_reg(wb_ack_i),
.iack_o_reg_0(iack_o_reg_0),
.irq_flag(irq_flag),
@@ -3449,6 +3454,9 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.rxack_0(rxack_0),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
+ .scl_pad_i(scl_pad_i),
+ .sda_pad_i(sda_pad_i),
+ .sda_padoen_o(sda_padoen_o),
.\st_irq_block.al_reg (\st_irq_block.al_reg_n_0 ),
.\txr_reg[7] (txr),
.wb_adr_o(wb_adr_o),
@@ -3483,7 +3491,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.I4(\s_addr_reg[4] ),
.I5(\cr_reg_n_0_[2] ),
.O(\cr[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'hC808))
\cr[3]_i_1
@@ -3518,78 +3526,78 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.Q(ack_in));
FDCE \cr_reg[4]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[0]),
.Q(write));
FDCE \cr_reg[5]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[1]),
.Q(read));
FDCE \cr_reg[6]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[2]),
.Q(stop));
FDCE \cr_reg[7]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[3]),
.Q(start));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\ctr[0]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[0]),
.O(ctr[0]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\ctr[1]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[1]),
.O(ctr[1]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\ctr[2]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[2]),
.O(ctr[2]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\ctr[3]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[3]),
.O(ctr[3]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\ctr[4]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[4]),
.O(ctr[4]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h8))
\ctr[5]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[5]),
.O(ctr[5]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h8))
\ctr[6]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[6]),
.O(ctr[6]));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h8))
\ctr[7]_i_2
@@ -3650,7 +3658,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.D(s_stb_r_reg_0),
.Q(wb_ack_i),
.R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'hB))
\prer[10]_i_1
@@ -3663,42 +3671,42 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
(.I0(s00_axi_wdata[3]),
.I1(s00_axi_aresetn),
.O(\prer[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'hB))
\prer[12]_i_1
(.I0(s00_axi_wdata[4]),
.I1(s00_axi_aresetn),
.O(\prer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'hB))
\prer[13]_i_1
(.I0(s00_axi_wdata[5]),
.I1(s00_axi_aresetn),
.O(\prer[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'hB))
\prer[14]_i_1
(.I0(s00_axi_wdata[6]),
.I1(s00_axi_aresetn),
.O(\prer[14]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'hB))
\prer[15]_i_2
(.I0(s00_axi_wdata[7]),
.I1(s00_axi_aresetn),
.O(\prer[15]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'hB))
\prer[8]_i_1
(.I0(s00_axi_wdata[0]),
.I1(s00_axi_aresetn),
.O(\prer[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'hB))
\prer[9]_i_1
@@ -3801,14 +3809,14 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.D(\prer[9]_i_1_n_0 ),
.PRE(wb_rst_o),
.Q(data0[7]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h2))
\s_rdata[7]_i_1
(.I0(wb_ack_i),
.I1(wb_we_o),
.O(\s_rdata_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hEFEE))
s_stb_r_i_1
@@ -3835,7 +3843,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.CLR(wb_rst_o),
.D(rxack_0),
.Q(rxack));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hA8))
\st_irq_block.tip_i_1
@@ -3849,7 +3857,7 @@ module system_design_axi_wb_i2c_master_0_1_i2c_master_top
.CLR(wb_rst_o),
.D(tip_1),
.Q(tip));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h80))
\st_irq_block.wb_inta_o_i_1
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
index 89015508238a9ae65448042936e326d3b85917ea..a04983be19e768fe0e5157a72c4569332fbbbb06 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Tue Jun 20 20:06:19 2017
+-- Date : Wed Oct 11 12:12:03 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
@@ -561,6 +561,8 @@ use UNISIM.VCOMPONENTS.ALL;
entity system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl is
port (
iscl_oen_reg_0 : out STD_LOGIC;
+ dscl_oen_reg_0 : out STD_LOGIC;
+ sda_padoen_o : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
irq_flag1_out : out STD_LOGIC;
al : out STD_LOGIC;
@@ -574,8 +576,6 @@ entity system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl is
\cr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\sr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_sequential_statemachine.c_state_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -584,6 +584,8 @@ entity system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl is
irq_flag : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sda_pad_i : in STD_LOGIC;
+ scl_pad_i : in STD_LOGIC;
\statemachine.core_cmd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\st_irq_block.al_reg\ : in STD_LOGIC;
\cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
@@ -752,11 +754,10 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctr
signal dSCL : STD_LOGIC;
signal dSDA : STD_LOGIC;
signal dscl_oen : STD_LOGIC;
+ signal \^dscl_oen_reg_0\ : STD_LOGIC;
signal filter_cnt : STD_LOGIC_VECTOR ( 13 downto 0 );
signal i2c_al : STD_LOGIC;
signal i2c_busy : STD_LOGIC;
- signal i2c_scl_io_INST_0_i_1_n_0 : STD_LOGIC;
- signal i2c_sda_io_INST_0_i_1_n_0 : STD_LOGIC;
signal ial : STD_LOGIC;
signal ibusy : STD_LOGIC;
signal iscl_oen : STD_LOGIC;
@@ -809,10 +810,9 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctr
signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sSCL : STD_LOGIC;
signal sSDA : STD_LOGIC;
- signal scl_padoen_o : STD_LOGIC;
signal sda_chk_i_1_n_0 : STD_LOGIC;
signal sda_chk_reg_n_0 : STD_LOGIC;
- signal sda_padoen_o : STD_LOGIC;
+ signal \^sda_padoen_o\ : STD_LOGIC;
signal slave_wait : STD_LOGIC;
signal slave_wait0 : STD_LOGIC;
signal sta_condition : STD_LOGIC;
@@ -830,33 +830,33 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctr
attribute KEEP of \FSM_sequential_c_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_sequential_c_state_reg[3]\ : label is "yes";
attribute KEEP of \FSM_sequential_c_state_reg[4]\ : label is "yes";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bus_status_ctrl.dSCL_i_1\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of clk_en_i_2 : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of i2c_scl_io_INST_0_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of i2c_sda_io_INST_0_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of iscl_oen_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of isda_oen_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \st_irq_block.irq_flag_i_1\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair14";
begin
+ dscl_oen_reg_0 <= \^dscl_oen_reg_0\;
iscl_oen_reg_0 <= \^iscl_oen_reg_0\;
+ sda_padoen_o <= \^sda_padoen_o\;
\FSM_sequential_c_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111110"
@@ -1125,7 +1125,7 @@ begin
)
port map (
I0 => s00_axi_aresetn,
- I1 => i2c_scl_io,
+ I1 => scl_pad_i,
O => \bus_status_ctrl.cSCL[0]_i_1_n_0\
);
\bus_status_ctrl.cSCL[1]_i_1\: unisim.vcomponents.LUT2
@@ -1159,7 +1159,7 @@ begin
)
port map (
I0 => s00_axi_aresetn,
- I1 => i2c_sda_io,
+ I1 => sda_pad_i,
O => \bus_status_ctrl.cSDA[0]_i_1_n_0\
);
\bus_status_ctrl.cSDA[1]_i_1\: unisim.vcomponents.LUT2
@@ -1706,7 +1706,7 @@ begin
I0 => s00_axi_aresetn,
I1 => sda_chk_reg_n_0,
I2 => sSDA,
- I3 => sda_padoen_o,
+ I3 => \^sda_padoen_o\,
I4 => \bus_status_ctrl.ial_i_2_n_0\,
I5 => \bus_status_ctrl.ial_i_3_n_0\,
O => ial
@@ -1854,7 +1854,7 @@ clk_en_i_2: unisim.vcomponents.LUT5
port map (
I0 => \ctr_reg[7]\(0),
I1 => sSCL,
- I2 => scl_padoen_o,
+ I2 => \^dscl_oen_reg_0\,
I3 => dSCL,
I4 => s00_axi_aresetn,
O => clk_en_i_2_n_0
@@ -2491,51 +2491,9 @@ dscl_oen_reg: unisim.vcomponents.FDCE
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg_0\,
- D => scl_padoen_o,
+ D => \^dscl_oen_reg_0\,
Q => dscl_oen
);
-i2c_scl_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_scl_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_scl_io
- );
-i2c_scl_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => scl_padoen_o,
- O => i2c_scl_io_INST_0_i_1_n_0
- );
-i2c_sda_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_sda_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_sda_io
- );
-i2c_sda_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => sda_padoen_o,
- O => i2c_sda_io_INST_0_i_1_n_0
- );
iscl_oen_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFFBF3"
@@ -2545,7 +2503,7 @@ iscl_oen_i_1: unisim.vcomponents.LUT5
I1 => s00_axi_aresetn,
I2 => i2c_al,
I3 => \iscl_oen9_out__0\,
- I4 => scl_padoen_o,
+ I4 => \^dscl_oen_reg_0\,
O => iscl_oen_i_1_n_0
);
iscl_oen_i_2: unisim.vcomponents.LUT5
@@ -2578,7 +2536,7 @@ iscl_oen_reg: unisim.vcomponents.FDPE
CE => '1',
D => iscl_oen_i_1_n_0,
PRE => \^iscl_oen_reg_0\,
- Q => scl_padoen_o
+ Q => \^dscl_oen_reg_0\
);
isda_oen_i_1: unisim.vcomponents.LUT5
generic map(
@@ -2589,7 +2547,7 @@ isda_oen_i_1: unisim.vcomponents.LUT5
I1 => s00_axi_aresetn,
I2 => i2c_al,
I3 => \isda_oen7_out__0\,
- I4 => sda_padoen_o,
+ I4 => \^sda_padoen_o\,
O => isda_oen_i_1_n_0
);
isda_oen_i_2: unisim.vcomponents.LUT6
@@ -2624,7 +2582,7 @@ isda_oen_reg: unisim.vcomponents.FDPE
CE => '1',
D => isda_oen_i_1_n_0,
PRE => \^iscl_oen_reg_0\,
- Q => sda_padoen_o
+ Q => \^sda_padoen_o\
);
minusOp_carry: unisim.vcomponents.CARRY4
port map (
@@ -2822,7 +2780,7 @@ slave_wait_i_1: unisim.vcomponents.LUT4
)
port map (
I0 => dscl_oen,
- I1 => scl_padoen_o,
+ I1 => \^dscl_oen_reg_0\,
I2 => sSCL,
I3 => slave_wait,
O => slave_wait0
@@ -3037,19 +2995,21 @@ use UNISIM.VCOMPONENTS.ALL;
entity system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl is
port (
iscl_oen_reg : out STD_LOGIC;
+ dscl_oen_reg : out STD_LOGIC;
+ sda_padoen_o : out STD_LOGIC;
irq_flag1_out : out STD_LOGIC;
rxack_0 : out STD_LOGIC;
al : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
\cr_reg[0]\ : in STD_LOGIC;
irq_flag : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ sda_pad_i : in STD_LOGIC;
+ scl_pad_i : in STD_LOGIC;
\st_irq_block.al_reg\ : in STD_LOGIC;
\cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -3077,12 +3037,12 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ct
signal bit_ctrl_n_11 : STD_LOGIC;
signal bit_ctrl_n_12 : STD_LOGIC;
signal bit_ctrl_n_13 : STD_LOGIC;
+ signal bit_ctrl_n_14 : STD_LOGIC;
signal bit_ctrl_n_15 : STD_LOGIC;
- signal bit_ctrl_n_16 : STD_LOGIC;
signal bit_ctrl_n_17 : STD_LOGIC;
signal bit_ctrl_n_18 : STD_LOGIC;
- signal bit_ctrl_n_5 : STD_LOGIC;
- signal bit_ctrl_n_6 : STD_LOGIC;
+ signal bit_ctrl_n_19 : STD_LOGIC;
+ signal bit_ctrl_n_20 : STD_LOGIC;
signal bit_ctrl_n_7 : STD_LOGIC;
signal bit_ctrl_n_8 : STD_LOGIC;
signal bit_ctrl_n_9 : STD_LOGIC;
@@ -3135,12 +3095,12 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ct
attribute KEEP of \FSM_sequential_statemachine.c_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_statemachine.c_state_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair22";
begin
iscl_oen_reg <= \^iscl_oen_reg\;
\FSM_sequential_statemachine.c_state[0]_i_2\: unisim.vcomponents.LUT5
@@ -3194,7 +3154,7 @@ begin
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_18,
+ D => bit_ctrl_n_20,
Q => \c_state__0\(0)
);
\FSM_sequential_statemachine.c_state_reg[1]\: unisim.vcomponents.FDCE
@@ -3202,7 +3162,7 @@ begin
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_17,
+ D => bit_ctrl_n_19,
Q => \c_state__0\(1)
);
\FSM_sequential_statemachine.c_state_reg[2]\: unisim.vcomponents.FDCE
@@ -3210,7 +3170,7 @@ begin
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_16,
+ D => bit_ctrl_n_18,
Q => \c_state__0\(2)
);
bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
@@ -3221,9 +3181,9 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
\FSM_sequential_statemachine.c_state_reg[1]_0\ => \statemachine.core_cmd[1]_i_2_n_0\,
\FSM_sequential_statemachine.c_state_reg[1]_1\ => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\,
\FSM_sequential_statemachine.c_state_reg[1]_2\ => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\,
- \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_16,
- \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_17,
- \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_18,
+ \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_18,
+ \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_19,
+ \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_20,
Q(15 downto 0) => Q(15 downto 0),
ack_in => ack_in,
ack_out => ack_out,
@@ -3236,8 +3196,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
\cr_reg[7]\(3 downto 0) => \cr_reg[7]\(3 downto 0),
\cr_reg[7]_0\ => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\,
\ctr_reg[7]\(0) => \ctr_reg[7]\(7),
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
+ dscl_oen_reg_0 => dscl_oen_reg,
iack_o_reg => iack_o_reg,
iack_o_reg_0 => iack_o_reg_0,
irq_flag => irq_flag,
@@ -3246,22 +3205,25 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
\out\(2 downto 0) => \c_state__0\(2 downto 0),
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
- \sr_reg[0]\(0) => bit_ctrl_n_15,
+ scl_pad_i => scl_pad_i,
+ sda_pad_i => sda_pad_i,
+ sda_padoen_o => sda_padoen_o,
+ \sr_reg[0]\(0) => bit_ctrl_n_17,
\sr_reg[6]\ => \wb_dat_o[6]_i_2_n_0\,
\sr_reg[7]\(0) => dout(7),
\st_irq_block.al_reg\ => \st_irq_block.al_reg\,
- \statemachine.ack_out_reg\ => bit_ctrl_n_13,
- \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_5,
- \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_6,
- \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_7,
- \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_8,
+ \statemachine.ack_out_reg\ => bit_ctrl_n_15,
+ \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_7,
+ \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_8,
+ \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_9,
+ \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_10,
\statemachine.core_cmd_reg[3]_0\(3 downto 0) => cmd(3 downto 0),
- \statemachine.core_txd_reg\ => bit_ctrl_n_10,
+ \statemachine.core_txd_reg\ => bit_ctrl_n_12,
\statemachine.core_txd_reg_0\ => \statemachine.core_txd_reg_n_0\,
- \statemachine.host_ack_reg\ => bit_ctrl_n_12,
- \statemachine.ld_reg\ => bit_ctrl_n_9,
+ \statemachine.host_ack_reg\ => bit_ctrl_n_14,
+ \statemachine.ld_reg\ => bit_ctrl_n_11,
\statemachine.ld_reg_0\ => \statemachine.ld_reg_n_0\,
- \statemachine.shift_reg\ => bit_ctrl_n_11,
+ \statemachine.shift_reg\ => bit_ctrl_n_13,
\txr_reg[6]\(1) => \txr_reg[7]\(6),
\txr_reg[6]\(0) => \txr_reg[7]\(0),
wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
@@ -3416,7 +3378,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => dcnt,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_15,
+ D => bit_ctrl_n_17,
Q => \sr_reg_n_0_[0]\
);
\sr_reg[1]\: unisim.vcomponents.FDCE
@@ -3489,7 +3451,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_13,
+ D => bit_ctrl_n_15,
Q => ack_out
);
\statemachine.core_cmd[1]_i_2\: unisim.vcomponents.LUT5
@@ -3535,7 +3497,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_8,
+ D => bit_ctrl_n_10,
Q => cmd(0)
);
\statemachine.core_cmd_reg[1]\: unisim.vcomponents.FDCE
@@ -3543,7 +3505,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_7,
+ D => bit_ctrl_n_9,
Q => cmd(1)
);
\statemachine.core_cmd_reg[2]\: unisim.vcomponents.FDCE
@@ -3551,7 +3513,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_6,
+ D => bit_ctrl_n_8,
Q => cmd(2)
);
\statemachine.core_cmd_reg[3]\: unisim.vcomponents.FDCE
@@ -3559,7 +3521,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_5,
+ D => bit_ctrl_n_7,
Q => cmd(3)
);
\statemachine.core_txd_reg\: unisim.vcomponents.FDCE
@@ -3567,7 +3529,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_10,
+ D => bit_ctrl_n_12,
Q => \statemachine.core_txd_reg_n_0\
);
\statemachine.host_ack_reg\: unisim.vcomponents.FDCE
@@ -3575,7 +3537,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_12,
+ D => bit_ctrl_n_14,
Q => cmd_ack
);
\statemachine.ld_reg\: unisim.vcomponents.FDCE
@@ -3583,7 +3545,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_9,
+ D => bit_ctrl_n_11,
Q => \statemachine.ld_reg_n_0\
);
\statemachine.shift_reg\: unisim.vcomponents.FDCE
@@ -3591,7 +3553,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_11,
+ D => bit_ctrl_n_13,
Q => \statemachine.shift_reg_n_0\
);
\wb_dat_o[0]_i_2\: unisim.vcomponents.LUT6
@@ -3774,16 +3736,18 @@ entity system_design_axi_wb_i2c_master_0_1_i2c_master_top is
port (
wb_ack_i : out STD_LOGIC;
wb_rst_o : out STD_LOGIC;
+ scl_padoen_o : out STD_LOGIC;
axi_int_o : out STD_LOGIC;
+ sda_padoen_o : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_stb_r_reg : out STD_LOGIC;
\s_rdata_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_rdata_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
s_stb_r_reg_0 : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
+ sda_pad_i : in STD_LOGIC;
+ scl_pad_i : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
@@ -3805,7 +3769,7 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_top is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ack_in : STD_LOGIC;
signal al : STD_LOGIC;
- signal byte_ctrl_n_12 : STD_LOGIC;
+ signal byte_ctrl_n_14 : STD_LOGIC;
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
@@ -3853,26 +3817,26 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_top is
signal \^wb_rst_o\ : STD_LOGIC;
signal write : STD_LOGIC;
attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair25";
begin
Q(0) <= \^q\(0);
wb_ack_i <= \^wb_ack_i\;
@@ -3880,7 +3844,7 @@ begin
byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
port map (
D(7 downto 0) => wb_dat_o(7 downto 0),
- E(0) => byte_ctrl_n_12,
+ E(0) => byte_ctrl_n_14,
Q(15 downto 2) => data0(13 downto 0),
Q(1) => \prer_reg_n_0_[1]\,
Q(0) => \prer_reg_n_0_[0]\,
@@ -3904,8 +3868,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
\ctr_reg[7]\(2) => \ctr_reg_n_0_[2]\,
\ctr_reg[7]\(1) => \ctr_reg_n_0_[1]\,
\ctr_reg[7]\(0) => \ctr_reg_n_0_[0]\,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
+ dscl_oen_reg => scl_padoen_o,
iack_o_reg => \^wb_ack_i\,
iack_o_reg_0 => iack_o_reg_0,
irq_flag => irq_flag,
@@ -3914,6 +3877,9 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
rxack_0 => rxack_0,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
+ scl_pad_i => scl_pad_i,
+ sda_pad_i => sda_pad_i,
+ sda_padoen_o => sda_padoen_o,
\st_irq_block.al_reg\ => \st_irq_block.al_reg_n_0\,
\txr_reg[7]\(7 downto 0) => txr(7 downto 0),
wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
@@ -4004,7 +3970,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
\cr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(0),
Q => write
@@ -4012,7 +3978,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
\cr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(1),
Q => read
@@ -4020,7 +3986,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
\cr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(2),
Q => stop
@@ -4028,7 +3994,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
\cr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(3),
Q => start
@@ -4686,17 +4652,24 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
signal cmp_axis_wbm_bridge_n_19 : STD_LOGIC;
signal cmp_axis_wbm_bridge_n_21 : STD_LOGIC;
signal cmp_axis_wbm_bridge_n_7 : STD_LOGIC;
- signal cmp_i2c_master_top_n_4 : STD_LOGIC;
- signal cmp_i2c_master_top_n_5 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_6 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_7 : STD_LOGIC;
signal ena : STD_LOGIC;
signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s00_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal scl_pad_i : STD_LOGIC;
+ signal scl_padoen_o : STD_LOGIC;
+ signal sda_pad_i : STD_LOGIC;
+ signal sda_padoen_o : STD_LOGIC;
signal wb_ack_i : STD_LOGIC;
signal wb_adr_o : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wb_cyc_o : STD_LOGIC;
signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wb_rst_o : STD_LOGIC;
signal wb_we_o : STD_LOGIC;
+ attribute box_type : string;
+ attribute box_type of iobuf_i2c_scl : label is "PRIMITIVE";
+ attribute box_type of iobuf_i2c_sda : label is "PRIMITIVE";
begin
s00_axi_bresp(1) <= \^s00_axi_bresp\(1);
s00_axi_bresp(0) <= \<const0>\;
@@ -4743,8 +4716,8 @@ cmp_axis_wbm_bridge: entity work.system_design_axi_wb_i2c_master_0_1_axis_wbm_br
\cr_reg[4]\ => cmp_axis_wbm_bridge_n_16,
\ctr_reg[0]\(0) => cmp_axis_wbm_bridge_n_19,
iack_o_reg => cmp_axis_wbm_bridge_n_21,
- iack_o_reg_0 => cmp_i2c_master_top_n_4,
- iack_o_reg_1(0) => cmp_i2c_master_top_n_5,
+ iack_o_reg_0 => cmp_i2c_master_top_n_6,
+ iack_o_reg_1(0) => cmp_i2c_master_top_n_7,
\prer_reg[8]\(1) => cmp_axis_wbm_bridge_n_17,
\prer_reg[8]\(0) => cmp_axis_wbm_bridge_n_18,
s00_axi_aclk => s00_axi_aclk,
@@ -4781,8 +4754,6 @@ cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_t
E(0) => cmp_axis_wbm_bridge_n_18,
Q(0) => ena,
axi_int_o => axi_int_o,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
iack_o_reg_0 => cmp_axis_wbm_bridge_n_16,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
@@ -4790,18 +4761,42 @@ cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_t
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_wdata(7 downto 0) => s00_axi_wdata(7 downto 0),
\s_addr_reg[4]\ => cmp_axis_wbm_bridge_n_7,
- \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_5,
+ \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_7,
\s_rdata_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
- s_stb_r_reg => cmp_i2c_master_top_n_4,
+ s_stb_r_reg => cmp_i2c_master_top_n_6,
s_stb_r_reg_0 => cmp_axis_wbm_bridge_n_21,
s_we_r_reg(0) => cmp_axis_wbm_bridge_n_19,
s_we_r_reg_0(0) => cmp_axis_wbm_bridge_n_11,
+ scl_pad_i => scl_pad_i,
+ scl_padoen_o => scl_padoen_o,
+ sda_pad_i => sda_pad_i,
+ sda_padoen_o => sda_padoen_o,
wb_ack_i => wb_ack_i,
wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
wb_cyc_o => wb_cyc_o,
wb_rst_o => wb_rst_o,
wb_we_o => wb_we_o
);
+iobuf_i2c_scl: unisim.vcomponents.IOBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => '0',
+ IO => i2c_scl_io,
+ O => scl_pad_i,
+ T => scl_padoen_o
+ );
+iobuf_i2c_sda: unisim.vcomponents.IOBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => '0',
+ IO => i2c_sda_io,
+ O => sda_pad_i,
+ T => sda_padoen_o
+ );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.v
index 34703cbcc4bee9df78eb2c1ebdd74df7b1d78d0e..7666083cb4bbe14d5ec7832346bf11690f627b41 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Tue Jun 20 20:06:18 2017
+// Date : Wed Oct 11 12:12:03 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.vhdl
index 1ed1fa559a1ff786fd4b8d0d012fbb4a7b5a251d..4f6655a49b2d9be0b5ee49b7229f39968fc23624 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Tue Jun 20 20:06:19 2017
+-- Date : Wed Oct 11 12:12:03 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd
index 3a78ac8b44fc12371e56cb3d614e9f2470ce763f..3fd151b77b6c7a30a7263e0fe7e59e97cb1aa41c 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.1
--- IP Revision: 5
+-- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.2
+-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/synth/system_design_axi_wb_i2c_master_2_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/synth/system_design_axi_wb_i2c_master_2_0.vhd
index 900ba355d9eb6bb7732abf0aabcb2caf5cd54409..e9fe9108d3af1e190afbbff523f6aa8e9bfbe28e 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/synth/system_design_axi_wb_i2c_master_2_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/synth/system_design_axi_wb_i2c_master_2_0.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.1
--- IP Revision: 5
+-- IP VLNV: cern.ch:ip:axi_wb_i2c_master:3.1.2
+-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.dcp
index 1838f915591221cde1964b913cc758db01b62eb2..c2f89c31aac1fb2569a73d20f3b0e13efb23fcf2 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci
index 7d7d82cd246240b1f60281fed5b154ed752accbc..aadbddf466caf30e5f913473c4f46cc857120926 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci
@@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_axi_wb_i2c_master_2_0</spirit:instanceName>
- <spirit:componentRef spirit:vendor="cern.ch" spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:version="3.1.1"/>
+ <spirit:componentRef spirit:vendor="cern.ch" spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:version="3.1.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
@@ -55,7 +55,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
index 40faba3cf061eab0764eb2cf757c787aea18fa73..a33066586228a05f278bab15c55df1e663ad165d 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
@@ -344,7 +344,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -356,7 +356,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>342d0b43</spirit:value>
+ <spirit:value>a1a0d50a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -375,7 +375,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -387,7 +387,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>342d0b43</spirit:value>
+ <spirit:value>a1a0d50a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -405,7 +405,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -417,7 +417,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>66f9670f</spirit:value>
+ <spirit:value>ce412196</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -436,7 +436,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:22 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -448,7 +448,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>66f9670f</spirit:value>
+ <spirit:value>ce412196</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -466,7 +466,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Jun 20 18:06:00 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:12:03 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -478,7 +478,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRC</spirit:name>
- <spirit:value>342d0b43</spirit:value>
+ <spirit:value>a1a0d50a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customizationCRCversion</spirit:name>
@@ -897,68 +897,68 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
@@ -974,72 +974,72 @@
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
<spirit:file>
- <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+ <spirit:name>../../ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>hdl_lib</spirit:logicalName>
</spirit:file>
@@ -1109,7 +1109,7 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>axi_wb_i2c_master</xilinx:displayName>
- <xilinx:coreRevision>5</xilinx:coreRevision>
+ <xilinx:coreRevision>6</xilinx:coreRevision>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:axi_wb_i2c_master:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
<xilinx:tag xilinx:name="cern.ch:user:axi_wb_i2c_master:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
@@ -1117,6 +1117,7 @@
<xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
<xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
<xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.1.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
+ <xilinx:tag xilinx:name="cern.ch:ip:axi_wb_i2c_master:3.1.2_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/axi_wb_i2c_master</xilinx:tag>
</xilinx:tags>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="user"/>
@@ -1151,7 +1152,7 @@
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2951d2ef"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e9d260ec"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af3e2a36"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="1a573fc4"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="15a214e0"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="675c1650"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
index cc50b9b15665f9a734a8c241e70e78823bf5bc9d..ad07f845cbdf90407ca53fa38305237b0da6c1eb 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Tue Jun 20 20:06:00 2017
+// Date : Wed Oct 11 12:12:02 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
@@ -65,8 +65,8 @@ module system_design_axi_wb_i2c_master_2_0
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *) input s00_axi_rready;
wire axi_int_o;
- wire i2c_scl_io;
- wire i2c_sda_io;
+ (* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "FAST" *) wire i2c_scl_io;
+ (* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "FAST" *) wire i2c_sda_io;
wire s00_axi_aclk;
wire [31:0]s00_axi_araddr;
wire s00_axi_aresetn;
@@ -82,7 +82,7 @@ module system_design_axi_wb_i2c_master_2_0
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
- wire [1:0]s00_axi_rresp;
+ (* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "FAST" *) wire [1:0]s00_axi_rresp;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire s00_axi_wready;
@@ -182,8 +182,8 @@ module system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
wire cmp_axis_wbm_bridge_n_19;
wire cmp_axis_wbm_bridge_n_21;
wire cmp_axis_wbm_bridge_n_7;
- wire cmp_i2c_master_top_n_4;
- wire cmp_i2c_master_top_n_5;
+ wire cmp_i2c_master_top_n_6;
+ wire cmp_i2c_master_top_n_7;
wire ena;
wire i2c_scl_io;
wire i2c_sda_io;
@@ -204,6 +204,10 @@ module system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
wire [31:0]s00_axi_wdata;
wire s00_axi_wready;
wire s00_axi_wvalid;
+ wire scl_pad_i;
+ wire scl_padoen_o;
+ wire sda_pad_i;
+ wire sda_padoen_o;
wire wb_ack_i;
wire [2:0]wb_adr_o;
wire wb_cyc_o;
@@ -250,8 +254,8 @@ module system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
.\cr_reg[4] (cmp_axis_wbm_bridge_n_16),
.\ctr_reg[0] (cmp_axis_wbm_bridge_n_19),
.iack_o_reg(cmp_axis_wbm_bridge_n_21),
- .iack_o_reg_0(cmp_i2c_master_top_n_4),
- .iack_o_reg_1(cmp_i2c_master_top_n_5),
+ .iack_o_reg_0(cmp_i2c_master_top_n_6),
+ .iack_o_reg_1(cmp_i2c_master_top_n_7),
.\prer_reg[8] ({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_araddr(s00_axi_araddr[4:2]),
@@ -281,8 +285,6 @@ module system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
.E({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
.Q(ena),
.axi_int_o(axi_int_o),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
.iack_o_reg_0(cmp_axis_wbm_bridge_n_16),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
@@ -290,17 +292,37 @@ module system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_wdata(s00_axi_wdata[7:0]),
.\s_addr_reg[4] (cmp_axis_wbm_bridge_n_7),
- .\s_rdata_reg[0] (cmp_i2c_master_top_n_5),
+ .\s_rdata_reg[0] (cmp_i2c_master_top_n_7),
.\s_rdata_reg[7] (wb_dat_o),
- .s_stb_r_reg(cmp_i2c_master_top_n_4),
+ .s_stb_r_reg(cmp_i2c_master_top_n_6),
.s_stb_r_reg_0(cmp_axis_wbm_bridge_n_21),
.s_we_r_reg(cmp_axis_wbm_bridge_n_19),
.s_we_r_reg_0(cmp_axis_wbm_bridge_n_11),
+ .scl_pad_i(scl_pad_i),
+ .scl_padoen_o(scl_padoen_o),
+ .sda_pad_i(sda_pad_i),
+ .sda_padoen_o(sda_padoen_o),
.wb_ack_i(wb_ack_i),
.wb_adr_o(wb_adr_o),
.wb_cyc_o(wb_cyc_o),
.wb_rst_o(wb_rst_o),
.wb_we_o(wb_we_o));
+ (* box_type = "PRIMITIVE" *)
+ IOBUF #(
+ .IOSTANDARD("DEFAULT"))
+ iobuf_i2c_scl
+ (.I(1'b0),
+ .IO(i2c_scl_io),
+ .O(scl_pad_i),
+ .T(scl_padoen_o));
+ (* box_type = "PRIMITIVE" *)
+ IOBUF #(
+ .IOSTANDARD("DEFAULT"))
+ iobuf_i2c_sda
+ (.I(1'b0),
+ .IO(i2c_sda_io),
+ .O(sda_pad_i),
+ .T(sda_padoen_o));
endmodule
(* ORIG_REF_NAME = "axis_wbm_bridge" *)
@@ -771,6 +793,8 @@ endmodule
(* ORIG_REF_NAME = "i2c_master_bit_ctrl" *)
module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
(iscl_oen_reg_0,
+ dscl_oen_reg_0,
+ sda_padoen_o,
E,
irq_flag1_out,
al,
@@ -784,8 +808,6 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
\cr_reg[4] ,
\sr_reg[0] ,
\FSM_sequential_statemachine.c_state_reg[2] ,
- i2c_sda_io,
- i2c_scl_io,
s00_axi_aclk,
s00_axi_aresetn,
out,
@@ -794,6 +816,8 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
irq_flag,
Q,
\ctr_reg[7] ,
+ sda_pad_i,
+ scl_pad_i,
\statemachine.core_cmd_reg[3]_0 ,
\st_irq_block.al_reg ,
\cr_reg[7] ,
@@ -816,6 +840,8 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
\cr_reg[7]_0 ,
\statemachine.core_txd_reg_0 );
output iscl_oen_reg_0;
+ output dscl_oen_reg_0;
+ output sda_padoen_o;
output [0:0]E;
output irq_flag1_out;
output al;
@@ -829,8 +855,6 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
output [0:0]\cr_reg[4] ;
output [0:0]\sr_reg[0] ;
output [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
input s00_axi_aclk;
input s00_axi_aresetn;
input [2:0]out;
@@ -839,6 +863,8 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
input irq_flag;
input [15:0]Q;
input [0:0]\ctr_reg[7] ;
+ input sda_pad_i;
+ input scl_pad_i;
input [3:0]\statemachine.core_cmd_reg[3]_0 ;
input \st_irq_block.al_reg ;
input [3:0]\cr_reg[7] ;
@@ -1019,13 +1045,10 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
wire dSCL;
wire dSDA;
wire dscl_oen;
+ wire dscl_oen_reg_0;
wire [13:0]filter_cnt;
wire i2c_al;
wire i2c_busy;
- wire i2c_scl_io;
- wire i2c_scl_io_INST_0_i_1_n_0;
- wire i2c_sda_io;
- wire i2c_sda_io_INST_0_i_1_n_0;
wire iack_o_reg;
wire iack_o_reg_0;
wire ial;
@@ -1085,9 +1108,10 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
wire s00_axi_aresetn;
wire sSCL;
wire sSDA;
- wire scl_padoen_o;
+ wire scl_pad_i;
wire sda_chk_i_1_n_0;
wire sda_chk_reg_n_0;
+ wire sda_pad_i;
wire sda_padoen_o;
wire slave_wait;
wire slave_wait0;
@@ -1319,13 +1343,14 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.I4(\cr_reg[7] [1]),
.I5(\cr_reg[7] [2]),
.O(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSCL[0]_i_1
(.I0(s00_axi_aresetn),
- .I1(i2c_scl_io),
+ .I1(scl_pad_i),
.O(\bus_status_ctrl.cSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSCL[1]_i_1
@@ -1344,13 +1369,14 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(\bus_status_ctrl.cSCL[1]_i_1_n_0 ),
.Q(p_0_in__1[0]));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSDA[0]_i_1
(.I0(s00_axi_aresetn),
- .I1(i2c_sda_io),
+ .I1(sda_pad_i),
.O(\bus_status_ctrl.cSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h8))
\bus_status_ctrl.cSDA[1]_i_1
@@ -1404,7 +1430,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.D(\bus_status_ctrl.dSCL_i_1_n_0 ),
.PRE(iscl_oen_reg_0),
.Q(dSCL));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.dSDA_i_1
@@ -1431,21 +1457,21 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(\bus_status_ctrl.dout_i_1_n_0 ),
.Q(core_rxd));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSCL[0]_i_1
(.I0(p_0_in__1[0]),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSCL[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSCL[1]_i_1
(.I0(p_0_in__1[1]),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSCL[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSCL[2]_i_1
@@ -1470,14 +1496,14 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.D(\bus_status_ctrl.fSCL[2]_i_1_n_0 ),
.PRE(iscl_oen_reg_0),
.Q(\bus_status_ctrl.fSCL_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSDA[0]_i_1
(.I0(\bus_status_ctrl.cSDA_reg_n_0_[1] ),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSDA[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSDA[1]_i_1
@@ -1490,7 +1516,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
(.I0(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
.I1(s00_axi_aresetn),
.O(\bus_status_ctrl.fSDA[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\bus_status_ctrl.fSDA[2]_i_2
@@ -1784,7 +1810,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(ial),
.Q(i2c_al));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h5400))
\bus_status_ctrl.ibusy_i_1
@@ -1799,7 +1825,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(ibusy),
.Q(i2c_busy));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hE8FF))
\bus_status_ctrl.sSCL_i_1
@@ -1828,7 +1854,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.D(\bus_status_ctrl.sSDA_i_1_n_0 ),
.PRE(iscl_oen_reg_0),
.Q(sSDA));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h2000))
\bus_status_ctrl.sta_condition_i_1
@@ -1843,7 +1869,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(sta_condition),
.Q(\bus_status_ctrl.sta_condition_reg_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h4000))
\bus_status_ctrl.sto_condition_i_1
@@ -1873,7 +1899,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
clk_en_i_2
(.I0(\ctr_reg[7] ),
.I1(sSCL),
- .I2(scl_padoen_o),
+ .I2(dscl_oen_reg_0),
.I3(dSCL),
.I4(s00_axi_aresetn),
.O(clk_en_i_2_n_0));
@@ -2299,41 +2325,8 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg_0),
- .D(scl_padoen_o),
+ .D(dscl_oen_reg_0),
.Q(dscl_oen));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_scl_io_INST_0
- (.I0(1'b0),
- .I1(i2c_scl_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_scl_io));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_scl_io_INST_0_i_1
- (.I0(scl_padoen_o),
- .O(i2c_scl_io_INST_0_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- i2c_sda_io_INST_0
- (.I0(1'b0),
- .I1(i2c_sda_io_INST_0_i_1_n_0),
- .I2(1'b0),
- .I3(1'b0),
- .I4(1'b0),
- .I5(1'b0),
- .O(i2c_sda_io));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT1 #(
- .INIT(2'h1))
- i2c_sda_io_INST_0_i_1
- (.I0(sda_padoen_o),
- .O(i2c_sda_io_INST_0_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFBFFFBF3))
iscl_oen_i_1
@@ -2341,7 +2334,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.I1(s00_axi_aresetn),
.I2(i2c_al),
.I3(iscl_oen9_out__0),
- .I4(scl_padoen_o),
+ .I4(dscl_oen_reg_0),
.O(iscl_oen_i_1_n_0));
LUT5 #(
.INIT(32'h00F3011F))
@@ -2366,8 +2359,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.CE(1'b1),
.D(iscl_oen_i_1_n_0),
.PRE(iscl_oen_reg_0),
- .Q(scl_padoen_o));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
+ .Q(dscl_oen_reg_0));
LUT5 #(
.INIT(32'hFBFFFBF3))
isda_oen_i_1
@@ -2516,7 +2508,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.INIT(16'h0F04))
slave_wait_i_1
(.I0(dscl_oen),
- .I1(scl_padoen_o),
+ .I1(dscl_oen_reg_0),
.I2(sSCL),
.I3(slave_wait),
.O(slave_wait0));
@@ -2526,7 +2518,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.CLR(iscl_oen_reg_0),
.D(slave_wait0),
.Q(slave_wait));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hE400))
\sr[0]_i_1
@@ -2535,7 +2527,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.I2(\txr_reg[6] [0]),
.I3(s00_axi_aresetn),
.O(\sr_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hAA08))
\st_irq_block.al_i_1
@@ -2598,7 +2590,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.I4(out[0]),
.I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
.O(\statemachine.core_cmd_reg[3] [1]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h08))
\statemachine.core_cmd[2]_i_1
@@ -2606,7 +2598,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.I1(s00_axi_aresetn),
.I2(i2c_al),
.O(\statemachine.core_cmd_reg[3] [2]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0040))
\statemachine.core_cmd[3]_i_1
@@ -2615,7 +2607,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
.I2(s00_axi_aresetn),
.I3(i2c_al),
.O(\statemachine.core_cmd_reg[3] [3]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h08))
\statemachine.core_txd_i_1
@@ -2681,19 +2673,21 @@ endmodule
(* ORIG_REF_NAME = "i2c_master_byte_ctrl" *)
module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
(iscl_oen_reg,
+ dscl_oen_reg,
+ sda_padoen_o,
irq_flag1_out,
rxack_0,
al,
D,
E,
- i2c_sda_io,
- i2c_scl_io,
s00_axi_aclk,
s00_axi_aresetn,
\cr_reg[0] ,
irq_flag,
Q,
\ctr_reg[7] ,
+ sda_pad_i,
+ scl_pad_i,
\st_irq_block.al_reg ,
\cr_reg[7] ,
wb_adr_o,
@@ -2708,19 +2702,21 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
wb_we_o,
iack_o_reg_0);
output iscl_oen_reg;
+ output dscl_oen_reg;
+ output sda_padoen_o;
output irq_flag1_out;
output rxack_0;
output al;
output [7:0]D;
output [0:0]E;
- inout i2c_sda_io;
- inout i2c_scl_io;
input s00_axi_aclk;
input s00_axi_aresetn;
input \cr_reg[0] ;
input irq_flag;
input [15:0]Q;
input [7:0]\ctr_reg[7] ;
+ input sda_pad_i;
+ input scl_pad_i;
input \st_irq_block.al_reg ;
input [3:0]\cr_reg[7] ;
input [2:0]wb_adr_o;
@@ -2748,12 +2744,12 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
wire bit_ctrl_n_11;
wire bit_ctrl_n_12;
wire bit_ctrl_n_13;
+ wire bit_ctrl_n_14;
wire bit_ctrl_n_15;
- wire bit_ctrl_n_16;
wire bit_ctrl_n_17;
wire bit_ctrl_n_18;
- wire bit_ctrl_n_5;
- wire bit_ctrl_n_6;
+ wire bit_ctrl_n_19;
+ wire bit_ctrl_n_20;
wire bit_ctrl_n_7;
wire bit_ctrl_n_8;
wire bit_ctrl_n_9;
@@ -2779,8 +2775,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
wire \dcnt_reg_n_0_[1] ;
wire \dcnt_reg_n_0_[2] ;
wire [7:7]dout;
- wire i2c_scl_io;
- wire i2c_sda_io;
+ wire dscl_oen_reg;
wire iack_o_reg;
wire iack_o_reg_0;
wire irq_flag;
@@ -2789,6 +2784,9 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
wire rxack_0;
wire s00_axi_aclk;
wire s00_axi_aresetn;
+ wire scl_pad_i;
+ wire sda_pad_i;
+ wire sda_padoen_o;
wire \sr[1]_i_1_n_0 ;
wire \sr[2]_i_1_n_0 ;
wire \sr[3]_i_1_n_0 ;
@@ -2860,21 +2858,21 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_18),
+ .D(bit_ctrl_n_20),
.Q(c_state__0[0]));
(* KEEP = "yes" *)
FDCE \FSM_sequential_statemachine.c_state_reg[1]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_17),
+ .D(bit_ctrl_n_19),
.Q(c_state__0[1]));
(* KEEP = "yes" *)
FDCE \FSM_sequential_statemachine.c_state_reg[2]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_16),
+ .D(bit_ctrl_n_18),
.Q(c_state__0[2]));
system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl bit_ctrl
(.D(D[6]),
@@ -2883,7 +2881,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.\FSM_sequential_statemachine.c_state_reg[1]_0 (\statemachine.core_cmd[1]_i_2_n_0 ),
.\FSM_sequential_statemachine.c_state_reg[1]_1 (\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ),
.\FSM_sequential_statemachine.c_state_reg[1]_2 (\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ),
- .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_16,bit_ctrl_n_17,bit_ctrl_n_18}),
+ .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_18,bit_ctrl_n_19,bit_ctrl_n_20}),
.Q(Q),
.ack_in(ack_in),
.ack_out(ack_out),
@@ -2896,8 +2894,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.\cr_reg[7] (\cr_reg[7] ),
.\cr_reg[7]_0 (\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ),
.\ctr_reg[7] (\ctr_reg[7] [7]),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
+ .dscl_oen_reg_0(dscl_oen_reg),
.iack_o_reg(iack_o_reg),
.iack_o_reg_0(iack_o_reg_0),
.irq_flag(irq_flag),
@@ -2906,23 +2903,26 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.out(c_state__0),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
- .\sr_reg[0] (bit_ctrl_n_15),
+ .scl_pad_i(scl_pad_i),
+ .sda_pad_i(sda_pad_i),
+ .sda_padoen_o(sda_padoen_o),
+ .\sr_reg[0] (bit_ctrl_n_17),
.\sr_reg[6] (\wb_dat_o[6]_i_2_n_0 ),
.\sr_reg[7] (dout),
.\st_irq_block.al_reg (\st_irq_block.al_reg ),
- .\statemachine.ack_out_reg (bit_ctrl_n_13),
- .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_5,bit_ctrl_n_6,bit_ctrl_n_7,bit_ctrl_n_8}),
+ .\statemachine.ack_out_reg (bit_ctrl_n_15),
+ .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_7,bit_ctrl_n_8,bit_ctrl_n_9,bit_ctrl_n_10}),
.\statemachine.core_cmd_reg[3]_0 (cmd),
- .\statemachine.core_txd_reg (bit_ctrl_n_10),
+ .\statemachine.core_txd_reg (bit_ctrl_n_12),
.\statemachine.core_txd_reg_0 (\statemachine.core_txd_reg_n_0 ),
- .\statemachine.host_ack_reg (bit_ctrl_n_12),
- .\statemachine.ld_reg (bit_ctrl_n_9),
+ .\statemachine.host_ack_reg (bit_ctrl_n_14),
+ .\statemachine.ld_reg (bit_ctrl_n_11),
.\statemachine.ld_reg_0 (\statemachine.ld_reg_n_0 ),
- .\statemachine.shift_reg (bit_ctrl_n_11),
+ .\statemachine.shift_reg (bit_ctrl_n_13),
.\txr_reg[6] ({\txr_reg[7] [6],\txr_reg[7] [0]}),
.wb_adr_o(wb_adr_o),
.wb_we_o(wb_we_o));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h8A))
\dcnt[0]_i_1
@@ -2930,7 +2930,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.I1(\statemachine.ld_reg_n_0 ),
.I2(\dcnt_reg_n_0_[0] ),
.O(\dcnt[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hA88A))
\dcnt[1]_i_1
@@ -2939,7 +2939,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.I2(\dcnt_reg_n_0_[0] ),
.I3(\dcnt_reg_n_0_[1] ),
.O(\dcnt[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hAAA8888A))
\dcnt[2]_i_1
@@ -2967,7 +2967,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.CLR(iscl_oen_reg),
.D(\dcnt[2]_i_1_n_0 ),
.Q(\dcnt_reg_n_0_[2] ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hE400))
\sr[1]_i_1
@@ -2976,7 +2976,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.I2(\txr_reg[7] [1]),
.I3(s00_axi_aresetn),
.O(\sr[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hE400))
\sr[2]_i_1
@@ -3036,7 +3036,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(dcnt),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_15),
+ .D(bit_ctrl_n_17),
.Q(\sr_reg_n_0_[0] ));
FDCE \sr_reg[1]
(.C(s00_axi_aclk),
@@ -3080,7 +3080,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
.CLR(iscl_oen_reg),
.D(\sr[7]_i_2_n_0 ),
.Q(dout));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\st_irq_block.rxack_i_1
@@ -3091,7 +3091,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_13),
+ .D(bit_ctrl_n_15),
.Q(ack_out));
LUT5 #(
.INIT(32'h00000001))
@@ -3126,49 +3126,49 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_8),
+ .D(bit_ctrl_n_10),
.Q(cmd[0]));
FDCE \statemachine.core_cmd_reg[1]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_7),
+ .D(bit_ctrl_n_9),
.Q(cmd[1]));
FDCE \statemachine.core_cmd_reg[2]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_6),
+ .D(bit_ctrl_n_8),
.Q(cmd[2]));
FDCE \statemachine.core_cmd_reg[3]
(.C(s00_axi_aclk),
.CE(c_state),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_5),
+ .D(bit_ctrl_n_7),
.Q(cmd[3]));
FDCE \statemachine.core_txd_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_10),
+ .D(bit_ctrl_n_12),
.Q(\statemachine.core_txd_reg_n_0 ));
FDCE \statemachine.host_ack_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_12),
+ .D(bit_ctrl_n_14),
.Q(cmd_ack));
FDCE \statemachine.ld_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_9),
+ .D(bit_ctrl_n_11),
.Q(\statemachine.ld_reg_n_0 ));
FDCE \statemachine.shift_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.CLR(iscl_oen_reg),
- .D(bit_ctrl_n_11),
+ .D(bit_ctrl_n_13),
.Q(\statemachine.shift_reg_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
@@ -3306,16 +3306,18 @@ endmodule
module system_design_axi_wb_i2c_master_2_0_i2c_master_top
(wb_ack_i,
wb_rst_o,
+ scl_padoen_o,
axi_int_o,
+ sda_padoen_o,
Q,
s_stb_r_reg,
\s_rdata_reg[0] ,
\s_rdata_reg[7] ,
- i2c_sda_io,
- i2c_scl_io,
s_stb_r_reg_0,
s00_axi_aclk,
s00_axi_aresetn,
+ sda_pad_i,
+ scl_pad_i,
s00_axi_wdata,
wb_adr_o,
s00_axi_awvalid,
@@ -3330,16 +3332,18 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
\s_addr_reg[4] );
output wb_ack_i;
output wb_rst_o;
+ output scl_padoen_o;
output axi_int_o;
+ output sda_padoen_o;
output [0:0]Q;
output s_stb_r_reg;
output [0:0]\s_rdata_reg[0] ;
output [7:0]\s_rdata_reg[7] ;
- inout i2c_sda_io;
- inout i2c_scl_io;
input s_stb_r_reg_0;
input s00_axi_aclk;
input s00_axi_aresetn;
+ input sda_pad_i;
+ input scl_pad_i;
input [7:0]s00_axi_wdata;
input [2:0]wb_adr_o;
input s00_axi_awvalid;
@@ -3359,7 +3363,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
wire ack_in;
wire al;
wire axi_int_o;
- wire byte_ctrl_n_12;
+ wire byte_ctrl_n_14;
wire \cr[0]_i_1_n_0 ;
wire \cr[1]_i_1_n_0 ;
wire \cr[2]_i_1_n_0 ;
@@ -3375,8 +3379,6 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
wire \ctr_reg_n_0_[4] ;
wire \ctr_reg_n_0_[5] ;
wire [13:0]data0;
- wire i2c_scl_io;
- wire i2c_sda_io;
wire iack_o_reg_0;
wire ien;
wire irq_flag;
@@ -3406,6 +3408,10 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
wire s_stb_r_reg_0;
wire [0:0]s_we_r_reg;
wire [0:0]s_we_r_reg_0;
+ wire scl_pad_i;
+ wire scl_padoen_o;
+ wire sda_pad_i;
+ wire sda_padoen_o;
wire \st_irq_block.al_reg_n_0 ;
wire \st_irq_block.wb_inta_o_i_1_n_0 ;
wire start;
@@ -3427,7 +3433,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl byte_ctrl
(.D(wb_dat_o),
- .E(byte_ctrl_n_12),
+ .E(byte_ctrl_n_14),
.Q({data0,\prer_reg_n_0_[1] ,\prer_reg_n_0_[0] }),
.ack_in(ack_in),
.al(al),
@@ -3439,8 +3445,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.\cr_reg[7] ({start,stop,read,write}),
.\cr_reg[7]_0 (\wb_dat_o[7]_i_3_n_0 ),
.\ctr_reg[7] ({Q,ien,\ctr_reg_n_0_[5] ,\ctr_reg_n_0_[4] ,\ctr_reg_n_0_[3] ,\ctr_reg_n_0_[2] ,\ctr_reg_n_0_[1] ,\ctr_reg_n_0_[0] }),
- .i2c_scl_io(i2c_scl_io),
- .i2c_sda_io(i2c_sda_io),
+ .dscl_oen_reg(scl_padoen_o),
.iack_o_reg(wb_ack_i),
.iack_o_reg_0(iack_o_reg_0),
.irq_flag(irq_flag),
@@ -3449,6 +3454,9 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.rxack_0(rxack_0),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
+ .scl_pad_i(scl_pad_i),
+ .sda_pad_i(sda_pad_i),
+ .sda_padoen_o(sda_padoen_o),
.\st_irq_block.al_reg (\st_irq_block.al_reg_n_0 ),
.\txr_reg[7] (txr),
.wb_adr_o(wb_adr_o),
@@ -3483,7 +3491,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.I4(\s_addr_reg[4] ),
.I5(\cr_reg_n_0_[2] ),
.O(\cr[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'hC808))
\cr[3]_i_1
@@ -3518,78 +3526,78 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.Q(ack_in));
FDCE \cr_reg[4]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[0]),
.Q(write));
FDCE \cr_reg[5]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[1]),
.Q(read));
FDCE \cr_reg[6]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[2]),
.Q(stop));
FDCE \cr_reg[7]
(.C(s00_axi_aclk),
- .CE(byte_ctrl_n_12),
+ .CE(byte_ctrl_n_14),
.CLR(wb_rst_o),
.D(D[3]),
.Q(start));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\ctr[0]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[0]),
.O(ctr[0]));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\ctr[1]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[1]),
.O(ctr[1]));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\ctr[2]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[2]),
.O(ctr[2]));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\ctr[3]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[3]),
.O(ctr[3]));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\ctr[4]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[4]),
.O(ctr[4]));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h8))
\ctr[5]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[5]),
.O(ctr[5]));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h8))
\ctr[6]_i_1
(.I0(s00_axi_aresetn),
.I1(s00_axi_wdata[6]),
.O(ctr[6]));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h8))
\ctr[7]_i_2
@@ -3650,7 +3658,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.D(s_stb_r_reg_0),
.Q(wb_ack_i),
.R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'hB))
\prer[10]_i_1
@@ -3663,42 +3671,42 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
(.I0(s00_axi_wdata[3]),
.I1(s00_axi_aresetn),
.O(\prer[11]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'hB))
\prer[12]_i_1
(.I0(s00_axi_wdata[4]),
.I1(s00_axi_aresetn),
.O(\prer[12]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'hB))
\prer[13]_i_1
(.I0(s00_axi_wdata[5]),
.I1(s00_axi_aresetn),
.O(\prer[13]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'hB))
\prer[14]_i_1
(.I0(s00_axi_wdata[6]),
.I1(s00_axi_aresetn),
.O(\prer[14]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'hB))
\prer[15]_i_2
(.I0(s00_axi_wdata[7]),
.I1(s00_axi_aresetn),
.O(\prer[15]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'hB))
\prer[8]_i_1
(.I0(s00_axi_wdata[0]),
.I1(s00_axi_aresetn),
.O(\prer[8]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'hB))
\prer[9]_i_1
@@ -3801,14 +3809,14 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.D(\prer[9]_i_1_n_0 ),
.PRE(wb_rst_o),
.Q(data0[7]));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h2))
\s_rdata[7]_i_1
(.I0(wb_ack_i),
.I1(wb_we_o),
.O(\s_rdata_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hEFEE))
s_stb_r_i_1
@@ -3835,7 +3843,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.CLR(wb_rst_o),
.D(rxack_0),
.Q(rxack));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hA8))
\st_irq_block.tip_i_1
@@ -3849,7 +3857,7 @@ module system_design_axi_wb_i2c_master_2_0_i2c_master_top
.CLR(wb_rst_o),
.D(tip_1),
.Q(tip));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h80))
\st_irq_block.wb_inta_o_i_1
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
index 9d359d30277af7191c6849a74542afefc918c126..74f0364dac84b18f08ea2fc6d5f13c0bef57c550 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Tue Jun 20 20:06:00 2017
+-- Date : Wed Oct 11 12:12:02 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
@@ -561,6 +561,8 @@ use UNISIM.VCOMPONENTS.ALL;
entity system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl is
port (
iscl_oen_reg_0 : out STD_LOGIC;
+ dscl_oen_reg_0 : out STD_LOGIC;
+ sda_padoen_o : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
irq_flag1_out : out STD_LOGIC;
al : out STD_LOGIC;
@@ -574,8 +576,6 @@ entity system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl is
\cr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\sr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_sequential_statemachine.c_state_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -584,6 +584,8 @@ entity system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl is
irq_flag : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sda_pad_i : in STD_LOGIC;
+ scl_pad_i : in STD_LOGIC;
\statemachine.core_cmd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\st_irq_block.al_reg\ : in STD_LOGIC;
\cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
@@ -752,11 +754,10 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctr
signal dSCL : STD_LOGIC;
signal dSDA : STD_LOGIC;
signal dscl_oen : STD_LOGIC;
+ signal \^dscl_oen_reg_0\ : STD_LOGIC;
signal filter_cnt : STD_LOGIC_VECTOR ( 13 downto 0 );
signal i2c_al : STD_LOGIC;
signal i2c_busy : STD_LOGIC;
- signal i2c_scl_io_INST_0_i_1_n_0 : STD_LOGIC;
- signal i2c_sda_io_INST_0_i_1_n_0 : STD_LOGIC;
signal ial : STD_LOGIC;
signal ibusy : STD_LOGIC;
signal iscl_oen : STD_LOGIC;
@@ -809,10 +810,9 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctr
signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sSCL : STD_LOGIC;
signal sSDA : STD_LOGIC;
- signal scl_padoen_o : STD_LOGIC;
signal sda_chk_i_1_n_0 : STD_LOGIC;
signal sda_chk_reg_n_0 : STD_LOGIC;
- signal sda_padoen_o : STD_LOGIC;
+ signal \^sda_padoen_o\ : STD_LOGIC;
signal slave_wait : STD_LOGIC;
signal slave_wait0 : STD_LOGIC;
signal sta_condition : STD_LOGIC;
@@ -830,33 +830,33 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctr
attribute KEEP of \FSM_sequential_c_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_sequential_c_state_reg[3]\ : label is "yes";
attribute KEEP of \FSM_sequential_c_state_reg[4]\ : label is "yes";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bus_status_ctrl.dSCL_i_1\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of clk_en_i_2 : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of i2c_scl_io_INST_0_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of i2c_sda_io_INST_0_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of iscl_oen_i_1 : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of isda_oen_i_1 : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \st_irq_block.irq_flag_i_1\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair14";
begin
+ dscl_oen_reg_0 <= \^dscl_oen_reg_0\;
iscl_oen_reg_0 <= \^iscl_oen_reg_0\;
+ sda_padoen_o <= \^sda_padoen_o\;
\FSM_sequential_c_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111110"
@@ -1125,7 +1125,7 @@ begin
)
port map (
I0 => s00_axi_aresetn,
- I1 => i2c_scl_io,
+ I1 => scl_pad_i,
O => \bus_status_ctrl.cSCL[0]_i_1_n_0\
);
\bus_status_ctrl.cSCL[1]_i_1\: unisim.vcomponents.LUT2
@@ -1159,7 +1159,7 @@ begin
)
port map (
I0 => s00_axi_aresetn,
- I1 => i2c_sda_io,
+ I1 => sda_pad_i,
O => \bus_status_ctrl.cSDA[0]_i_1_n_0\
);
\bus_status_ctrl.cSDA[1]_i_1\: unisim.vcomponents.LUT2
@@ -1706,7 +1706,7 @@ begin
I0 => s00_axi_aresetn,
I1 => sda_chk_reg_n_0,
I2 => sSDA,
- I3 => sda_padoen_o,
+ I3 => \^sda_padoen_o\,
I4 => \bus_status_ctrl.ial_i_2_n_0\,
I5 => \bus_status_ctrl.ial_i_3_n_0\,
O => ial
@@ -1854,7 +1854,7 @@ clk_en_i_2: unisim.vcomponents.LUT5
port map (
I0 => \ctr_reg[7]\(0),
I1 => sSCL,
- I2 => scl_padoen_o,
+ I2 => \^dscl_oen_reg_0\,
I3 => dSCL,
I4 => s00_axi_aresetn,
O => clk_en_i_2_n_0
@@ -2491,51 +2491,9 @@ dscl_oen_reg: unisim.vcomponents.FDCE
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg_0\,
- D => scl_padoen_o,
+ D => \^dscl_oen_reg_0\,
Q => dscl_oen
);
-i2c_scl_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_scl_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_scl_io
- );
-i2c_scl_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => scl_padoen_o,
- O => i2c_scl_io_INST_0_i_1_n_0
- );
-i2c_sda_io_INST_0: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFF888F888F888"
- )
- port map (
- I0 => '0',
- I1 => i2c_sda_io_INST_0_i_1_n_0,
- I2 => '0',
- I3 => '0',
- I4 => '0',
- I5 => '0',
- O => i2c_sda_io
- );
-i2c_sda_io_INST_0_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => sda_padoen_o,
- O => i2c_sda_io_INST_0_i_1_n_0
- );
iscl_oen_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFFBF3"
@@ -2545,7 +2503,7 @@ iscl_oen_i_1: unisim.vcomponents.LUT5
I1 => s00_axi_aresetn,
I2 => i2c_al,
I3 => \iscl_oen9_out__0\,
- I4 => scl_padoen_o,
+ I4 => \^dscl_oen_reg_0\,
O => iscl_oen_i_1_n_0
);
iscl_oen_i_2: unisim.vcomponents.LUT5
@@ -2578,7 +2536,7 @@ iscl_oen_reg: unisim.vcomponents.FDPE
CE => '1',
D => iscl_oen_i_1_n_0,
PRE => \^iscl_oen_reg_0\,
- Q => scl_padoen_o
+ Q => \^dscl_oen_reg_0\
);
isda_oen_i_1: unisim.vcomponents.LUT5
generic map(
@@ -2589,7 +2547,7 @@ isda_oen_i_1: unisim.vcomponents.LUT5
I1 => s00_axi_aresetn,
I2 => i2c_al,
I3 => \isda_oen7_out__0\,
- I4 => sda_padoen_o,
+ I4 => \^sda_padoen_o\,
O => isda_oen_i_1_n_0
);
isda_oen_i_2: unisim.vcomponents.LUT6
@@ -2624,7 +2582,7 @@ isda_oen_reg: unisim.vcomponents.FDPE
CE => '1',
D => isda_oen_i_1_n_0,
PRE => \^iscl_oen_reg_0\,
- Q => sda_padoen_o
+ Q => \^sda_padoen_o\
);
minusOp_carry: unisim.vcomponents.CARRY4
port map (
@@ -2822,7 +2780,7 @@ slave_wait_i_1: unisim.vcomponents.LUT4
)
port map (
I0 => dscl_oen,
- I1 => scl_padoen_o,
+ I1 => \^dscl_oen_reg_0\,
I2 => sSCL,
I3 => slave_wait,
O => slave_wait0
@@ -3037,19 +2995,21 @@ use UNISIM.VCOMPONENTS.ALL;
entity system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl is
port (
iscl_oen_reg : out STD_LOGIC;
+ dscl_oen_reg : out STD_LOGIC;
+ sda_padoen_o : out STD_LOGIC;
irq_flag1_out : out STD_LOGIC;
rxack_0 : out STD_LOGIC;
al : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
\cr_reg[0]\ : in STD_LOGIC;
irq_flag : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ sda_pad_i : in STD_LOGIC;
+ scl_pad_i : in STD_LOGIC;
\st_irq_block.al_reg\ : in STD_LOGIC;
\cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
@@ -3077,12 +3037,12 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ct
signal bit_ctrl_n_11 : STD_LOGIC;
signal bit_ctrl_n_12 : STD_LOGIC;
signal bit_ctrl_n_13 : STD_LOGIC;
+ signal bit_ctrl_n_14 : STD_LOGIC;
signal bit_ctrl_n_15 : STD_LOGIC;
- signal bit_ctrl_n_16 : STD_LOGIC;
signal bit_ctrl_n_17 : STD_LOGIC;
signal bit_ctrl_n_18 : STD_LOGIC;
- signal bit_ctrl_n_5 : STD_LOGIC;
- signal bit_ctrl_n_6 : STD_LOGIC;
+ signal bit_ctrl_n_19 : STD_LOGIC;
+ signal bit_ctrl_n_20 : STD_LOGIC;
signal bit_ctrl_n_7 : STD_LOGIC;
signal bit_ctrl_n_8 : STD_LOGIC;
signal bit_ctrl_n_9 : STD_LOGIC;
@@ -3135,12 +3095,12 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ct
attribute KEEP of \FSM_sequential_statemachine.c_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_statemachine.c_state_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair22";
begin
iscl_oen_reg <= \^iscl_oen_reg\;
\FSM_sequential_statemachine.c_state[0]_i_2\: unisim.vcomponents.LUT5
@@ -3194,7 +3154,7 @@ begin
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_18,
+ D => bit_ctrl_n_20,
Q => \c_state__0\(0)
);
\FSM_sequential_statemachine.c_state_reg[1]\: unisim.vcomponents.FDCE
@@ -3202,7 +3162,7 @@ begin
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_17,
+ D => bit_ctrl_n_19,
Q => \c_state__0\(1)
);
\FSM_sequential_statemachine.c_state_reg[2]\: unisim.vcomponents.FDCE
@@ -3210,7 +3170,7 @@ begin
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_16,
+ D => bit_ctrl_n_18,
Q => \c_state__0\(2)
);
bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
@@ -3221,9 +3181,9 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
\FSM_sequential_statemachine.c_state_reg[1]_0\ => \statemachine.core_cmd[1]_i_2_n_0\,
\FSM_sequential_statemachine.c_state_reg[1]_1\ => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\,
\FSM_sequential_statemachine.c_state_reg[1]_2\ => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\,
- \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_16,
- \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_17,
- \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_18,
+ \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_18,
+ \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_19,
+ \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_20,
Q(15 downto 0) => Q(15 downto 0),
ack_in => ack_in,
ack_out => ack_out,
@@ -3236,8 +3196,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
\cr_reg[7]\(3 downto 0) => \cr_reg[7]\(3 downto 0),
\cr_reg[7]_0\ => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\,
\ctr_reg[7]\(0) => \ctr_reg[7]\(7),
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
+ dscl_oen_reg_0 => dscl_oen_reg,
iack_o_reg => iack_o_reg,
iack_o_reg_0 => iack_o_reg_0,
irq_flag => irq_flag,
@@ -3246,22 +3205,25 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
\out\(2 downto 0) => \c_state__0\(2 downto 0),
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
- \sr_reg[0]\(0) => bit_ctrl_n_15,
+ scl_pad_i => scl_pad_i,
+ sda_pad_i => sda_pad_i,
+ sda_padoen_o => sda_padoen_o,
+ \sr_reg[0]\(0) => bit_ctrl_n_17,
\sr_reg[6]\ => \wb_dat_o[6]_i_2_n_0\,
\sr_reg[7]\(0) => dout(7),
\st_irq_block.al_reg\ => \st_irq_block.al_reg\,
- \statemachine.ack_out_reg\ => bit_ctrl_n_13,
- \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_5,
- \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_6,
- \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_7,
- \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_8,
+ \statemachine.ack_out_reg\ => bit_ctrl_n_15,
+ \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_7,
+ \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_8,
+ \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_9,
+ \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_10,
\statemachine.core_cmd_reg[3]_0\(3 downto 0) => cmd(3 downto 0),
- \statemachine.core_txd_reg\ => bit_ctrl_n_10,
+ \statemachine.core_txd_reg\ => bit_ctrl_n_12,
\statemachine.core_txd_reg_0\ => \statemachine.core_txd_reg_n_0\,
- \statemachine.host_ack_reg\ => bit_ctrl_n_12,
- \statemachine.ld_reg\ => bit_ctrl_n_9,
+ \statemachine.host_ack_reg\ => bit_ctrl_n_14,
+ \statemachine.ld_reg\ => bit_ctrl_n_11,
\statemachine.ld_reg_0\ => \statemachine.ld_reg_n_0\,
- \statemachine.shift_reg\ => bit_ctrl_n_11,
+ \statemachine.shift_reg\ => bit_ctrl_n_13,
\txr_reg[6]\(1) => \txr_reg[7]\(6),
\txr_reg[6]\(0) => \txr_reg[7]\(0),
wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
@@ -3416,7 +3378,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => dcnt,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_15,
+ D => bit_ctrl_n_17,
Q => \sr_reg_n_0_[0]\
);
\sr_reg[1]\: unisim.vcomponents.FDCE
@@ -3489,7 +3451,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_13,
+ D => bit_ctrl_n_15,
Q => ack_out
);
\statemachine.core_cmd[1]_i_2\: unisim.vcomponents.LUT5
@@ -3535,7 +3497,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_8,
+ D => bit_ctrl_n_10,
Q => cmd(0)
);
\statemachine.core_cmd_reg[1]\: unisim.vcomponents.FDCE
@@ -3543,7 +3505,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_7,
+ D => bit_ctrl_n_9,
Q => cmd(1)
);
\statemachine.core_cmd_reg[2]\: unisim.vcomponents.FDCE
@@ -3551,7 +3513,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_6,
+ D => bit_ctrl_n_8,
Q => cmd(2)
);
\statemachine.core_cmd_reg[3]\: unisim.vcomponents.FDCE
@@ -3559,7 +3521,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => c_state,
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_5,
+ D => bit_ctrl_n_7,
Q => cmd(3)
);
\statemachine.core_txd_reg\: unisim.vcomponents.FDCE
@@ -3567,7 +3529,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_10,
+ D => bit_ctrl_n_12,
Q => \statemachine.core_txd_reg_n_0\
);
\statemachine.host_ack_reg\: unisim.vcomponents.FDCE
@@ -3575,7 +3537,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_12,
+ D => bit_ctrl_n_14,
Q => cmd_ack
);
\statemachine.ld_reg\: unisim.vcomponents.FDCE
@@ -3583,7 +3545,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_9,
+ D => bit_ctrl_n_11,
Q => \statemachine.ld_reg_n_0\
);
\statemachine.shift_reg\: unisim.vcomponents.FDCE
@@ -3591,7 +3553,7 @@ bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
C => s00_axi_aclk,
CE => '1',
CLR => \^iscl_oen_reg\,
- D => bit_ctrl_n_11,
+ D => bit_ctrl_n_13,
Q => \statemachine.shift_reg_n_0\
);
\wb_dat_o[0]_i_2\: unisim.vcomponents.LUT6
@@ -3774,16 +3736,18 @@ entity system_design_axi_wb_i2c_master_2_0_i2c_master_top is
port (
wb_ack_i : out STD_LOGIC;
wb_rst_o : out STD_LOGIC;
+ scl_padoen_o : out STD_LOGIC;
axi_int_o : out STD_LOGIC;
+ sda_padoen_o : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_stb_r_reg : out STD_LOGIC;
\s_rdata_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_rdata_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- i2c_sda_io : inout STD_LOGIC;
- i2c_scl_io : inout STD_LOGIC;
s_stb_r_reg_0 : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
+ sda_pad_i : in STD_LOGIC;
+ scl_pad_i : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
@@ -3805,7 +3769,7 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_top is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ack_in : STD_LOGIC;
signal al : STD_LOGIC;
- signal byte_ctrl_n_12 : STD_LOGIC;
+ signal byte_ctrl_n_14 : STD_LOGIC;
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
@@ -3853,26 +3817,26 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_top is
signal \^wb_rst_o\ : STD_LOGIC;
signal write : STD_LOGIC;
attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair25";
begin
Q(0) <= \^q\(0);
wb_ack_i <= \^wb_ack_i\;
@@ -3880,7 +3844,7 @@ begin
byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
port map (
D(7 downto 0) => wb_dat_o(7 downto 0),
- E(0) => byte_ctrl_n_12,
+ E(0) => byte_ctrl_n_14,
Q(15 downto 2) => data0(13 downto 0),
Q(1) => \prer_reg_n_0_[1]\,
Q(0) => \prer_reg_n_0_[0]\,
@@ -3904,8 +3868,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
\ctr_reg[7]\(2) => \ctr_reg_n_0_[2]\,
\ctr_reg[7]\(1) => \ctr_reg_n_0_[1]\,
\ctr_reg[7]\(0) => \ctr_reg_n_0_[0]\,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
+ dscl_oen_reg => scl_padoen_o,
iack_o_reg => \^wb_ack_i\,
iack_o_reg_0 => iack_o_reg_0,
irq_flag => irq_flag,
@@ -3914,6 +3877,9 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
rxack_0 => rxack_0,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
+ scl_pad_i => scl_pad_i,
+ sda_pad_i => sda_pad_i,
+ sda_padoen_o => sda_padoen_o,
\st_irq_block.al_reg\ => \st_irq_block.al_reg_n_0\,
\txr_reg[7]\(7 downto 0) => txr(7 downto 0),
wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
@@ -4004,7 +3970,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
\cr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(0),
Q => write
@@ -4012,7 +3978,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
\cr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(1),
Q => read
@@ -4020,7 +3986,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
\cr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(2),
Q => stop
@@ -4028,7 +3994,7 @@ byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
\cr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s00_axi_aclk,
- CE => byte_ctrl_n_12,
+ CE => byte_ctrl_n_14,
CLR => \^wb_rst_o\,
D => D(3),
Q => start
@@ -4686,17 +4652,24 @@ architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
signal cmp_axis_wbm_bridge_n_19 : STD_LOGIC;
signal cmp_axis_wbm_bridge_n_21 : STD_LOGIC;
signal cmp_axis_wbm_bridge_n_7 : STD_LOGIC;
- signal cmp_i2c_master_top_n_4 : STD_LOGIC;
- signal cmp_i2c_master_top_n_5 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_6 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_7 : STD_LOGIC;
signal ena : STD_LOGIC;
signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s00_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal scl_pad_i : STD_LOGIC;
+ signal scl_padoen_o : STD_LOGIC;
+ signal sda_pad_i : STD_LOGIC;
+ signal sda_padoen_o : STD_LOGIC;
signal wb_ack_i : STD_LOGIC;
signal wb_adr_o : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wb_cyc_o : STD_LOGIC;
signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wb_rst_o : STD_LOGIC;
signal wb_we_o : STD_LOGIC;
+ attribute box_type : string;
+ attribute box_type of iobuf_i2c_scl : label is "PRIMITIVE";
+ attribute box_type of iobuf_i2c_sda : label is "PRIMITIVE";
begin
s00_axi_bresp(1) <= \^s00_axi_bresp\(1);
s00_axi_bresp(0) <= \<const0>\;
@@ -4743,8 +4716,8 @@ cmp_axis_wbm_bridge: entity work.system_design_axi_wb_i2c_master_2_0_axis_wbm_br
\cr_reg[4]\ => cmp_axis_wbm_bridge_n_16,
\ctr_reg[0]\(0) => cmp_axis_wbm_bridge_n_19,
iack_o_reg => cmp_axis_wbm_bridge_n_21,
- iack_o_reg_0 => cmp_i2c_master_top_n_4,
- iack_o_reg_1(0) => cmp_i2c_master_top_n_5,
+ iack_o_reg_0 => cmp_i2c_master_top_n_6,
+ iack_o_reg_1(0) => cmp_i2c_master_top_n_7,
\prer_reg[8]\(1) => cmp_axis_wbm_bridge_n_17,
\prer_reg[8]\(0) => cmp_axis_wbm_bridge_n_18,
s00_axi_aclk => s00_axi_aclk,
@@ -4781,8 +4754,6 @@ cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_t
E(0) => cmp_axis_wbm_bridge_n_18,
Q(0) => ena,
axi_int_o => axi_int_o,
- i2c_scl_io => i2c_scl_io,
- i2c_sda_io => i2c_sda_io,
iack_o_reg_0 => cmp_axis_wbm_bridge_n_16,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
@@ -4790,18 +4761,42 @@ cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_t
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_wdata(7 downto 0) => s00_axi_wdata(7 downto 0),
\s_addr_reg[4]\ => cmp_axis_wbm_bridge_n_7,
- \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_5,
+ \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_7,
\s_rdata_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
- s_stb_r_reg => cmp_i2c_master_top_n_4,
+ s_stb_r_reg => cmp_i2c_master_top_n_6,
s_stb_r_reg_0 => cmp_axis_wbm_bridge_n_21,
s_we_r_reg(0) => cmp_axis_wbm_bridge_n_19,
s_we_r_reg_0(0) => cmp_axis_wbm_bridge_n_11,
+ scl_pad_i => scl_pad_i,
+ scl_padoen_o => scl_padoen_o,
+ sda_pad_i => sda_pad_i,
+ sda_padoen_o => sda_padoen_o,
wb_ack_i => wb_ack_i,
wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
wb_cyc_o => wb_cyc_o,
wb_rst_o => wb_rst_o,
wb_we_o => wb_we_o
);
+iobuf_i2c_scl: unisim.vcomponents.IOBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => '0',
+ IO => i2c_scl_io,
+ O => scl_pad_i,
+ T => scl_padoen_o
+ );
+iobuf_i2c_sda: unisim.vcomponents.IOBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => '0',
+ IO => i2c_sda_io,
+ O => sda_pad_i,
+ T => sda_padoen_o
+ );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.v
index c10cf792e4e170e461d059539fac5c8105e1ca4c..d9e0bca10a28a6d8fbf824e8aa6576cd8994b23f 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Tue Jun 20 20:06:00 2017
+// Date : Wed Oct 11 12:12:02 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.vhdl
index ea4ee8b0cb0c78f777eaf3c5f7db22cfc43b563e..914e175585547bda068df6d2be9c3ad586fb7cff 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Tue Jun 20 20:06:00 2017
+-- Date : Wed Oct 11 12:12:02 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp
index d5e7e5bc46b1ca06e97667bceaebd478f073182c..0c450a338173d405b1561b0a7143b1648ff2c1d7 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
index a67ebc2767d7683de2f23e453a247786ea14f784..18f4f898d7e561f5638ecf3ea266c87d77adc50a 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
@@ -358,7 +358,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:38 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:21 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -389,7 +389,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:38 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:21 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -419,7 +419,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:38 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:21 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -450,7 +450,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:28:38 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:10:21 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -480,7 +480,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Jun 21 06:34:35 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 10:13:24 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
index d22c6f9f393799cb8ebcfc15d121cf0d8ef041db..70045f18a10243b9846b7837e9233ba9d85967b1 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:34:34 2017
+// Date : Wed Oct 11 12:13:22 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
@@ -4154,7 +4154,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.C(s00_axi_aclk),
.CE(axi_arready_i_1_n_0),
.D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[22]_0 ),
+ .Q(\axi_rdata_reg[22]_1 ),
.R(rst_i));
(* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
FDRE #(
@@ -4163,7 +4163,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.C(s00_axi_aclk),
.CE(axi_arready_i_1_n_0),
.D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[17]_0 ),
+ .Q(\axi_rdata_reg[17]_1 ),
.R(rst_i));
(* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
FDRE #(
@@ -4172,7 +4172,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.C(s00_axi_aclk),
.CE(axi_arready_i_1_n_0),
.D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[12]_1 ),
+ .Q(\axi_rdata_reg[12]_0 ),
.R(rst_i));
(* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
FDRE #(
@@ -4208,7 +4208,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.C(s00_axi_aclk),
.CE(axi_arready_i_1_n_0),
.D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[22]_1 ),
+ .Q(\axi_rdata_reg[22]_0 ),
.R(rst_i));
(* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
FDRE #(
@@ -4217,7 +4217,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.C(s00_axi_aclk),
.CE(axi_arready_i_1_n_0),
.D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[17]_1 ),
+ .Q(\axi_rdata_reg[17]_0 ),
.R(rst_i));
(* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
FDRE #(
@@ -4226,7 +4226,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.C(s00_axi_aclk),
.CE(axi_arready_i_1_n_0),
.D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[12]_0 ),
+ .Q(\axi_rdata_reg[12]_1 ),
.R(rst_i));
(* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
FDRE #(
@@ -4441,7 +4441,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I3(s00_axi_wvalid),
.I4(s00_axi_awvalid),
.O(axi_bvalid04_out));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h01FF))
\axi_bresp[1]_i_3
@@ -4483,7 +4483,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_araddr_reg[5]_rep_10 ),
.O(\axi_rdata[0]_i_1_n_0 ));
LUT6 #(
- .INIT(64'hEE55FA00EE00FA00))
+ .INIT(64'h4455FA004400FA00))
\axi_rdata[0]_i_14
(.I0(\axi_rdata_reg[0]_0 ),
.I1(\data_rw_o[3] [0]),
@@ -4683,19 +4683,19 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[10]_i_13
- (.I0(\axi_rdata_reg[12]_1 ),
+ (.I0(\axi_rdata_reg[12]_0 ),
.I1(\s_datao_fmc1[4] [2]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[10]_i_33_n_0 ),
.O(\axi_rdata[10]_i_13_n_0 ));
LUT5 #(
- .INIT(32'hCC408840))
+ .INIT(32'hCCC888C8))
\axi_rdata[10]_i_14
(.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[12]_0 ),
+ .I1(\axi_rdata_reg[12]_1 ),
.I2(gem_status_vector_i[10]),
- .I3(\axi_rdata_reg[12]_1 ),
+ .I3(\axi_rdata_reg[12]_0 ),
.I4(\data_rw_o_reg_n_0_[3][10] ),
.O(\axi_rdata[10]_i_14_n_0 ));
LUT6 #(
@@ -4703,9 +4703,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_17
(.I0(\axi_rdata[10]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\dac_ch_o_reg[0][31]_0 [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[10]_i_17_n_0 ));
LUT5 #(
@@ -4713,17 +4713,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_19
(.I0(\axi_rdata[10]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\s_datao_fmc2[4] [2]),
- .I4(\axi_rdata_reg[12]_0 ),
+ .I4(\axi_rdata_reg[12]_1 ),
.O(\axi_rdata[10]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[10]_i_23
- (.I0(\axi_rdata_reg[12]_0 ),
+ (.I0(\axi_rdata_reg[12]_1 ),
.I1(\dac_ch_o_reg[0][31] [10]),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[10]_i_23_n_0 ));
LUT6 #(
@@ -4731,9 +4731,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_29
(.I0(\[2].[3].s_reqs_reg[11][value][11] [10]),
.I1(\[2].[2].s_reqs_reg[10][value][11] [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11] [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11] [10]),
.O(\axi_rdata[10]_i_29_n_0 ));
LUT6 #(
@@ -4741,9 +4741,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_30
(.I0(\[3].[3].s_reqs_reg[15][value][11] [10]),
.I1(\[3].[2].s_reqs_reg[14][value][11] [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11] [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11] [10]),
.O(\axi_rdata[10]_i_30_n_0 ));
LUT6 #(
@@ -4751,9 +4751,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_31
(.I0(Q[10]),
.I1(\[0].[2].s_reqs_reg[2][value][11] [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11] [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11] [10]),
.O(\axi_rdata[10]_i_31_n_0 ));
LUT6 #(
@@ -4761,9 +4761,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_32
(.I0(\[1].[3].s_reqs_reg[7][value][11] [10]),
.I1(\[1].[2].s_reqs_reg[6][value][11] [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11] [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11] [10]),
.O(\axi_rdata[10]_i_32_n_0 ));
LUT5 #(
@@ -4771,18 +4771,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_33
(.I0(\data_rw_o_reg_n_0_[11][10] ),
.I1(\data_rw_o_reg_n_0_[10][10] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc1[0] [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[10]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[10]_i_34
(.I0(\[4].[3].s_reqs_reg[19][value][11] [10]),
.I1(\[4].[2].s_reqs_reg[18][value][11] [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11] [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11] [10]),
.O(\axi_rdata[10]_i_34_n_0 ));
LUT6 #(
@@ -4790,9 +4790,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_35
(.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [10]),
.I1(\[1].[2].s_reqs_reg[6][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11]_0 [10]),
.O(\axi_rdata[10]_i_35_n_0 ));
LUT6 #(
@@ -4800,9 +4800,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_36
(.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [10]),
.I1(\[2].[2].s_reqs_reg[10][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11]_0 [10]),
.O(\axi_rdata[10]_i_36_n_0 ));
LUT6 #(
@@ -4810,9 +4810,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_37
(.I0(\[0].[3].s_reqs_reg[3][value][11] [10]),
.I1(\[0].[2].s_reqs_reg[2][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11]_0 [10]),
.O(\axi_rdata[10]_i_37_n_0 ));
LUT5 #(
@@ -4820,18 +4820,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_39
(.I0(\data_rw_o_reg_n_0_[79][10] ),
.I1(\data_rw_o_reg_n_0_[78][10] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc2[0] [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[10]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[10]_i_42
(.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [10]),
.I1(\[3].[2].s_reqs_reg[14][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11]_0 [10]),
.O(\axi_rdata[10]_i_42_n_0 ));
LUT6 #(
@@ -4839,9 +4839,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[10]_i_43
(.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [10]),
.I1(\[4].[2].s_reqs_reg[18][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11]_0 [10]),
.O(\axi_rdata[10]_i_43_n_0 ));
LUT6 #(
@@ -4897,19 +4897,19 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[11]_i_13
- (.I0(\axi_rdata_reg[12]_1 ),
+ (.I0(\axi_rdata_reg[12]_0 ),
.I1(\s_datao_fmc1[4] [3]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[11]_i_33_n_0 ),
.O(\axi_rdata[11]_i_13_n_0 ));
LUT5 #(
- .INIT(32'hCC408840))
+ .INIT(32'hCCC888C8))
\axi_rdata[11]_i_14
(.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[12]_0 ),
+ .I1(\axi_rdata_reg[12]_1 ),
.I2(gem_status_vector_i[11]),
- .I3(\axi_rdata_reg[12]_1 ),
+ .I3(\axi_rdata_reg[12]_0 ),
.I4(\data_rw_o_reg_n_0_[3][11] ),
.O(\axi_rdata[11]_i_14_n_0 ));
LUT6 #(
@@ -4917,9 +4917,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_17
(.I0(\axi_rdata[11]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\dac_ch_o_reg[0][31]_0 [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[11]_i_17_n_0 ));
LUT5 #(
@@ -4927,17 +4927,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_19
(.I0(\axi_rdata[11]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\s_datao_fmc2[4] [3]),
- .I4(\axi_rdata_reg[12]_0 ),
+ .I4(\axi_rdata_reg[12]_1 ),
.O(\axi_rdata[11]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[11]_i_23
- (.I0(\axi_rdata_reg[12]_0 ),
+ (.I0(\axi_rdata_reg[12]_1 ),
.I1(\dac_ch_o_reg[0][31] [11]),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[11]_i_23_n_0 ));
LUT6 #(
@@ -4945,9 +4945,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_29
(.I0(\[2].[3].s_reqs_reg[11][value][11] [11]),
.I1(\[2].[2].s_reqs_reg[10][value][11] [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11] [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11] [11]),
.O(\axi_rdata[11]_i_29_n_0 ));
LUT6 #(
@@ -4955,9 +4955,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_30
(.I0(\[3].[3].s_reqs_reg[15][value][11] [11]),
.I1(\[3].[2].s_reqs_reg[14][value][11] [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11] [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11] [11]),
.O(\axi_rdata[11]_i_30_n_0 ));
LUT6 #(
@@ -4965,9 +4965,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_31
(.I0(Q[11]),
.I1(\[0].[2].s_reqs_reg[2][value][11] [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11] [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11] [11]),
.O(\axi_rdata[11]_i_31_n_0 ));
LUT6 #(
@@ -4975,9 +4975,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_32
(.I0(\[1].[3].s_reqs_reg[7][value][11] [11]),
.I1(\[1].[2].s_reqs_reg[6][value][11] [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11] [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11] [11]),
.O(\axi_rdata[11]_i_32_n_0 ));
LUT5 #(
@@ -4985,18 +4985,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_33
(.I0(\data_rw_o_reg_n_0_[11][11] ),
.I1(\data_rw_o_reg_n_0_[10][11] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc1[0] [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[11]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[11]_i_34
(.I0(\[4].[3].s_reqs_reg[19][value][11] [11]),
.I1(\[4].[2].s_reqs_reg[18][value][11] [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11] [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11] [11]),
.O(\axi_rdata[11]_i_34_n_0 ));
LUT6 #(
@@ -5004,9 +5004,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_35
(.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [11]),
.I1(\[1].[2].s_reqs_reg[6][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11]_0 [11]),
.O(\axi_rdata[11]_i_35_n_0 ));
LUT6 #(
@@ -5014,9 +5014,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_36
(.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [11]),
.I1(\[2].[2].s_reqs_reg[10][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11]_0 [11]),
.O(\axi_rdata[11]_i_36_n_0 ));
LUT6 #(
@@ -5024,9 +5024,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_37
(.I0(\[0].[3].s_reqs_reg[3][value][11] [11]),
.I1(\[0].[2].s_reqs_reg[2][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11]_0 [11]),
.O(\axi_rdata[11]_i_37_n_0 ));
LUT5 #(
@@ -5034,18 +5034,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_39
(.I0(\data_rw_o_reg_n_0_[79][11] ),
.I1(\data_rw_o_reg_n_0_[78][11] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc2[0] [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[11]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[11]_i_42
(.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [11]),
.I1(\[3].[2].s_reqs_reg[14][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11]_0 [11]),
.O(\axi_rdata[11]_i_42_n_0 ));
LUT6 #(
@@ -5053,9 +5053,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[11]_i_43
(.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [11]),
.I1(\[4].[2].s_reqs_reg[18][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11]_0 [11]),
.O(\axi_rdata[11]_i_43_n_0 ));
LUT6 #(
@@ -5111,19 +5111,19 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[12]_i_13
- (.I0(\axi_rdata_reg[12]_1 ),
+ (.I0(\axi_rdata_reg[12]_0 ),
.I1(\s_datao_fmc1[4] [4]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[12]_i_33_n_0 ),
.O(\axi_rdata[12]_i_13_n_0 ));
LUT5 #(
- .INIT(32'h44C800C8))
+ .INIT(32'hCCC888C8))
\axi_rdata[12]_i_14
(.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[12]_0 ),
+ .I1(\axi_rdata_reg[12]_1 ),
.I2(gem_status_vector_i[12]),
- .I3(\axi_rdata_reg[12]_1 ),
+ .I3(\axi_rdata_reg[12]_0 ),
.I4(\data_rw_o_reg_n_0_[3][12] ),
.O(\axi_rdata[12]_i_14_n_0 ));
LUT6 #(
@@ -5131,9 +5131,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_17
(.I0(\axi_rdata[12]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\dac_ch_o_reg[0][31]_0 [12]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[12]_i_17_n_0 ));
LUT5 #(
@@ -5141,16 +5141,16 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_19
(.I0(\axi_rdata[12]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\s_datao_fmc2[4] [4]),
- .I4(\axi_rdata_reg[12]_0 ),
+ .I4(\axi_rdata_reg[12]_1 ),
.O(\axi_rdata[12]_i_19_n_0 ));
LUT4 #(
.INIT(16'h0004))
\axi_rdata[12]_i_23
- (.I0(\axi_rdata_reg[12]_0 ),
+ (.I0(\axi_rdata_reg[12]_1 ),
.I1(\dac_ch_o_reg[0][31] [12]),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[12]_i_23_n_0 ));
LUT6 #(
@@ -5158,9 +5158,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_29
(.I0(\data_rw_o_reg_n_0_[27][12] ),
.I1(\data_rw_o_reg_n_0_[26][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[25][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[24][12] ),
.O(\axi_rdata[12]_i_29_n_0 ));
LUT6 #(
@@ -5168,9 +5168,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_30
(.I0(\data_rw_o_reg_n_0_[31][12] ),
.I1(\data_rw_o_reg_n_0_[30][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[29][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[28][12] ),
.O(\axi_rdata[12]_i_30_n_0 ));
LUT6 #(
@@ -5178,9 +5178,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_31
(.I0(\data_rw_o_reg_n_0_[19][12] ),
.I1(\data_rw_o_reg_n_0_[18][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[17][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[16][12] ),
.O(\axi_rdata[12]_i_31_n_0 ));
LUT6 #(
@@ -5188,9 +5188,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_32
(.I0(\data_rw_o_reg_n_0_[23][12] ),
.I1(\data_rw_o_reg_n_0_[22][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[21][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[20][12] ),
.O(\axi_rdata[12]_i_32_n_0 ));
LUT5 #(
@@ -5198,18 +5198,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_33
(.I0(\data_rw_o_reg_n_0_[11][12] ),
.I1(\data_rw_o_reg_n_0_[10][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc1[0] [12]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[12]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[12]_i_34
(.I0(\data_rw_o_reg_n_0_[35][12] ),
.I1(\data_rw_o_reg_n_0_[34][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[33][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[32][12] ),
.O(\axi_rdata[12]_i_34_n_0 ));
LUT6 #(
@@ -5217,9 +5217,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_35
(.I0(\data_rw_o_reg_n_0_[91][12] ),
.I1(\data_rw_o_reg_n_0_[90][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[89][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[88][12] ),
.O(\axi_rdata[12]_i_35_n_0 ));
LUT6 #(
@@ -5227,9 +5227,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_36
(.I0(\data_rw_o_reg_n_0_[95][12] ),
.I1(\data_rw_o_reg_n_0_[94][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[93][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[92][12] ),
.O(\axi_rdata[12]_i_36_n_0 ));
LUT6 #(
@@ -5237,9 +5237,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_37
(.I0(\data_rw_o_reg_n_0_[87][12] ),
.I1(\data_rw_o_reg_n_0_[86][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[85][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[84][12] ),
.O(\axi_rdata[12]_i_37_n_0 ));
LUT5 #(
@@ -5247,18 +5247,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_39
(.I0(\data_rw_o_reg_n_0_[79][12] ),
.I1(\data_rw_o_reg_n_0_[78][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc2[0] [12]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[12]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[12]_i_42
(.I0(\data_rw_o_reg_n_0_[99][12] ),
.I1(\data_rw_o_reg_n_0_[98][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[97][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[96][12] ),
.O(\axi_rdata[12]_i_42_n_0 ));
LUT6 #(
@@ -5266,9 +5266,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[12]_i_43
(.I0(\data_rw_o_reg_n_0_[103][12] ),
.I1(\data_rw_o_reg_n_0_[102][12] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\data_rw_o_reg_n_0_[101][12] ),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\data_rw_o_reg_n_0_[100][12] ),
.O(\axi_rdata[12]_i_43_n_0 ));
LUT6 #(
@@ -5324,29 +5324,29 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[13]_i_13
- (.I0(\axi_rdata_reg[17]_0 ),
+ (.I0(\axi_rdata_reg[17]_1 ),
.I1(\s_datao_fmc1[4] [5]),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[13]_i_33_n_0 ),
.O(\axi_rdata[13]_i_13_n_0 ));
LUT5 #(
- .INIT(32'h0000B800))
+ .INIT(32'hCCC888C8))
\axi_rdata[13]_i_14
- (.I0(\data_rw_o_reg_n_0_[3][13] ),
+ (.I0(\axi_rdata_reg[18]_0 ),
.I1(\axi_rdata_reg[17]_0 ),
.I2(gem_status_vector_i[13]),
.I3(\axi_rdata_reg[17]_1 ),
- .I4(\axi_rdata_reg[18]_0 ),
+ .I4(\data_rw_o_reg_n_0_[3][13] ),
.O(\axi_rdata[13]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000000022222E22))
\axi_rdata[13]_i_17
(.I0(\axi_rdata[13]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [13]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[13]_i_17_n_0 ));
LUT5 #(
@@ -5354,17 +5354,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_19
(.I0(\axi_rdata[13]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\s_datao_fmc2[4] [5]),
- .I4(\axi_rdata_reg[17]_1 ),
+ .I4(\axi_rdata_reg[17]_0 ),
.O(\axi_rdata[13]_i_19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[13]_i_23
- (.I0(\axi_rdata_reg[17]_1 ),
+ (.I0(\axi_rdata_reg[17]_0 ),
.I1(\dac_ch_o_reg[0][31] [13]),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[13]_i_23_n_0 ));
LUT6 #(
@@ -5372,9 +5372,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_29
(.I0(\data_rw_o_reg_n_0_[27][13] ),
.I1(\data_rw_o_reg_n_0_[26][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[25][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[24][13] ),
.O(\axi_rdata[13]_i_29_n_0 ));
LUT6 #(
@@ -5382,9 +5382,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_30
(.I0(\data_rw_o_reg_n_0_[31][13] ),
.I1(\data_rw_o_reg_n_0_[30][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[29][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[28][13] ),
.O(\axi_rdata[13]_i_30_n_0 ));
LUT6 #(
@@ -5392,9 +5392,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_31
(.I0(\data_rw_o_reg_n_0_[19][13] ),
.I1(\data_rw_o_reg_n_0_[18][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[17][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[16][13] ),
.O(\axi_rdata[13]_i_31_n_0 ));
LUT6 #(
@@ -5402,9 +5402,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_32
(.I0(\data_rw_o_reg_n_0_[23][13] ),
.I1(\data_rw_o_reg_n_0_[22][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[21][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[20][13] ),
.O(\axi_rdata[13]_i_32_n_0 ));
LUT5 #(
@@ -5412,18 +5412,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_33
(.I0(\data_rw_o_reg_n_0_[11][13] ),
.I1(\data_rw_o_reg_n_0_[10][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc1[0] [13]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[13]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[13]_i_34
(.I0(\data_rw_o_reg_n_0_[35][13] ),
.I1(\data_rw_o_reg_n_0_[34][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[33][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[32][13] ),
.O(\axi_rdata[13]_i_34_n_0 ));
LUT6 #(
@@ -5431,9 +5431,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_35
(.I0(\data_rw_o_reg_n_0_[91][13] ),
.I1(\data_rw_o_reg_n_0_[90][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[89][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[88][13] ),
.O(\axi_rdata[13]_i_35_n_0 ));
LUT6 #(
@@ -5441,9 +5441,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_36
(.I0(\data_rw_o_reg_n_0_[95][13] ),
.I1(\data_rw_o_reg_n_0_[94][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[93][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[92][13] ),
.O(\axi_rdata[13]_i_36_n_0 ));
LUT6 #(
@@ -5451,9 +5451,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_37
(.I0(\data_rw_o_reg_n_0_[87][13] ),
.I1(\data_rw_o_reg_n_0_[86][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[85][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[84][13] ),
.O(\axi_rdata[13]_i_37_n_0 ));
LUT5 #(
@@ -5461,18 +5461,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_39
(.I0(\data_rw_o_reg_n_0_[79][13] ),
.I1(\data_rw_o_reg_n_0_[78][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc2[0] [13]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[13]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[13]_i_42
(.I0(\data_rw_o_reg_n_0_[99][13] ),
.I1(\data_rw_o_reg_n_0_[98][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[97][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[96][13] ),
.O(\axi_rdata[13]_i_42_n_0 ));
LUT6 #(
@@ -5480,9 +5480,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[13]_i_43
(.I0(\data_rw_o_reg_n_0_[103][13] ),
.I1(\data_rw_o_reg_n_0_[102][13] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[101][13] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[100][13] ),
.O(\axi_rdata[13]_i_43_n_0 ));
LUT6 #(
@@ -5538,9 +5538,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[14]_i_13
- (.I0(\axi_rdata_reg[17]_0 ),
+ (.I0(\axi_rdata_reg[17]_1 ),
.I1(\s_datao_fmc1[4] [6]),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[14]_i_33_n_0 ),
.O(\axi_rdata[14]_i_13_n_0 ));
@@ -5548,9 +5548,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.INIT(32'h0000B800))
\axi_rdata[14]_i_14
(.I0(\data_rw_o_reg_n_0_[3][14] ),
- .I1(\axi_rdata_reg[17]_0 ),
+ .I1(\axi_rdata_reg[17]_1 ),
.I2(gem_status_vector_i[14]),
- .I3(\axi_rdata_reg[17]_1 ),
+ .I3(\axi_rdata_reg[17]_0 ),
.I4(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[14]_i_14_n_0 ));
LUT6 #(
@@ -5558,9 +5558,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_17
(.I0(\axi_rdata[14]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [14]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[14]_i_17_n_0 ));
LUT5 #(
@@ -5568,17 +5568,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_19
(.I0(\axi_rdata[14]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\s_datao_fmc2[4] [6]),
- .I4(\axi_rdata_reg[17]_1 ),
+ .I4(\axi_rdata_reg[17]_0 ),
.O(\axi_rdata[14]_i_19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[14]_i_23
- (.I0(\axi_rdata_reg[17]_1 ),
+ (.I0(\axi_rdata_reg[17]_0 ),
.I1(\dac_ch_o_reg[0][31] [14]),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[14]_i_23_n_0 ));
LUT6 #(
@@ -5586,9 +5586,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_29
(.I0(\data_rw_o_reg_n_0_[27][14] ),
.I1(\data_rw_o_reg_n_0_[26][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[25][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[24][14] ),
.O(\axi_rdata[14]_i_29_n_0 ));
LUT6 #(
@@ -5596,9 +5596,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_30
(.I0(\data_rw_o_reg_n_0_[31][14] ),
.I1(\data_rw_o_reg_n_0_[30][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[29][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[28][14] ),
.O(\axi_rdata[14]_i_30_n_0 ));
LUT6 #(
@@ -5606,9 +5606,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_31
(.I0(\data_rw_o_reg_n_0_[19][14] ),
.I1(\data_rw_o_reg_n_0_[18][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[17][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[16][14] ),
.O(\axi_rdata[14]_i_31_n_0 ));
LUT6 #(
@@ -5616,9 +5616,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_32
(.I0(\data_rw_o_reg_n_0_[23][14] ),
.I1(\data_rw_o_reg_n_0_[22][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[21][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[20][14] ),
.O(\axi_rdata[14]_i_32_n_0 ));
LUT5 #(
@@ -5626,18 +5626,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_33
(.I0(\data_rw_o_reg_n_0_[11][14] ),
.I1(\data_rw_o_reg_n_0_[10][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc1[0] [14]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[14]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[14]_i_34
(.I0(\data_rw_o_reg_n_0_[35][14] ),
.I1(\data_rw_o_reg_n_0_[34][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[33][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[32][14] ),
.O(\axi_rdata[14]_i_34_n_0 ));
LUT6 #(
@@ -5645,9 +5645,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_35
(.I0(\data_rw_o_reg_n_0_[91][14] ),
.I1(\data_rw_o_reg_n_0_[90][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[89][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[88][14] ),
.O(\axi_rdata[14]_i_35_n_0 ));
LUT6 #(
@@ -5655,9 +5655,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_36
(.I0(\data_rw_o_reg_n_0_[95][14] ),
.I1(\data_rw_o_reg_n_0_[94][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[93][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[92][14] ),
.O(\axi_rdata[14]_i_36_n_0 ));
LUT6 #(
@@ -5665,9 +5665,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_37
(.I0(\data_rw_o_reg_n_0_[87][14] ),
.I1(\data_rw_o_reg_n_0_[86][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[85][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[84][14] ),
.O(\axi_rdata[14]_i_37_n_0 ));
LUT5 #(
@@ -5675,18 +5675,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_39
(.I0(\data_rw_o_reg_n_0_[79][14] ),
.I1(\data_rw_o_reg_n_0_[78][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc2[0] [14]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[14]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[14]_i_42
(.I0(\data_rw_o_reg_n_0_[99][14] ),
.I1(\data_rw_o_reg_n_0_[98][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[97][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[96][14] ),
.O(\axi_rdata[14]_i_42_n_0 ));
LUT6 #(
@@ -5694,9 +5694,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[14]_i_43
(.I0(\data_rw_o_reg_n_0_[103][14] ),
.I1(\data_rw_o_reg_n_0_[102][14] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[101][14] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[100][14] ),
.O(\axi_rdata[14]_i_43_n_0 ));
LUT6 #(
@@ -5752,19 +5752,19 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[15]_i_13
- (.I0(\axi_rdata_reg[17]_0 ),
+ (.I0(\axi_rdata_reg[17]_1 ),
.I1(\s_datao_fmc1[4] [7]),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[15]_i_33_n_0 ),
.O(\axi_rdata[15]_i_13_n_0 ));
LUT5 #(
- .INIT(32'hCC408840))
+ .INIT(32'hCCC888C8))
\axi_rdata[15]_i_14
(.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_1 ),
+ .I1(\axi_rdata_reg[17]_0 ),
.I2(gem_status_vector_i[15]),
- .I3(\axi_rdata_reg[17]_0 ),
+ .I3(\axi_rdata_reg[17]_1 ),
.I4(\data_rw_o_reg_n_0_[3][15] ),
.O(\axi_rdata[15]_i_14_n_0 ));
LUT6 #(
@@ -5772,9 +5772,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_17
(.I0(\axi_rdata[15]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [15]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[15]_i_17_n_0 ));
LUT5 #(
@@ -5782,17 +5782,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_19
(.I0(\axi_rdata[15]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\s_datao_fmc2[4] [7]),
- .I4(\axi_rdata_reg[17]_1 ),
+ .I4(\axi_rdata_reg[17]_0 ),
.O(\axi_rdata[15]_i_19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[15]_i_23
- (.I0(\axi_rdata_reg[17]_1 ),
+ (.I0(\axi_rdata_reg[17]_0 ),
.I1(\dac_ch_o_reg[0][31] [15]),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[15]_i_23_n_0 ));
LUT6 #(
@@ -5800,9 +5800,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_29
(.I0(\data_rw_o_reg_n_0_[27][15] ),
.I1(\data_rw_o_reg_n_0_[26][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[25][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[24][15] ),
.O(\axi_rdata[15]_i_29_n_0 ));
LUT6 #(
@@ -5810,9 +5810,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_30
(.I0(\data_rw_o_reg_n_0_[31][15] ),
.I1(\data_rw_o_reg_n_0_[30][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[29][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[28][15] ),
.O(\axi_rdata[15]_i_30_n_0 ));
LUT6 #(
@@ -5820,9 +5820,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_31
(.I0(\data_rw_o_reg_n_0_[19][15] ),
.I1(\data_rw_o_reg_n_0_[18][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[17][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[16][15] ),
.O(\axi_rdata[15]_i_31_n_0 ));
LUT6 #(
@@ -5830,9 +5830,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_32
(.I0(\data_rw_o_reg_n_0_[23][15] ),
.I1(\data_rw_o_reg_n_0_[22][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[21][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[20][15] ),
.O(\axi_rdata[15]_i_32_n_0 ));
LUT5 #(
@@ -5840,18 +5840,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_33
(.I0(\data_rw_o_reg_n_0_[11][15] ),
.I1(\data_rw_o_reg_n_0_[10][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc1[0] [15]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[15]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[15]_i_34
(.I0(\data_rw_o_reg_n_0_[35][15] ),
.I1(\data_rw_o_reg_n_0_[34][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[33][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[32][15] ),
.O(\axi_rdata[15]_i_34_n_0 ));
LUT6 #(
@@ -5859,9 +5859,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_35
(.I0(\data_rw_o_reg_n_0_[91][15] ),
.I1(\data_rw_o_reg_n_0_[90][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[89][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[88][15] ),
.O(\axi_rdata[15]_i_35_n_0 ));
LUT6 #(
@@ -5869,9 +5869,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_36
(.I0(\data_rw_o_reg_n_0_[95][15] ),
.I1(\data_rw_o_reg_n_0_[94][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[93][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[92][15] ),
.O(\axi_rdata[15]_i_36_n_0 ));
LUT6 #(
@@ -5879,9 +5879,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_37
(.I0(\data_rw_o_reg_n_0_[87][15] ),
.I1(\data_rw_o_reg_n_0_[86][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[85][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[84][15] ),
.O(\axi_rdata[15]_i_37_n_0 ));
LUT5 #(
@@ -5889,18 +5889,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_39
(.I0(\data_rw_o_reg_n_0_[79][15] ),
.I1(\data_rw_o_reg_n_0_[78][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc2[0] [15]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[15]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[15]_i_42
(.I0(\data_rw_o_reg_n_0_[99][15] ),
.I1(\data_rw_o_reg_n_0_[98][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[97][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[96][15] ),
.O(\axi_rdata[15]_i_42_n_0 ));
LUT6 #(
@@ -5908,9 +5908,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[15]_i_43
(.I0(\data_rw_o_reg_n_0_[103][15] ),
.I1(\data_rw_o_reg_n_0_[102][15] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[101][15] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[100][15] ),
.O(\axi_rdata[15]_i_43_n_0 ));
LUT6 #(
@@ -5966,29 +5966,29 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[16]_i_13
- (.I0(\axi_rdata_reg[17]_0 ),
+ (.I0(\axi_rdata_reg[17]_1 ),
.I1(\s_datao_fmc1[4] [8]),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[16]_i_33_n_0 ),
.O(\axi_rdata[16]_i_13_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
- .INIT(16'hC800))
+ .INIT(16'hC888))
\axi_rdata[16]_i_14
(.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_1 ),
+ .I1(\axi_rdata_reg[17]_0 ),
.I2(\data_rw_o_reg_n_0_[3][16] ),
- .I3(\axi_rdata_reg[17]_0 ),
+ .I3(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[16]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000000022222E22))
\axi_rdata[16]_i_17
(.I0(\axi_rdata[16]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [16]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[16]_i_17_n_0 ));
LUT5 #(
@@ -5996,17 +5996,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_19
(.I0(\axi_rdata[16]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\s_datao_fmc2[4] [8]),
- .I4(\axi_rdata_reg[17]_1 ),
+ .I4(\axi_rdata_reg[17]_0 ),
.O(\axi_rdata[16]_i_19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[16]_i_23
- (.I0(\axi_rdata_reg[17]_1 ),
+ (.I0(\axi_rdata_reg[17]_0 ),
.I1(\dac_ch_o_reg[0][31] [16]),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[16]_i_23_n_0 ));
LUT6 #(
@@ -6014,9 +6014,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_29
(.I0(\data_rw_o_reg_n_0_[27][16] ),
.I1(\data_rw_o_reg_n_0_[26][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[25][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[24][16] ),
.O(\axi_rdata[16]_i_29_n_0 ));
LUT6 #(
@@ -6024,9 +6024,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_30
(.I0(\data_rw_o_reg_n_0_[31][16] ),
.I1(\data_rw_o_reg_n_0_[30][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[29][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[28][16] ),
.O(\axi_rdata[16]_i_30_n_0 ));
LUT6 #(
@@ -6034,9 +6034,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_31
(.I0(\data_rw_o_reg_n_0_[19][16] ),
.I1(\data_rw_o_reg_n_0_[18][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[17][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[16][16] ),
.O(\axi_rdata[16]_i_31_n_0 ));
LUT6 #(
@@ -6044,9 +6044,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_32
(.I0(\data_rw_o_reg_n_0_[23][16] ),
.I1(\data_rw_o_reg_n_0_[22][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[21][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[20][16] ),
.O(\axi_rdata[16]_i_32_n_0 ));
LUT5 #(
@@ -6054,18 +6054,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_33
(.I0(\data_rw_o_reg_n_0_[11][16] ),
.I1(\data_rw_o_reg_n_0_[10][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc1[0] [16]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[16]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[16]_i_34
(.I0(\data_rw_o_reg_n_0_[35][16] ),
.I1(\data_rw_o_reg_n_0_[34][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[33][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[32][16] ),
.O(\axi_rdata[16]_i_34_n_0 ));
LUT6 #(
@@ -6073,9 +6073,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_35
(.I0(\data_rw_o_reg_n_0_[91][16] ),
.I1(\data_rw_o_reg_n_0_[90][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[89][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[88][16] ),
.O(\axi_rdata[16]_i_35_n_0 ));
LUT6 #(
@@ -6083,9 +6083,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_36
(.I0(\data_rw_o_reg_n_0_[95][16] ),
.I1(\data_rw_o_reg_n_0_[94][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[93][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[92][16] ),
.O(\axi_rdata[16]_i_36_n_0 ));
LUT6 #(
@@ -6093,9 +6093,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_37
(.I0(\data_rw_o_reg_n_0_[87][16] ),
.I1(\data_rw_o_reg_n_0_[86][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[85][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[84][16] ),
.O(\axi_rdata[16]_i_37_n_0 ));
LUT5 #(
@@ -6103,18 +6103,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_39
(.I0(\data_rw_o_reg_n_0_[79][16] ),
.I1(\data_rw_o_reg_n_0_[78][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc2[0] [16]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[16]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[16]_i_42
(.I0(\data_rw_o_reg_n_0_[99][16] ),
.I1(\data_rw_o_reg_n_0_[98][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[97][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[96][16] ),
.O(\axi_rdata[16]_i_42_n_0 ));
LUT6 #(
@@ -6122,9 +6122,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[16]_i_43
(.I0(\data_rw_o_reg_n_0_[103][16] ),
.I1(\data_rw_o_reg_n_0_[102][16] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[101][16] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[100][16] ),
.O(\axi_rdata[16]_i_43_n_0 ));
LUT6 #(
@@ -6180,28 +6180,28 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[17]_i_13
- (.I0(\axi_rdata_reg[17]_0 ),
+ (.I0(\axi_rdata_reg[17]_1 ),
.I1(\s_datao_fmc1[4] [9]),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[17]_i_33_n_0 ),
.O(\axi_rdata[17]_i_13_n_0 ));
LUT4 #(
- .INIT(16'h4088))
+ .INIT(16'h0080))
\axi_rdata[17]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_1 ),
- .I2(\data_rw_o_reg_n_0_[3][17] ),
- .I3(\axi_rdata_reg[17]_0 ),
+ (.I0(\axi_rdata_reg[17]_1 ),
+ .I1(\data_rw_o_reg_n_0_[3][17] ),
+ .I2(\axi_rdata_reg[17]_0 ),
+ .I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[17]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000000022222E22))
\axi_rdata[17]_i_17
(.I0(\axi_rdata[17]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [17]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[17]_i_17_n_0 ));
LUT5 #(
@@ -6209,17 +6209,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_19
(.I0(\axi_rdata[17]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\s_datao_fmc2[4] [9]),
- .I4(\axi_rdata_reg[17]_1 ),
+ .I4(\axi_rdata_reg[17]_0 ),
.O(\axi_rdata[17]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[17]_i_23
- (.I0(\axi_rdata_reg[17]_1 ),
+ (.I0(\axi_rdata_reg[17]_0 ),
.I1(\dac_ch_o_reg[0][31] [17]),
- .I2(\axi_rdata_reg[17]_0 ),
+ .I2(\axi_rdata_reg[17]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[17]_i_23_n_0 ));
LUT6 #(
@@ -6227,9 +6227,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_29
(.I0(\data_rw_o_reg_n_0_[27][17] ),
.I1(\data_rw_o_reg_n_0_[26][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[25][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[24][17] ),
.O(\axi_rdata[17]_i_29_n_0 ));
LUT6 #(
@@ -6237,9 +6237,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_30
(.I0(\data_rw_o_reg_n_0_[31][17] ),
.I1(\data_rw_o_reg_n_0_[30][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[29][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[28][17] ),
.O(\axi_rdata[17]_i_30_n_0 ));
LUT6 #(
@@ -6247,9 +6247,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_31
(.I0(\data_rw_o_reg_n_0_[19][17] ),
.I1(\data_rw_o_reg_n_0_[18][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[17][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[16][17] ),
.O(\axi_rdata[17]_i_31_n_0 ));
LUT6 #(
@@ -6257,9 +6257,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_32
(.I0(\data_rw_o_reg_n_0_[23][17] ),
.I1(\data_rw_o_reg_n_0_[22][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[21][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[20][17] ),
.O(\axi_rdata[17]_i_32_n_0 ));
LUT5 #(
@@ -6267,18 +6267,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_33
(.I0(\data_rw_o_reg_n_0_[11][17] ),
.I1(\data_rw_o_reg_n_0_[10][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc1[0] [17]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[17]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[17]_i_34
(.I0(\data_rw_o_reg_n_0_[35][17] ),
.I1(\data_rw_o_reg_n_0_[34][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[33][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[32][17] ),
.O(\axi_rdata[17]_i_34_n_0 ));
LUT6 #(
@@ -6286,9 +6286,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_35
(.I0(\data_rw_o_reg_n_0_[91][17] ),
.I1(\data_rw_o_reg_n_0_[90][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[89][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[88][17] ),
.O(\axi_rdata[17]_i_35_n_0 ));
LUT6 #(
@@ -6296,9 +6296,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_36
(.I0(\data_rw_o_reg_n_0_[95][17] ),
.I1(\data_rw_o_reg_n_0_[94][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[93][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[92][17] ),
.O(\axi_rdata[17]_i_36_n_0 ));
LUT6 #(
@@ -6306,9 +6306,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_37
(.I0(\data_rw_o_reg_n_0_[87][17] ),
.I1(\data_rw_o_reg_n_0_[86][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[85][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[84][17] ),
.O(\axi_rdata[17]_i_37_n_0 ));
LUT5 #(
@@ -6316,18 +6316,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_39
(.I0(\data_rw_o_reg_n_0_[79][17] ),
.I1(\data_rw_o_reg_n_0_[78][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\s_datao_fmc2[0] [17]),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.O(\axi_rdata[17]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[17]_i_42
(.I0(\data_rw_o_reg_n_0_[99][17] ),
.I1(\data_rw_o_reg_n_0_[98][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[97][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[96][17] ),
.O(\axi_rdata[17]_i_42_n_0 ));
LUT6 #(
@@ -6335,9 +6335,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[17]_i_43
(.I0(\data_rw_o_reg_n_0_[103][17] ),
.I1(\data_rw_o_reg_n_0_[102][17] ),
- .I2(\axi_rdata_reg[17]_1 ),
+ .I2(\axi_rdata_reg[17]_0 ),
.I3(\data_rw_o_reg_n_0_[101][17] ),
- .I4(\axi_rdata_reg[17]_0 ),
+ .I4(\axi_rdata_reg[17]_1 ),
.I5(\data_rw_o_reg_n_0_[100][17] ),
.O(\axi_rdata[17]_i_43_n_0 ));
LUT6 #(
@@ -6393,29 +6393,29 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[18]_i_13
- (.I0(\axi_rdata_reg[22]_0 ),
+ (.I0(\axi_rdata_reg[22]_1 ),
.I1(\s_datao_fmc1[4] [10]),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\axi_rdata_reg[18]_0 ),
.I4(\axi_rdata[18]_i_33_n_0 ),
.O(\axi_rdata[18]_i_13_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
- .INIT(16'h0080))
+ .INIT(16'hC888))
\axi_rdata[18]_i_14
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\data_rw_o_reg_n_0_[3][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
+ (.I0(\axi_rdata_reg[18]_0 ),
+ .I1(\axi_rdata_reg[22]_0 ),
+ .I2(\data_rw_o_reg_n_0_[3][18] ),
+ .I3(\axi_rdata_reg[22]_1 ),
.O(\axi_rdata[18]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000000022222E22))
\axi_rdata[18]_i_17
(.I0(\axi_rdata[18]_i_34_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [18]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[18]_i_17_n_0 ));
LUT5 #(
@@ -6423,17 +6423,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_19
(.I0(\axi_rdata[18]_i_37_n_0 ),
.I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\s_datao_fmc2[4] [10]),
- .I4(\axi_rdata_reg[22]_1 ),
+ .I4(\axi_rdata_reg[22]_0 ),
.O(\axi_rdata[18]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[18]_i_23
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\dac_ch_o_reg[0][31] [18]),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\axi_rdata_reg[18]_0 ),
.O(\axi_rdata[18]_i_23_n_0 ));
LUT6 #(
@@ -6441,9 +6441,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_29
(.I0(\data_rw_o_reg_n_0_[27][18] ),
.I1(\data_rw_o_reg_n_0_[26][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[25][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[24][18] ),
.O(\axi_rdata[18]_i_29_n_0 ));
LUT6 #(
@@ -6451,9 +6451,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_30
(.I0(\data_rw_o_reg_n_0_[31][18] ),
.I1(\data_rw_o_reg_n_0_[30][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[29][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[28][18] ),
.O(\axi_rdata[18]_i_30_n_0 ));
LUT6 #(
@@ -6461,9 +6461,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_31
(.I0(\data_rw_o_reg_n_0_[19][18] ),
.I1(\data_rw_o_reg_n_0_[18][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[17][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[16][18] ),
.O(\axi_rdata[18]_i_31_n_0 ));
LUT6 #(
@@ -6471,9 +6471,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_32
(.I0(\data_rw_o_reg_n_0_[23][18] ),
.I1(\data_rw_o_reg_n_0_[22][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[21][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[20][18] ),
.O(\axi_rdata[18]_i_32_n_0 ));
LUT5 #(
@@ -6481,18 +6481,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_33
(.I0(\data_rw_o_reg_n_0_[11][18] ),
.I1(\data_rw_o_reg_n_0_[10][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\s_datao_fmc1[0] [18]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.O(\axi_rdata[18]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[18]_i_34
(.I0(\data_rw_o_reg_n_0_[35][18] ),
.I1(\data_rw_o_reg_n_0_[34][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[33][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[32][18] ),
.O(\axi_rdata[18]_i_34_n_0 ));
LUT6 #(
@@ -6500,9 +6500,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_35
(.I0(\data_rw_o_reg_n_0_[91][18] ),
.I1(\data_rw_o_reg_n_0_[90][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[89][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[88][18] ),
.O(\axi_rdata[18]_i_35_n_0 ));
LUT6 #(
@@ -6510,9 +6510,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_36
(.I0(\data_rw_o_reg_n_0_[95][18] ),
.I1(\data_rw_o_reg_n_0_[94][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[93][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[92][18] ),
.O(\axi_rdata[18]_i_36_n_0 ));
LUT6 #(
@@ -6520,9 +6520,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_37
(.I0(\data_rw_o_reg_n_0_[87][18] ),
.I1(\data_rw_o_reg_n_0_[86][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[85][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[84][18] ),
.O(\axi_rdata[18]_i_37_n_0 ));
LUT5 #(
@@ -6530,18 +6530,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_39
(.I0(\data_rw_o_reg_n_0_[79][18] ),
.I1(\data_rw_o_reg_n_0_[78][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\s_datao_fmc2[0] [18]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.O(\axi_rdata[18]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[18]_i_42
(.I0(\data_rw_o_reg_n_0_[99][18] ),
.I1(\data_rw_o_reg_n_0_[98][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[97][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[96][18] ),
.O(\axi_rdata[18]_i_42_n_0 ));
LUT6 #(
@@ -6549,9 +6549,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[18]_i_43
(.I0(\data_rw_o_reg_n_0_[103][18] ),
.I1(\data_rw_o_reg_n_0_[102][18] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[101][18] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[100][18] ),
.O(\axi_rdata[18]_i_43_n_0 ));
LUT6 #(
@@ -6607,29 +6607,29 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[19]_i_13
- (.I0(\axi_rdata_reg[22]_0 ),
+ (.I0(\axi_rdata_reg[22]_1 ),
.I1(\s_datao_fmc1[4] [11]),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\axi_rdata_reg[23]_0 [2]),
.I4(\axi_rdata[19]_i_33_n_0 ),
.O(\axi_rdata[19]_i_13_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hC888))
\axi_rdata[19]_i_14
(.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[22]_1 ),
+ .I1(\axi_rdata_reg[22]_0 ),
.I2(\data_rw_o_reg_n_0_[3][19] ),
- .I3(\axi_rdata_reg[22]_0 ),
+ .I3(\axi_rdata_reg[22]_1 ),
.O(\axi_rdata[19]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000000022222E22))
\axi_rdata[19]_i_17
(.I0(\axi_rdata[19]_i_34_n_0 ),
.I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [19]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[19]_i_17_n_0 ));
LUT5 #(
@@ -6637,17 +6637,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_19
(.I0(\axi_rdata[19]_i_37_n_0 ),
.I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\s_datao_fmc2[4] [11]),
- .I4(\axi_rdata_reg[22]_1 ),
+ .I4(\axi_rdata_reg[22]_0 ),
.O(\axi_rdata[19]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[19]_i_23
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\dac_ch_o_reg[0][31] [19]),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[19]_i_23_n_0 ));
LUT6 #(
@@ -6655,9 +6655,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_29
(.I0(\data_rw_o_reg_n_0_[27][19] ),
.I1(\data_rw_o_reg_n_0_[26][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[25][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[24][19] ),
.O(\axi_rdata[19]_i_29_n_0 ));
LUT6 #(
@@ -6665,9 +6665,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_30
(.I0(\data_rw_o_reg_n_0_[31][19] ),
.I1(\data_rw_o_reg_n_0_[30][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[29][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[28][19] ),
.O(\axi_rdata[19]_i_30_n_0 ));
LUT6 #(
@@ -6675,9 +6675,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_31
(.I0(\data_rw_o_reg_n_0_[19][19] ),
.I1(\data_rw_o_reg_n_0_[18][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[17][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[16][19] ),
.O(\axi_rdata[19]_i_31_n_0 ));
LUT6 #(
@@ -6685,9 +6685,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_32
(.I0(\data_rw_o_reg_n_0_[23][19] ),
.I1(\data_rw_o_reg_n_0_[22][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[21][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[20][19] ),
.O(\axi_rdata[19]_i_32_n_0 ));
LUT5 #(
@@ -6695,18 +6695,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_33
(.I0(\data_rw_o_reg_n_0_[11][19] ),
.I1(\data_rw_o_reg_n_0_[10][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\s_datao_fmc1[0] [19]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.O(\axi_rdata[19]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[19]_i_34
(.I0(\data_rw_o_reg_n_0_[35][19] ),
.I1(\data_rw_o_reg_n_0_[34][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[33][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[32][19] ),
.O(\axi_rdata[19]_i_34_n_0 ));
LUT6 #(
@@ -6714,9 +6714,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_35
(.I0(\data_rw_o_reg_n_0_[91][19] ),
.I1(\data_rw_o_reg_n_0_[90][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[89][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[88][19] ),
.O(\axi_rdata[19]_i_35_n_0 ));
LUT6 #(
@@ -6724,9 +6724,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_36
(.I0(\data_rw_o_reg_n_0_[95][19] ),
.I1(\data_rw_o_reg_n_0_[94][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[93][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[92][19] ),
.O(\axi_rdata[19]_i_36_n_0 ));
LUT6 #(
@@ -6734,9 +6734,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_37
(.I0(\data_rw_o_reg_n_0_[87][19] ),
.I1(\data_rw_o_reg_n_0_[86][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[85][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[84][19] ),
.O(\axi_rdata[19]_i_37_n_0 ));
LUT5 #(
@@ -6744,18 +6744,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_39
(.I0(\data_rw_o_reg_n_0_[79][19] ),
.I1(\data_rw_o_reg_n_0_[78][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\s_datao_fmc2[0] [19]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.O(\axi_rdata[19]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[19]_i_42
(.I0(\data_rw_o_reg_n_0_[99][19] ),
.I1(\data_rw_o_reg_n_0_[98][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[97][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[96][19] ),
.O(\axi_rdata[19]_i_42_n_0 ));
LUT6 #(
@@ -6763,9 +6763,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[19]_i_43
(.I0(\data_rw_o_reg_n_0_[103][19] ),
.I1(\data_rw_o_reg_n_0_[102][19] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[101][19] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[100][19] ),
.O(\axi_rdata[19]_i_43_n_0 ));
LUT6 #(
@@ -6819,7 +6819,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_araddr_reg[5]_rep_9 ),
.O(\axi_rdata[1]_i_1_n_0 ));
LUT6 #(
- .INIT(64'h4455FA004400FA00))
+ .INIT(64'hEE555000EE005000))
\axi_rdata[1]_i_14
(.I0(\axi_rdata_reg[9]_0 ),
.I1(\data_rw_o[3] [1]),
@@ -6838,7 +6838,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[2]_1 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[1]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[1]_i_23
@@ -7017,13 +7017,13 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[23]_0 [3]),
.I5(\axi_araddr_reg[4]_8 ),
.O(\axi_rdata[20]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[20]_i_14
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\dac_ch_o_reg[0][31] [20]),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[20]_i_14_n_0 ));
LUT6 #(
@@ -7060,37 +7060,37 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_20
(.I0(\axi_rdata[20]_i_34_n_0 ),
.I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [20]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[20]_i_20_n_0 ));
LUT5 #(
.INIT(32'h0000B800))
\axi_rdata[20]_i_23
(.I0(\data_rw_o_reg_n_0_[11][20] ),
- .I1(\axi_rdata_reg[22]_0 ),
+ .I1(\axi_rdata_reg[22]_1 ),
.I2(\data_rw_o_reg_n_0_[10][20] ),
- .I3(\axi_rdata_reg[22]_1 ),
+ .I3(\axi_rdata_reg[22]_0 ),
.I4(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[20]_i_23_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
- .INIT(16'hC800))
+ .INIT(16'h0080))
\axi_rdata[20]_i_24
- (.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[22]_1 ),
- .I2(\data_rw_o_reg_n_0_[3][20] ),
- .I3(\axi_rdata_reg[22]_0 ),
+ (.I0(\axi_rdata_reg[22]_1 ),
+ .I1(\data_rw_o_reg_n_0_[3][20] ),
+ .I2(\axi_rdata_reg[22]_0 ),
+ .I3(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[20]_i_24_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[20]_i_25
(.I0(\data_rw_o_reg_n_0_[99][20] ),
.I1(\data_rw_o_reg_n_0_[98][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[97][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[96][20] ),
.O(\axi_rdata[20]_i_25_n_0 ));
LUT6 #(
@@ -7098,17 +7098,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_26
(.I0(\data_rw_o_reg_n_0_[103][20] ),
.I1(\data_rw_o_reg_n_0_[102][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[101][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[100][20] ),
.O(\axi_rdata[20]_i_26_n_0 ));
LUT4 #(
.INIT(16'hA808))
\axi_rdata[20]_i_27
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\data_rw_o_reg_n_0_[78][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\data_rw_o_reg_n_0_[79][20] ),
.O(\axi_rdata[20]_i_27_n_0 ));
LUT6 #(
@@ -7116,9 +7116,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_31
(.I0(\data_rw_o_reg_n_0_[95][20] ),
.I1(\data_rw_o_reg_n_0_[94][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[93][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[92][20] ),
.O(\axi_rdata[20]_i_31_n_0 ));
LUT6 #(
@@ -7126,9 +7126,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_32
(.I0(\data_rw_o_reg_n_0_[91][20] ),
.I1(\data_rw_o_reg_n_0_[90][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[89][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[88][20] ),
.O(\axi_rdata[20]_i_32_n_0 ));
LUT6 #(
@@ -7136,9 +7136,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_33
(.I0(\data_rw_o_reg_n_0_[87][20] ),
.I1(\data_rw_o_reg_n_0_[86][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[85][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[84][20] ),
.O(\axi_rdata[20]_i_33_n_0 ));
LUT6 #(
@@ -7146,9 +7146,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_34
(.I0(\data_rw_o_reg_n_0_[35][20] ),
.I1(\data_rw_o_reg_n_0_[34][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[33][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[32][20] ),
.O(\axi_rdata[20]_i_34_n_0 ));
LUT6 #(
@@ -7156,9 +7156,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_35
(.I0(\data_rw_o_reg_n_0_[27][20] ),
.I1(\data_rw_o_reg_n_0_[26][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[25][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[24][20] ),
.O(\axi_rdata[20]_i_35_n_0 ));
LUT6 #(
@@ -7166,9 +7166,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_36
(.I0(\data_rw_o_reg_n_0_[31][20] ),
.I1(\data_rw_o_reg_n_0_[30][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[29][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[28][20] ),
.O(\axi_rdata[20]_i_36_n_0 ));
LUT6 #(
@@ -7176,9 +7176,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_37
(.I0(\data_rw_o_reg_n_0_[19][20] ),
.I1(\data_rw_o_reg_n_0_[18][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[17][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[16][20] ),
.O(\axi_rdata[20]_i_37_n_0 ));
LUT6 #(
@@ -7186,9 +7186,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[20]_i_38
(.I0(\data_rw_o_reg_n_0_[23][20] ),
.I1(\data_rw_o_reg_n_0_[22][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[21][20] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[20][20] ),
.O(\axi_rdata[20]_i_38_n_0 ));
LUT6 #(
@@ -7231,13 +7231,13 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[23]_0 [3]),
.I5(\axi_araddr_reg[4]_6 ),
.O(\axi_rdata[21]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[21]_i_14
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\dac_ch_o_reg[0][31] [21]),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[21]_i_14_n_0 ));
LUT6 #(
@@ -7274,37 +7274,37 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_20
(.I0(\axi_rdata[21]_i_34_n_0 ),
.I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [21]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[21]_i_20_n_0 ));
LUT5 #(
.INIT(32'h0000B800))
\axi_rdata[21]_i_23
(.I0(\data_rw_o_reg_n_0_[11][21] ),
- .I1(\axi_rdata_reg[22]_0 ),
+ .I1(\axi_rdata_reg[22]_1 ),
.I2(\data_rw_o_reg_n_0_[10][21] ),
- .I3(\axi_rdata_reg[22]_1 ),
+ .I3(\axi_rdata_reg[22]_0 ),
.I4(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[21]_i_23_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
- .INIT(16'hC800))
+ .INIT(16'hC888))
\axi_rdata[21]_i_24
(.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[22]_1 ),
+ .I1(\axi_rdata_reg[22]_0 ),
.I2(\data_rw_o_reg_n_0_[3][21] ),
- .I3(\axi_rdata_reg[22]_0 ),
+ .I3(\axi_rdata_reg[22]_1 ),
.O(\axi_rdata[21]_i_24_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[21]_i_25
(.I0(\data_rw_o_reg_n_0_[99][21] ),
.I1(\data_rw_o_reg_n_0_[98][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[97][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[96][21] ),
.O(\axi_rdata[21]_i_25_n_0 ));
LUT6 #(
@@ -7312,17 +7312,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_26
(.I0(\data_rw_o_reg_n_0_[103][21] ),
.I1(\data_rw_o_reg_n_0_[102][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[101][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[100][21] ),
.O(\axi_rdata[21]_i_26_n_0 ));
LUT4 #(
.INIT(16'hA808))
\axi_rdata[21]_i_27
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\data_rw_o_reg_n_0_[78][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\data_rw_o_reg_n_0_[79][21] ),
.O(\axi_rdata[21]_i_27_n_0 ));
LUT6 #(
@@ -7330,9 +7330,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_31
(.I0(\data_rw_o_reg_n_0_[95][21] ),
.I1(\data_rw_o_reg_n_0_[94][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[93][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[92][21] ),
.O(\axi_rdata[21]_i_31_n_0 ));
LUT6 #(
@@ -7340,9 +7340,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_32
(.I0(\data_rw_o_reg_n_0_[91][21] ),
.I1(\data_rw_o_reg_n_0_[90][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[89][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[88][21] ),
.O(\axi_rdata[21]_i_32_n_0 ));
LUT6 #(
@@ -7350,9 +7350,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_33
(.I0(\data_rw_o_reg_n_0_[87][21] ),
.I1(\data_rw_o_reg_n_0_[86][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[85][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[84][21] ),
.O(\axi_rdata[21]_i_33_n_0 ));
LUT6 #(
@@ -7360,9 +7360,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_34
(.I0(\data_rw_o_reg_n_0_[35][21] ),
.I1(\data_rw_o_reg_n_0_[34][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[33][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[32][21] ),
.O(\axi_rdata[21]_i_34_n_0 ));
LUT6 #(
@@ -7370,9 +7370,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_35
(.I0(\data_rw_o_reg_n_0_[27][21] ),
.I1(\data_rw_o_reg_n_0_[26][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[25][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[24][21] ),
.O(\axi_rdata[21]_i_35_n_0 ));
LUT6 #(
@@ -7380,9 +7380,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_36
(.I0(\data_rw_o_reg_n_0_[31][21] ),
.I1(\data_rw_o_reg_n_0_[30][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[29][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[28][21] ),
.O(\axi_rdata[21]_i_36_n_0 ));
LUT6 #(
@@ -7390,9 +7390,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_37
(.I0(\data_rw_o_reg_n_0_[19][21] ),
.I1(\data_rw_o_reg_n_0_[18][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[17][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[16][21] ),
.O(\axi_rdata[21]_i_37_n_0 ));
LUT6 #(
@@ -7400,9 +7400,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[21]_i_38
(.I0(\data_rw_o_reg_n_0_[23][21] ),
.I1(\data_rw_o_reg_n_0_[22][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[21][21] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[20][21] ),
.O(\axi_rdata[21]_i_38_n_0 ));
LUT6 #(
@@ -7445,13 +7445,13 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[23]_0 [3]),
.I5(\axi_araddr_reg[4]_4 ),
.O(\axi_rdata[22]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[22]_i_14
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\dac_ch_o_reg[0][31] [22]),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[22]_i_14_n_0 ));
LUT6 #(
@@ -7488,37 +7488,37 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_20
(.I0(\axi_rdata[22]_i_34_n_0 ),
.I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\dac_ch_o_reg[0][31]_0 [22]),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[22]_i_20_n_0 ));
LUT5 #(
.INIT(32'h0000B800))
\axi_rdata[22]_i_23
(.I0(\data_rw_o_reg_n_0_[11][22] ),
- .I1(\axi_rdata_reg[22]_0 ),
+ .I1(\axi_rdata_reg[22]_1 ),
.I2(\data_rw_o_reg_n_0_[10][22] ),
- .I3(\axi_rdata_reg[22]_1 ),
+ .I3(\axi_rdata_reg[22]_0 ),
.I4(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[22]_i_23_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
- .INIT(16'h4088))
+ .INIT(16'h0080))
\axi_rdata[22]_i_24
- (.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[22]_1 ),
- .I2(\data_rw_o_reg_n_0_[3][22] ),
- .I3(\axi_rdata_reg[22]_0 ),
+ (.I0(\axi_rdata_reg[22]_1 ),
+ .I1(\data_rw_o_reg_n_0_[3][22] ),
+ .I2(\axi_rdata_reg[22]_0 ),
+ .I3(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[22]_i_24_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[22]_i_25
(.I0(\data_rw_o_reg_n_0_[99][22] ),
.I1(\data_rw_o_reg_n_0_[98][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[97][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[96][22] ),
.O(\axi_rdata[22]_i_25_n_0 ));
LUT6 #(
@@ -7526,17 +7526,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_26
(.I0(\data_rw_o_reg_n_0_[103][22] ),
.I1(\data_rw_o_reg_n_0_[102][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[101][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[100][22] ),
.O(\axi_rdata[22]_i_26_n_0 ));
LUT4 #(
.INIT(16'hA808))
\axi_rdata[22]_i_27
- (.I0(\axi_rdata_reg[22]_1 ),
+ (.I0(\axi_rdata_reg[22]_0 ),
.I1(\data_rw_o_reg_n_0_[78][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
+ .I2(\axi_rdata_reg[22]_1 ),
.I3(\data_rw_o_reg_n_0_[79][22] ),
.O(\axi_rdata[22]_i_27_n_0 ));
LUT6 #(
@@ -7544,9 +7544,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_31
(.I0(\data_rw_o_reg_n_0_[95][22] ),
.I1(\data_rw_o_reg_n_0_[94][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[93][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[92][22] ),
.O(\axi_rdata[22]_i_31_n_0 ));
LUT6 #(
@@ -7554,9 +7554,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_32
(.I0(\data_rw_o_reg_n_0_[91][22] ),
.I1(\data_rw_o_reg_n_0_[90][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[89][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[88][22] ),
.O(\axi_rdata[22]_i_32_n_0 ));
LUT6 #(
@@ -7564,9 +7564,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_33
(.I0(\data_rw_o_reg_n_0_[87][22] ),
.I1(\data_rw_o_reg_n_0_[86][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[85][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[84][22] ),
.O(\axi_rdata[22]_i_33_n_0 ));
LUT6 #(
@@ -7574,9 +7574,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_34
(.I0(\data_rw_o_reg_n_0_[35][22] ),
.I1(\data_rw_o_reg_n_0_[34][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[33][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[32][22] ),
.O(\axi_rdata[22]_i_34_n_0 ));
LUT6 #(
@@ -7584,9 +7584,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_35
(.I0(\data_rw_o_reg_n_0_[27][22] ),
.I1(\data_rw_o_reg_n_0_[26][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[25][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[24][22] ),
.O(\axi_rdata[22]_i_35_n_0 ));
LUT6 #(
@@ -7594,9 +7594,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_36
(.I0(\data_rw_o_reg_n_0_[31][22] ),
.I1(\data_rw_o_reg_n_0_[30][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[29][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[28][22] ),
.O(\axi_rdata[22]_i_36_n_0 ));
LUT6 #(
@@ -7604,9 +7604,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_37
(.I0(\data_rw_o_reg_n_0_[19][22] ),
.I1(\data_rw_o_reg_n_0_[18][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[17][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[16][22] ),
.O(\axi_rdata[22]_i_37_n_0 ));
LUT6 #(
@@ -7614,9 +7614,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[22]_i_38
(.I0(\data_rw_o_reg_n_0_[23][22] ),
.I1(\data_rw_o_reg_n_0_[22][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
+ .I2(\axi_rdata_reg[22]_0 ),
.I3(\data_rw_o_reg_n_0_[21][22] ),
- .I4(\axi_rdata_reg[22]_0 ),
+ .I4(\axi_rdata_reg[22]_1 ),
.I5(\data_rw_o_reg_n_0_[20][22] ),
.O(\axi_rdata[22]_i_38_n_0 ));
LUT6 #(
@@ -7659,7 +7659,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[23]_0 [3]),
.I5(\axi_araddr_reg[4]_2 ),
.O(\axi_rdata[23]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[23]_i_15
@@ -7714,14 +7714,14 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I3(\axi_rdata_reg[23]_0 [1]),
.I4(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[23]_i_24_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
- .INIT(16'h0080))
+ .INIT(16'hC888))
\axi_rdata[23]_i_25
- (.I0(\axi_rdata_reg[23]_0 [0]),
- .I1(\data_rw_o_reg_n_0_[3][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\axi_rdata_reg[23]_0 [2]),
+ (.I0(\axi_rdata_reg[23]_0 [2]),
+ .I1(\axi_rdata_reg[23]_0 [1]),
+ .I2(\data_rw_o_reg_n_0_[3][23] ),
+ .I3(\axi_rdata_reg[23]_0 [0]),
.O(\axi_rdata[23]_i_25_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
@@ -8046,14 +8046,14 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[24]_i_7_n_0 ));
LUT6 #(
- .INIT(64'hBB88B888B888B888))
+ .INIT(64'h88888888B8888888))
\axi_rdata[24]_i_9
(.I0(\axi_rdata[24]_i_17_n_0 ),
.I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][24] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
+ .I2(\axi_rdata_reg[23]_0 [0]),
+ .I3(\data_rw_o_reg_n_0_[3][24] ),
+ .I4(\axi_rdata_reg[23]_0 [1]),
+ .I5(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[24]_i_9_n_0 ));
LUT4 #(
.INIT(16'h4540))
@@ -8230,7 +8230,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[25]_i_7_n_0 ));
LUT6 #(
- .INIT(64'hBB88B88888888888))
+ .INIT(64'hBB88B888B888B888))
\axi_rdata[25]_i_9
(.I0(\axi_rdata[25]_i_17_n_0 ),
.I1(\axi_rdata_reg[23]_0 [3]),
@@ -8414,7 +8414,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[26]_i_7_n_0 ));
LUT6 #(
- .INIT(64'hBB88B88888888888))
+ .INIT(64'hBB88B888B888B888))
\axi_rdata[26]_i_9
(.I0(\axi_rdata[26]_i_17_n_0 ),
.I1(\axi_rdata_reg[23]_0 [3]),
@@ -8782,7 +8782,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[28]_i_7_n_0 ));
LUT6 #(
- .INIT(64'h8B888888B888B888))
+ .INIT(64'hBB88B888B888B888))
\axi_rdata[28]_i_9
(.I0(\axi_rdata[28]_i_17_n_0 ),
.I1(\axi_rdata_reg[23]_0 [3]),
@@ -8966,14 +8966,14 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[29]_i_7_n_0 ));
LUT6 #(
- .INIT(64'hBB88B88888888888))
+ .INIT(64'h88888888B8888888))
\axi_rdata[29]_i_9
(.I0(\axi_rdata[29]_i_17_n_0 ),
.I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][29] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
+ .I2(\axi_rdata_reg[23]_0 [0]),
+ .I3(\data_rw_o_reg_n_0_[3][29] ),
+ .I4(\axi_rdata_reg[23]_0 [1]),
+ .I5(\axi_rdata_reg[23]_0 [2]),
.O(\axi_rdata[29]_i_9_n_0 ));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
@@ -8986,14 +8986,14 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_araddr_reg[5]_rep_8 ),
.O(\axi_rdata[2]_i_1_n_0 ));
LUT6 #(
- .INIT(64'h4455FA004400FA00))
+ .INIT(64'h00000000F8C83808))
\axi_rdata[2]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
- .I1(\data_rw_o_reg_n_0_[3][2] ),
- .I2(gem_status_vector_i[2]),
- .I3(\axi_rdata_reg[2]_0 ),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_ins_reg[3] [2]),
+ (.I0(\s_ins_reg[3] [2]),
+ .I1(\axi_rdata_reg[2]_1 ),
+ .I2(\axi_rdata_reg[2]_0 ),
+ .I3(gem_status_vector_i[2]),
+ .I4(\data_rw_o_reg_n_0_[3][2] ),
+ .I5(\axi_rdata_reg[9]_0 ),
.O(\axi_rdata[2]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000000022222E22))
@@ -9005,7 +9005,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[2]_1 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[2]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[2]_i_23
@@ -9349,7 +9349,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_rdata_reg[23]_0 [3]),
.O(\axi_rdata[30]_i_7_n_0 ));
LUT6 #(
- .INIT(64'h8B888888B888B888))
+ .INIT(64'hBB88B888B888B888))
\axi_rdata[30]_i_9
(.I0(\axi_rdata[30]_i_17_n_0 ),
.I1(\axi_rdata_reg[23]_0 [3]),
@@ -9366,14 +9366,14 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I2(s00_axi_rvalid),
.O(\axi_rdata[31]_i_1_n_0 ));
LUT6 #(
- .INIT(64'h88888888B8888888))
+ .INIT(64'hBB88B888B888B888))
\axi_rdata[31]_i_10
(.I0(\axi_rdata[31]_i_18_n_0 ),
.I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\data_rw_o_reg_n_0_[3][31] ),
- .I4(\axi_rdata_reg[23]_0 [1]),
- .I5(\axi_rdata_reg[23]_0 [2]),
+ .I2(\axi_rdata_reg[23]_0 [2]),
+ .I3(\axi_rdata_reg[23]_0 [1]),
+ .I4(\data_rw_o_reg_n_0_[3][31] ),
+ .I5(\axi_rdata_reg[23]_0 [0]),
.O(\axi_rdata[31]_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
@@ -9579,7 +9579,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[7]_1 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[3]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[3]_i_23
@@ -9777,7 +9777,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[7]_1 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[4]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[4]_i_23
@@ -9955,7 +9955,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_araddr_reg[5]_rep_5 ),
.O(\axi_rdata[5]_i_1_n_0 ));
LUT5 #(
- .INIT(32'h44C800C8))
+ .INIT(32'hCCC888C8))
\axi_rdata[5]_i_14
(.I0(\axi_rdata_reg[9]_0 ),
.I1(\axi_rdata_reg[7]_0 ),
@@ -9973,7 +9973,6 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[7]_1 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[5]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[5]_i_23
@@ -10151,7 +10150,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_araddr_reg[5]_rep_4 ),
.O(\axi_rdata[6]_i_1_n_0 ));
LUT5 #(
- .INIT(32'hCC408840))
+ .INIT(32'hCCC888C8))
\axi_rdata[6]_i_14
(.I0(\axi_rdata_reg[9]_0 ),
.I1(\axi_rdata_reg[7]_0 ),
@@ -10169,6 +10168,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata_reg[7]_1 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[6]_i_17_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[6]_i_23
@@ -10346,7 +10346,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I5(\axi_araddr_reg[5]_rep_3 ),
.O(\axi_rdata[7]_i_1_n_0 ));
LUT5 #(
- .INIT(32'hCC408840))
+ .INIT(32'hCCC888C8))
\axi_rdata[7]_i_14
(.I0(\axi_rdata_reg[9]_0 ),
.I1(\axi_rdata_reg[7]_0 ),
@@ -10544,29 +10544,29 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[8]_i_13
- (.I0(\axi_rdata_reg[12]_1 ),
+ (.I0(\axi_rdata_reg[12]_0 ),
.I1(\s_datao_fmc1[4] [0]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\axi_rdata_reg[9]_0 ),
.I4(\axi_rdata[8]_i_33_n_0 ),
.O(\axi_rdata[8]_i_13_n_0 ));
LUT5 #(
- .INIT(32'h44C800C8))
+ .INIT(32'h0000B800))
\axi_rdata[8]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
+ (.I0(\data_rw_o_reg_n_0_[3][8] ),
.I1(\axi_rdata_reg[12]_0 ),
.I2(gem_status_vector_i[8]),
.I3(\axi_rdata_reg[12]_1 ),
- .I4(\data_rw_o_reg_n_0_[3][8] ),
+ .I4(\axi_rdata_reg[9]_0 ),
.O(\axi_rdata[8]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000000022222E22))
\axi_rdata[8]_i_17
(.I0(\axi_rdata[8]_i_34_n_0 ),
.I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\dac_ch_o_reg[0][31]_0 [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[8]_i_17_n_0 ));
LUT5 #(
@@ -10574,17 +10574,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_19
(.I0(\axi_rdata[8]_i_37_n_0 ),
.I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\s_datao_fmc2[4] [0]),
- .I4(\axi_rdata_reg[12]_0 ),
+ .I4(\axi_rdata_reg[12]_1 ),
.O(\axi_rdata[8]_i_19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[8]_i_23
- (.I0(\axi_rdata_reg[12]_0 ),
+ (.I0(\axi_rdata_reg[12]_1 ),
.I1(\dac_ch_o_reg[0][31] [8]),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\axi_rdata_reg[9]_0 ),
.O(\axi_rdata[8]_i_23_n_0 ));
LUT6 #(
@@ -10592,9 +10592,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_29
(.I0(\[2].[3].s_reqs_reg[11][value][11] [8]),
.I1(\[2].[2].s_reqs_reg[10][value][11] [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11] [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11] [8]),
.O(\axi_rdata[8]_i_29_n_0 ));
LUT6 #(
@@ -10602,9 +10602,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_30
(.I0(\[3].[3].s_reqs_reg[15][value][11] [8]),
.I1(\[3].[2].s_reqs_reg[14][value][11] [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11] [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11] [8]),
.O(\axi_rdata[8]_i_30_n_0 ));
LUT6 #(
@@ -10612,9 +10612,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_31
(.I0(Q[8]),
.I1(\[0].[2].s_reqs_reg[2][value][11] [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11] [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11] [8]),
.O(\axi_rdata[8]_i_31_n_0 ));
LUT6 #(
@@ -10622,9 +10622,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_32
(.I0(\[1].[3].s_reqs_reg[7][value][11] [8]),
.I1(\[1].[2].s_reqs_reg[6][value][11] [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11] [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11] [8]),
.O(\axi_rdata[8]_i_32_n_0 ));
LUT5 #(
@@ -10632,18 +10632,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_33
(.I0(\data_rw_o_reg_n_0_[11][8] ),
.I1(\data_rw_o_reg_n_0_[10][8] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc1[0] [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[8]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[8]_i_34
(.I0(\[4].[3].s_reqs_reg[19][value][11] [8]),
.I1(\[4].[2].s_reqs_reg[18][value][11] [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11] [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11] [8]),
.O(\axi_rdata[8]_i_34_n_0 ));
LUT6 #(
@@ -10651,9 +10651,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_35
(.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [8]),
.I1(\[1].[2].s_reqs_reg[6][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11]_0 [8]),
.O(\axi_rdata[8]_i_35_n_0 ));
LUT6 #(
@@ -10661,9 +10661,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_36
(.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [8]),
.I1(\[2].[2].s_reqs_reg[10][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11]_0 [8]),
.O(\axi_rdata[8]_i_36_n_0 ));
LUT6 #(
@@ -10671,9 +10671,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_37
(.I0(\[0].[3].s_reqs_reg[3][value][11] [8]),
.I1(\[0].[2].s_reqs_reg[2][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11]_0 [8]),
.O(\axi_rdata[8]_i_37_n_0 ));
LUT5 #(
@@ -10681,18 +10681,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_39
(.I0(\data_rw_o_reg_n_0_[79][8] ),
.I1(\data_rw_o_reg_n_0_[78][8] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc2[0] [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[8]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[8]_i_42
(.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [8]),
.I1(\[3].[2].s_reqs_reg[14][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11]_0 [8]),
.O(\axi_rdata[8]_i_42_n_0 ));
LUT6 #(
@@ -10700,9 +10700,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[8]_i_43
(.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [8]),
.I1(\[4].[2].s_reqs_reg[18][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11]_0 [8]),
.O(\axi_rdata[8]_i_43_n_0 ));
LUT6 #(
@@ -10758,19 +10758,19 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
LUT5 #(
.INIT(32'h04FF0400))
\axi_rdata[9]_i_13
- (.I0(\axi_rdata_reg[12]_1 ),
+ (.I0(\axi_rdata_reg[12]_0 ),
.I1(\s_datao_fmc1[4] [1]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\axi_rdata_reg[9]_0 ),
.I4(\axi_rdata[9]_i_33_n_0 ),
.O(\axi_rdata[9]_i_13_n_0 ));
LUT5 #(
- .INIT(32'h44C800C8))
+ .INIT(32'hCCC888C8))
\axi_rdata[9]_i_14
(.I0(\axi_rdata_reg[9]_0 ),
- .I1(\axi_rdata_reg[12]_0 ),
+ .I1(\axi_rdata_reg[12]_1 ),
.I2(gem_status_vector_i[9]),
- .I3(\axi_rdata_reg[12]_1 ),
+ .I3(\axi_rdata_reg[12]_0 ),
.I4(\data_rw_o_reg_n_0_[3][9] ),
.O(\axi_rdata[9]_i_14_n_0 ));
LUT6 #(
@@ -10778,9 +10778,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_17
(.I0(\axi_rdata[9]_i_34_n_0 ),
.I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\dac_ch_o_reg[0][31]_0 [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\axi_rdata_reg[10]_0 ),
.O(\axi_rdata[9]_i_17_n_0 ));
LUT5 #(
@@ -10788,17 +10788,17 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_19
(.I0(\axi_rdata[9]_i_37_n_0 ),
.I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\s_datao_fmc2[4] [1]),
- .I4(\axi_rdata_reg[12]_0 ),
+ .I4(\axi_rdata_reg[12]_1 ),
.O(\axi_rdata[9]_i_19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0004))
\axi_rdata[9]_i_23
- (.I0(\axi_rdata_reg[12]_0 ),
+ (.I0(\axi_rdata_reg[12]_1 ),
.I1(\dac_ch_o_reg[0][31] [9]),
- .I2(\axi_rdata_reg[12]_1 ),
+ .I2(\axi_rdata_reg[12]_0 ),
.I3(\axi_rdata_reg[9]_0 ),
.O(\axi_rdata[9]_i_23_n_0 ));
LUT6 #(
@@ -10806,9 +10806,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_29
(.I0(\[2].[3].s_reqs_reg[11][value][11] [9]),
.I1(\[2].[2].s_reqs_reg[10][value][11] [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11] [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11] [9]),
.O(\axi_rdata[9]_i_29_n_0 ));
LUT6 #(
@@ -10816,9 +10816,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_30
(.I0(\[3].[3].s_reqs_reg[15][value][11] [9]),
.I1(\[3].[2].s_reqs_reg[14][value][11] [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11] [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11] [9]),
.O(\axi_rdata[9]_i_30_n_0 ));
LUT6 #(
@@ -10826,9 +10826,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_31
(.I0(Q[9]),
.I1(\[0].[2].s_reqs_reg[2][value][11] [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11] [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11] [9]),
.O(\axi_rdata[9]_i_31_n_0 ));
LUT6 #(
@@ -10836,9 +10836,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_32
(.I0(\[1].[3].s_reqs_reg[7][value][11] [9]),
.I1(\[1].[2].s_reqs_reg[6][value][11] [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11] [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11] [9]),
.O(\axi_rdata[9]_i_32_n_0 ));
LUT5 #(
@@ -10846,18 +10846,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_33
(.I0(\data_rw_o_reg_n_0_[11][9] ),
.I1(\data_rw_o_reg_n_0_[10][9] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc1[0] [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[9]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[9]_i_34
(.I0(\[4].[3].s_reqs_reg[19][value][11] [9]),
.I1(\[4].[2].s_reqs_reg[18][value][11] [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11] [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11] [9]),
.O(\axi_rdata[9]_i_34_n_0 ));
LUT6 #(
@@ -10865,9 +10865,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_35
(.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [9]),
.I1(\[1].[2].s_reqs_reg[6][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[1].[1].s_reqs_reg[5][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[1].[0].s_reqs_reg[4][value][11]_0 [9]),
.O(\axi_rdata[9]_i_35_n_0 ));
LUT6 #(
@@ -10875,9 +10875,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_36
(.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [9]),
.I1(\[2].[2].s_reqs_reg[10][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[2].[1].s_reqs_reg[9][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[2].[0].s_reqs_reg[8][value][11]_0 [9]),
.O(\axi_rdata[9]_i_36_n_0 ));
LUT6 #(
@@ -10885,9 +10885,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_37
(.I0(\[0].[3].s_reqs_reg[3][value][11] [9]),
.I1(\[0].[2].s_reqs_reg[2][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[0].[1].s_reqs_reg[1][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[0].[0].s_reqs_reg[0][value][11]_0 [9]),
.O(\axi_rdata[9]_i_37_n_0 ));
LUT5 #(
@@ -10895,18 +10895,18 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_39
(.I0(\data_rw_o_reg_n_0_[79][9] ),
.I1(\data_rw_o_reg_n_0_[78][9] ),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\s_datao_fmc2[0] [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.O(\axi_rdata[9]_i_39_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axi_rdata[9]_i_42
(.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [9]),
.I1(\[3].[2].s_reqs_reg[14][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[3].[1].s_reqs_reg[13][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[3].[0].s_reqs_reg[12][value][11]_0 [9]),
.O(\axi_rdata[9]_i_42_n_0 ));
LUT6 #(
@@ -10914,9 +10914,9 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
\axi_rdata[9]_i_43
(.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [9]),
.I1(\[4].[2].s_reqs_reg[18][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_0 ),
+ .I2(\axi_rdata_reg[12]_1 ),
.I3(\[4].[1].s_reqs_reg[17][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_1 ),
+ .I4(\axi_rdata_reg[12]_0 ),
.I5(\[4].[0].s_reqs_reg[16][value][11]_0 [9]),
.O(\axi_rdata[9]_i_43_n_0 ));
LUT6 #(
@@ -12181,7 +12181,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\axi_rdata[23]_i_2_n_0 ),
.I5(s00_axi_aresetn),
.O(\axi_rresp[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h8))
\axi_rresp[1]_i_2
@@ -12194,7 +12194,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.D(\axi_rresp[1]_i_1_n_0 ),
.Q(s00_axi_rresp),
.R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h08F8))
axi_rvalid_i_1
@@ -12368,7 +12368,6 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\data_rw_o[103][31]_i_3_n_0 ),
.I5(\data_rw_o[97][31]_i_3_n_0 ),
.O(\data_rw_o[103][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[103][31]_i_3
@@ -12489,7 +12488,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[1]),
.I5(\data_rw_o[16][31]_i_3_n_0 ),
.O(\data_rw_o[16][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hFFFE))
\data_rw_o[16][31]_i_3
@@ -12536,7 +12535,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[4]),
.I5(\data_rw_o[17][31]_i_3_n_0 ),
.O(\data_rw_o[17][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hFFFE))
\data_rw_o[17][31]_i_3
@@ -12621,7 +12620,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[1]),
.I5(\data_rw_o[19][31]_i_3_n_0 ),
.O(\data_rw_o[19][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hFFFE))
\data_rw_o[19][31]_i_3
@@ -12782,7 +12781,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[3]),
.I5(sel0[5]),
.O(\data_rw_o[23][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[23][31]_i_3
@@ -12796,7 +12795,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.I0(sel0[1]),
.I1(sel0[0]),
.O(\data_rw_o[23][31]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[23][31]_i_5
@@ -13107,7 +13106,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[4]),
.I5(sel0[5]),
.O(\data_rw_o[31][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h7FFF))
\data_rw_o[31][31]_i_3
@@ -13161,7 +13160,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
(.I0(sel0[3]),
.I1(sel0[2]),
.O(\data_rw_o[32][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[32][31]_i_4
@@ -13206,7 +13205,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[4]),
.I5(sel0[1]),
.O(\data_rw_o[33][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[33][31]_i_3
@@ -13289,7 +13288,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\data_rw_o[23][31]_i_5_n_0 ),
.I5(\data_rw_o[35][31]_i_3_n_0 ),
.O(\data_rw_o[35][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[35][31]_i_3
@@ -13373,7 +13372,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I3(s00_axi_wvalid),
.I4(s00_axi_awvalid),
.O(\data_rw_o[0]1 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'hFFFE))
\data_rw_o[3][31]_i_7
@@ -13420,21 +13419,21 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[0]),
.I5(\data_rw_o[78][31]_i_5_n_0 ),
.O(\data_rw_o[78][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[78][31]_i_3
(.I0(sel0[6]),
.I1(sel0[2]),
.O(\data_rw_o[78][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[78][31]_i_4
(.I0(sel0[1]),
.I1(sel0[3]),
.O(\data_rw_o[78][31]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[78][31]_i_5
@@ -13564,7 +13563,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[1]),
.I5(sel0[5]),
.O(\data_rw_o[85][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[85][31]_i_3
@@ -13616,6 +13615,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\data_rw_o[85][31]_i_4_n_0 ),
.I5(\data_rw_o[86][31]_i_3_n_0 ),
.O(\data_rw_o[86][31]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[86][31]_i_3
@@ -13660,7 +13660,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\data_rw_o[85][31]_i_4_n_0 ),
.I5(\data_rw_o[87][31]_i_3_n_0 ),
.O(\data_rw_o[87][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'hB))
\data_rw_o[87][31]_i_3
@@ -13705,7 +13705,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[3]),
.I5(\data_rw_o[88][31]_i_3_n_0 ),
.O(\data_rw_o[88][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hFFFE))
\data_rw_o[88][31]_i_3
@@ -13752,14 +13752,14 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(\data_rw_o[89][31]_i_3_n_0 ),
.I5(\data_rw_o[89][31]_i_4_n_0 ),
.O(\data_rw_o[89][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[89][31]_i_3
(.I0(sel0[2]),
.I1(sel0[7]),
.O(\data_rw_o[89][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'hE))
\data_rw_o[89][31]_i_4
@@ -13918,7 +13918,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[1]),
.I5(\data_rw_o[87][31]_i_3_n_0 ),
.O(\data_rw_o[93][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[93][31]_i_3
@@ -13963,7 +13963,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[0]),
.I5(\data_rw_o[87][31]_i_3_n_0 ),
.O(\data_rw_o[94][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[94][31]_i_3
@@ -14046,7 +14046,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[6]),
.I5(\data_rw_o[96][31]_i_3_n_0 ),
.O(\data_rw_o[96][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hFFFE))
\data_rw_o[96][31]_i_3
@@ -14093,7 +14093,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[4]),
.I5(sel0[1]),
.O(\data_rw_o[97][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'hB))
\data_rw_o[97][31]_i_3
@@ -14176,7 +14176,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I4(sel0[4]),
.I5(sel0[2]),
.O(\data_rw_o[99][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h7))
\data_rw_o[99][31]_i_3
@@ -22830,7 +22830,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.D(s00_axi_wdata[9]),
.Q(\[3].[3].s_reqs_reg[15][value][11]_0 [9]),
.S(rst_i));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h4777))
dig_out6_n_INST_0
@@ -22839,7 +22839,7 @@ module system_design_fasec_hwtest_0_0_axi4lite_slave
.I2(\data_rw_o[3] [1]),
.I3(s_tick),
.O(dig_out6_n));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hF808))
\dig_outs_i[0]_INST_0
@@ -56981,14 +56981,14 @@ module system_design_fasec_hwtest_0_0_fasec_hwtest
.\FMC1_LA_P_b[27] (FMC1_LA_P_b[27:20]),
.\FMC1_LA_P_b[32] ({FMC1_LA_P_b[32:31],FMC1_LA_P_b[19:0]}),
.Q(\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0 ),
- .\axi_araddr_reg[2]_rep (cmp_axi4lite_slave_n_523),
- .\axi_araddr_reg[2]_rep__0 (cmp_axi4lite_slave_n_521),
- .\axi_araddr_reg[2]_rep__1 (cmp_axi4lite_slave_n_519),
+ .\axi_araddr_reg[2]_rep (cmp_axi4lite_slave_n_524),
+ .\axi_araddr_reg[2]_rep__0 (cmp_axi4lite_slave_n_522),
+ .\axi_araddr_reg[2]_rep__1 (cmp_axi4lite_slave_n_518),
.\axi_araddr_reg[2]_rep__2 (cmp_axi4lite_slave_n_517),
.\axi_araddr_reg[2]_rep__3 (cmp_axi4lite_slave_n_220),
- .\axi_araddr_reg[3]_rep (cmp_axi4lite_slave_n_524),
- .\axi_araddr_reg[3]_rep__0 (cmp_axi4lite_slave_n_522),
- .\axi_araddr_reg[3]_rep__1 (cmp_axi4lite_slave_n_518),
+ .\axi_araddr_reg[3]_rep (cmp_axi4lite_slave_n_523),
+ .\axi_araddr_reg[3]_rep__0 (cmp_axi4lite_slave_n_521),
+ .\axi_araddr_reg[3]_rep__1 (cmp_axi4lite_slave_n_519),
.\axi_araddr_reg[3]_rep__2 (cmp_axi4lite_slave_n_516),
.\axi_araddr_reg[3]_rep__3 (cmp_axi4lite_slave_n_219),
.\axi_araddr_reg[4] (axi_araddr[4:2]),
@@ -57162,14 +57162,14 @@ module system_design_fasec_hwtest_0_0_fasec_hwtest
.\FMC2_LA_P_b[27] (FMC2_LA_P_b[27:20]),
.\FMC2_LA_P_b[32] ({FMC2_LA_P_b[32:31],FMC2_LA_P_b[19:0]}),
.Q(\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15 ),
- .\axi_araddr_reg[2]_rep (cmp_axi4lite_slave_n_523),
- .\axi_araddr_reg[2]_rep__0 (cmp_axi4lite_slave_n_521),
- .\axi_araddr_reg[2]_rep__1 (cmp_axi4lite_slave_n_519),
+ .\axi_araddr_reg[2]_rep (cmp_axi4lite_slave_n_524),
+ .\axi_araddr_reg[2]_rep__0 (cmp_axi4lite_slave_n_522),
+ .\axi_araddr_reg[2]_rep__1 (cmp_axi4lite_slave_n_518),
.\axi_araddr_reg[2]_rep__2 (cmp_axi4lite_slave_n_517),
.\axi_araddr_reg[2]_rep__3 (cmp_axi4lite_slave_n_220),
- .\axi_araddr_reg[3]_rep (cmp_axi4lite_slave_n_524),
- .\axi_araddr_reg[3]_rep__0 (cmp_axi4lite_slave_n_522),
- .\axi_araddr_reg[3]_rep__1 (cmp_axi4lite_slave_n_518),
+ .\axi_araddr_reg[3]_rep (cmp_axi4lite_slave_n_523),
+ .\axi_araddr_reg[3]_rep__0 (cmp_axi4lite_slave_n_521),
+ .\axi_araddr_reg[3]_rep__1 (cmp_axi4lite_slave_n_519),
.\axi_araddr_reg[3]_rep__2 (cmp_axi4lite_slave_n_516),
.\axi_araddr_reg[3]_rep__3 (cmp_axi4lite_slave_n_219),
.\axi_araddr_reg[4]_rep (cmp_axi4lite_slave_n_520),
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
index 2af8b07b86a72ad10cf16ef3b2c47d30e3651080..b3681fa6f80ca977d671760f804c277f1b34fbf7 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:34:34 2017
+-- Date : Wed Oct 11 12:13:23 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
@@ -2620,69 +2620,69 @@ architecture STRUCTURE of system_design_fasec_hwtest_0_0_axi4lite_slave is
attribute ORIG_CELL_NAME of \axi_araddr_reg[5]_rep\ : label is "axi_araddr_reg[5]";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axi_bresp[1]_i_2\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \axi_bresp[1]_i_3\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \axi_rdata[10]_i_23\ : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of \axi_rdata[11]_i_23\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \axi_bresp[1]_i_3\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \axi_rdata[10]_i_23\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \axi_rdata[11]_i_23\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \axi_rdata[13]_i_23\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axi_rdata[14]_i_23\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axi_rdata[15]_i_23\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \axi_rdata[16]_i_14\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \axi_rdata[16]_i_14\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axi_rdata[16]_i_23\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \axi_rdata[17]_i_23\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \axi_rdata[18]_i_14\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \axi_rdata[18]_i_23\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \axi_rdata[19]_i_14\ : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \axi_rdata[19]_i_23\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \axi_rdata[1]_i_23\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \axi_rdata[20]_i_14\ : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of \axi_rdata[20]_i_24\ : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of \axi_rdata[21]_i_14\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \axi_rdata[17]_i_23\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \axi_rdata[18]_i_14\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \axi_rdata[18]_i_23\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \axi_rdata[19]_i_14\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \axi_rdata[19]_i_23\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \axi_rdata[1]_i_23\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \axi_rdata[20]_i_14\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \axi_rdata[20]_i_24\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \axi_rdata[21]_i_14\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \axi_rdata[21]_i_24\ : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \axi_rdata[22]_i_14\ : label is "soft_lutpair16";
- attribute SOFT_HLUTNM of \axi_rdata[22]_i_24\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \axi_rdata[23]_i_15\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \axi_rdata[23]_i_25\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \axi_rdata[2]_i_23\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \axi_rdata[3]_i_23\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \axi_rdata[4]_i_23\ : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of \axi_rdata[5]_i_23\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \axi_rdata[22]_i_14\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \axi_rdata[22]_i_24\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \axi_rdata[23]_i_15\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \axi_rdata[23]_i_25\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \axi_rdata[2]_i_23\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \axi_rdata[3]_i_23\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \axi_rdata[4]_i_23\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \axi_rdata[6]_i_23\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \axi_rdata[7]_i_23\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axi_rdata[8]_i_23\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axi_rdata[9]_i_23\ : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of \axi_rresp[1]_i_2\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of axi_rvalid_i_1 : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \axi_rresp[1]_i_2\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of axi_rvalid_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \data_rw_o[103][31]_i_3\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \data_rw_o[16][31]_i_3\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \data_rw_o[17][31]_i_3\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \data_rw_o[19][31]_i_3\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_3\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \data_rw_o[16][31]_i_3\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \data_rw_o[17][31]_i_3\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \data_rw_o[19][31]_i_3\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_4\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_5\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \data_rw_o[31][31]_i_3\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_5\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \data_rw_o[31][31]_i_3\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_rw_o[32][31]_i_3\ : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of \data_rw_o[32][31]_i_4\ : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of \data_rw_o[33][31]_i_3\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \data_rw_o[35][31]_i_3\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \data_rw_o[32][31]_i_4\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \data_rw_o[33][31]_i_3\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \data_rw_o[35][31]_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \data_rw_o[3][31]_i_4\ : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of \data_rw_o[3][31]_i_7\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_3\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_4\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_5\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \data_rw_o[3][31]_i_7\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_3\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_4\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_5\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \data_rw_o[84][31]_i_3\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \data_rw_o[85][31]_i_3\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \data_rw_o[85][31]_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \data_rw_o[85][31]_i_4\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \data_rw_o[87][31]_i_3\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of \data_rw_o[88][31]_i_3\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \data_rw_o[89][31]_i_3\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \data_rw_o[89][31]_i_4\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \data_rw_o[93][31]_i_3\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \data_rw_o[94][31]_i_3\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \data_rw_o[96][31]_i_3\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \data_rw_o[97][31]_i_3\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \data_rw_o[99][31]_i_3\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of dig_out6_n_INST_0 : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \dig_outs_i[0]_INST_0\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \data_rw_o[86][31]_i_3\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \data_rw_o[87][31]_i_3\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \data_rw_o[88][31]_i_3\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \data_rw_o[89][31]_i_3\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \data_rw_o[89][31]_i_4\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \data_rw_o[93][31]_i_3\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \data_rw_o[94][31]_i_3\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \data_rw_o[96][31]_i_3\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \data_rw_o[97][31]_i_3\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \data_rw_o[99][31]_i_3\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of dig_out6_n_INST_0 : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \dig_outs_i[0]_INST_0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \v_dout[4]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \v_dout[4]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \v_dout[5]_i_1\ : label is "soft_lutpair33";
@@ -3858,7 +3858,7 @@ begin
C => s00_axi_aclk,
CE => axi_arready_i_1_n_0,
D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[22]_0\,
+ Q => \^axi_rdata_reg[22]_1\,
R => rst_i
);
\axi_araddr_reg[2]_rep__0\: unisim.vcomponents.FDRE
@@ -3869,7 +3869,7 @@ begin
C => s00_axi_aclk,
CE => axi_arready_i_1_n_0,
D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[17]_0\,
+ Q => \^axi_rdata_reg[17]_1\,
R => rst_i
);
\axi_araddr_reg[2]_rep__1\: unisim.vcomponents.FDRE
@@ -3880,7 +3880,7 @@ begin
C => s00_axi_aclk,
CE => axi_arready_i_1_n_0,
D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[12]_1\,
+ Q => \^axi_rdata_reg[12]_0\,
R => rst_i
);
\axi_araddr_reg[2]_rep__2\: unisim.vcomponents.FDRE
@@ -3924,7 +3924,7 @@ begin
C => s00_axi_aclk,
CE => axi_arready_i_1_n_0,
D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[22]_1\,
+ Q => \^axi_rdata_reg[22]_0\,
R => rst_i
);
\axi_araddr_reg[3]_rep__0\: unisim.vcomponents.FDRE
@@ -3935,7 +3935,7 @@ begin
C => s00_axi_aclk,
CE => axi_arready_i_1_n_0,
D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[17]_1\,
+ Q => \^axi_rdata_reg[17]_0\,
R => rst_i
);
\axi_araddr_reg[3]_rep__1\: unisim.vcomponents.FDRE
@@ -3946,7 +3946,7 @@ begin
C => s00_axi_aclk,
CE => axi_arready_i_1_n_0,
D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[12]_0\,
+ Q => \^axi_rdata_reg[12]_1\,
R => rst_i
);
\axi_araddr_reg[3]_rep__2\: unisim.vcomponents.FDRE
@@ -4284,7 +4284,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[0]_i_14\: unisim.vcomponents.LUT6
generic map(
- INIT => X"EE55FA00EE00FA00"
+ INIT => X"4455FA004400FA00"
)
port map (
I0 => \^axi_rdata_reg[0]_0\,
@@ -4545,22 +4545,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[12]_1\,
+ I0 => \^axi_rdata_reg[12]_0\,
I1 => \s_datao_fmc1[4]\(2),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[10]_i_33_n_0\,
O => \axi_rdata[10]_i_13_n_0\
);
\axi_rdata[10]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"CC408840"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[12]_0\,
+ I1 => \^axi_rdata_reg[12]_1\,
I2 => gem_status_vector_i(10),
- I3 => \^axi_rdata_reg[12]_1\,
+ I3 => \^axi_rdata_reg[12]_0\,
I4 => \data_rw_o_reg_n_0_[3][10]\,
O => \axi_rdata[10]_i_14_n_0\
);
@@ -4571,9 +4571,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[10]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \dac_ch_o_reg[0][31]_0\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^axi_rdata_reg[10]_0\,
O => \axi_rdata[10]_i_17_n_0\
);
@@ -4584,9 +4584,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[10]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \s_datao_fmc2[4]\(2),
- I4 => \^axi_rdata_reg[12]_0\,
+ I4 => \^axi_rdata_reg[12]_1\,
O => \axi_rdata[10]_i_19_n_0\
);
\axi_rdata[10]_i_23\: unisim.vcomponents.LUT4
@@ -4594,9 +4594,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[12]_0\,
+ I0 => \^axi_rdata_reg[12]_1\,
I1 => \dac_ch_o_reg[0][31]\(10),
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[10]_i_23_n_0\
);
@@ -4607,9 +4607,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]\(10),
I1 => \^[2].[2].s_reqs_reg[10][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]\(10),
O => \axi_rdata[10]_i_29_n_0\
);
@@ -4620,9 +4620,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]\(10),
I1 => \^[3].[2].s_reqs_reg[14][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]\(10),
O => \axi_rdata[10]_i_30_n_0\
);
@@ -4633,9 +4633,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^q\(10),
I1 => \^[0].[2].s_reqs_reg[2][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]\(10),
O => \axi_rdata[10]_i_31_n_0\
);
@@ -4646,9 +4646,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]\(10),
I1 => \^[1].[2].s_reqs_reg[6][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]\(10),
O => \axi_rdata[10]_i_32_n_0\
);
@@ -4659,9 +4659,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][10]\,
I1 => \data_rw_o_reg_n_0_[10][10]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc1[0]\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[10]_i_33_n_0\
);
\axi_rdata[10]_i_34\: unisim.vcomponents.LUT6
@@ -4671,9 +4671,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]\(10),
I1 => \^[4].[2].s_reqs_reg[18][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]\(10),
O => \axi_rdata[10]_i_34_n_0\
);
@@ -4684,9 +4684,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(10),
I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(10),
O => \axi_rdata[10]_i_35_n_0\
);
@@ -4697,9 +4697,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(10),
I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(10),
O => \axi_rdata[10]_i_36_n_0\
);
@@ -4710,9 +4710,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[0].[3].s_reqs_reg[3][value][11]\(10),
I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(10),
O => \axi_rdata[10]_i_37_n_0\
);
@@ -4723,9 +4723,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][10]\,
I1 => \data_rw_o_reg_n_0_[78][10]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc2[0]\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[10]_i_39_n_0\
);
\axi_rdata[10]_i_42\: unisim.vcomponents.LUT6
@@ -4735,9 +4735,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(10),
I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(10),
O => \axi_rdata[10]_i_42_n_0\
);
@@ -4748,9 +4748,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(10),
I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(10),
O => \axi_rdata[10]_i_43_n_0\
);
@@ -4824,22 +4824,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[12]_1\,
+ I0 => \^axi_rdata_reg[12]_0\,
I1 => \s_datao_fmc1[4]\(3),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[11]_i_33_n_0\,
O => \axi_rdata[11]_i_13_n_0\
);
\axi_rdata[11]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"CC408840"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[12]_0\,
+ I1 => \^axi_rdata_reg[12]_1\,
I2 => gem_status_vector_i(11),
- I3 => \^axi_rdata_reg[12]_1\,
+ I3 => \^axi_rdata_reg[12]_0\,
I4 => \data_rw_o_reg_n_0_[3][11]\,
O => \axi_rdata[11]_i_14_n_0\
);
@@ -4850,9 +4850,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[11]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \dac_ch_o_reg[0][31]_0\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[11]_i_17_n_0\
);
@@ -4863,9 +4863,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[11]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \s_datao_fmc2[4]\(3),
- I4 => \^axi_rdata_reg[12]_0\,
+ I4 => \^axi_rdata_reg[12]_1\,
O => \axi_rdata[11]_i_19_n_0\
);
\axi_rdata[11]_i_23\: unisim.vcomponents.LUT4
@@ -4873,9 +4873,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[12]_0\,
+ I0 => \^axi_rdata_reg[12]_1\,
I1 => \dac_ch_o_reg[0][31]\(11),
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[11]_i_23_n_0\
);
@@ -4886,9 +4886,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]\(11),
I1 => \^[2].[2].s_reqs_reg[10][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]\(11),
O => \axi_rdata[11]_i_29_n_0\
);
@@ -4899,9 +4899,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]\(11),
I1 => \^[3].[2].s_reqs_reg[14][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]\(11),
O => \axi_rdata[11]_i_30_n_0\
);
@@ -4912,9 +4912,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^q\(11),
I1 => \^[0].[2].s_reqs_reg[2][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]\(11),
O => \axi_rdata[11]_i_31_n_0\
);
@@ -4925,9 +4925,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]\(11),
I1 => \^[1].[2].s_reqs_reg[6][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]\(11),
O => \axi_rdata[11]_i_32_n_0\
);
@@ -4938,9 +4938,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][11]\,
I1 => \data_rw_o_reg_n_0_[10][11]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc1[0]\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[11]_i_33_n_0\
);
\axi_rdata[11]_i_34\: unisim.vcomponents.LUT6
@@ -4950,9 +4950,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]\(11),
I1 => \^[4].[2].s_reqs_reg[18][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]\(11),
O => \axi_rdata[11]_i_34_n_0\
);
@@ -4963,9 +4963,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(11),
I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(11),
O => \axi_rdata[11]_i_35_n_0\
);
@@ -4976,9 +4976,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(11),
I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(11),
O => \axi_rdata[11]_i_36_n_0\
);
@@ -4989,9 +4989,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[0].[3].s_reqs_reg[3][value][11]\(11),
I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(11),
O => \axi_rdata[11]_i_37_n_0\
);
@@ -5002,9 +5002,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][11]\,
I1 => \data_rw_o_reg_n_0_[78][11]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc2[0]\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[11]_i_39_n_0\
);
\axi_rdata[11]_i_42\: unisim.vcomponents.LUT6
@@ -5014,9 +5014,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(11),
I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(11),
O => \axi_rdata[11]_i_42_n_0\
);
@@ -5027,9 +5027,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(11),
I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(11),
O => \axi_rdata[11]_i_43_n_0\
);
@@ -5103,22 +5103,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[12]_1\,
+ I0 => \^axi_rdata_reg[12]_0\,
I1 => \s_datao_fmc1[4]\(4),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[12]_i_33_n_0\,
O => \axi_rdata[12]_i_13_n_0\
);
\axi_rdata[12]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"44C800C8"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[12]_0\,
+ I1 => \^axi_rdata_reg[12]_1\,
I2 => gem_status_vector_i(12),
- I3 => \^axi_rdata_reg[12]_1\,
+ I3 => \^axi_rdata_reg[12]_0\,
I4 => \data_rw_o_reg_n_0_[3][12]\,
O => \axi_rdata[12]_i_14_n_0\
);
@@ -5129,9 +5129,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[12]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \dac_ch_o_reg[0][31]_0\(12),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[12]_i_17_n_0\
);
@@ -5142,9 +5142,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[12]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \s_datao_fmc2[4]\(4),
- I4 => \^axi_rdata_reg[12]_0\,
+ I4 => \^axi_rdata_reg[12]_1\,
O => \axi_rdata[12]_i_19_n_0\
);
\axi_rdata[12]_i_23\: unisim.vcomponents.LUT4
@@ -5152,9 +5152,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[12]_0\,
+ I0 => \^axi_rdata_reg[12]_1\,
I1 => \dac_ch_o_reg[0][31]\(12),
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[12]_i_23_n_0\
);
@@ -5165,9 +5165,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][12]\,
I1 => \data_rw_o_reg_n_0_[26][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[25][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[24][12]\,
O => \axi_rdata[12]_i_29_n_0\
);
@@ -5178,9 +5178,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][12]\,
I1 => \data_rw_o_reg_n_0_[30][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[29][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[28][12]\,
O => \axi_rdata[12]_i_30_n_0\
);
@@ -5191,9 +5191,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][12]\,
I1 => \data_rw_o_reg_n_0_[18][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[17][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[16][12]\,
O => \axi_rdata[12]_i_31_n_0\
);
@@ -5204,9 +5204,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][12]\,
I1 => \data_rw_o_reg_n_0_[22][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[21][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[20][12]\,
O => \axi_rdata[12]_i_32_n_0\
);
@@ -5217,9 +5217,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][12]\,
I1 => \data_rw_o_reg_n_0_[10][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc1[0]\(12),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[12]_i_33_n_0\
);
\axi_rdata[12]_i_34\: unisim.vcomponents.LUT6
@@ -5229,9 +5229,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][12]\,
I1 => \data_rw_o_reg_n_0_[34][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[33][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[32][12]\,
O => \axi_rdata[12]_i_34_n_0\
);
@@ -5242,9 +5242,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][12]\,
I1 => \data_rw_o_reg_n_0_[90][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[89][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[88][12]\,
O => \axi_rdata[12]_i_35_n_0\
);
@@ -5255,9 +5255,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][12]\,
I1 => \data_rw_o_reg_n_0_[94][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[93][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[92][12]\,
O => \axi_rdata[12]_i_36_n_0\
);
@@ -5268,9 +5268,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][12]\,
I1 => \data_rw_o_reg_n_0_[86][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[85][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[84][12]\,
O => \axi_rdata[12]_i_37_n_0\
);
@@ -5281,9 +5281,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][12]\,
I1 => \data_rw_o_reg_n_0_[78][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc2[0]\(12),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[12]_i_39_n_0\
);
\axi_rdata[12]_i_42\: unisim.vcomponents.LUT6
@@ -5293,9 +5293,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][12]\,
I1 => \data_rw_o_reg_n_0_[98][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[97][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[96][12]\,
O => \axi_rdata[12]_i_42_n_0\
);
@@ -5306,9 +5306,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][12]\,
I1 => \data_rw_o_reg_n_0_[102][12]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \data_rw_o_reg_n_0_[101][12]\,
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \data_rw_o_reg_n_0_[100][12]\,
O => \axi_rdata[12]_i_43_n_0\
);
@@ -5382,23 +5382,23 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[17]_0\,
+ I0 => \^axi_rdata_reg[17]_1\,
I1 => \s_datao_fmc1[4]\(5),
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[13]_i_33_n_0\,
O => \axi_rdata[13]_i_13_n_0\
);
\axi_rdata[13]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"0000B800"
+ INIT => X"CCC888C8"
)
port map (
- I0 => \data_rw_o_reg_n_0_[3][13]\,
+ I0 => \^axi_rdata_reg[18]_0\,
I1 => \^axi_rdata_reg[17]_0\,
I2 => gem_status_vector_i(13),
I3 => \^axi_rdata_reg[17]_1\,
- I4 => \^axi_rdata_reg[18]_0\,
+ I4 => \data_rw_o_reg_n_0_[3][13]\,
O => \axi_rdata[13]_i_14_n_0\
);
\axi_rdata[13]_i_17\: unisim.vcomponents.LUT6
@@ -5408,9 +5408,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[13]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(13),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[13]_i_17_n_0\
);
@@ -5421,9 +5421,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[13]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \s_datao_fmc2[4]\(5),
- I4 => \^axi_rdata_reg[17]_1\,
+ I4 => \^axi_rdata_reg[17]_0\,
O => \axi_rdata[13]_i_19_n_0\
);
\axi_rdata[13]_i_23\: unisim.vcomponents.LUT4
@@ -5431,9 +5431,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[17]_1\,
+ I0 => \^axi_rdata_reg[17]_0\,
I1 => \dac_ch_o_reg[0][31]\(13),
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[13]_i_23_n_0\
);
@@ -5444,9 +5444,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][13]\,
I1 => \data_rw_o_reg_n_0_[26][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[25][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[24][13]\,
O => \axi_rdata[13]_i_29_n_0\
);
@@ -5457,9 +5457,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][13]\,
I1 => \data_rw_o_reg_n_0_[30][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[29][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[28][13]\,
O => \axi_rdata[13]_i_30_n_0\
);
@@ -5470,9 +5470,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][13]\,
I1 => \data_rw_o_reg_n_0_[18][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[17][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[16][13]\,
O => \axi_rdata[13]_i_31_n_0\
);
@@ -5483,9 +5483,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][13]\,
I1 => \data_rw_o_reg_n_0_[22][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[21][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[20][13]\,
O => \axi_rdata[13]_i_32_n_0\
);
@@ -5496,9 +5496,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][13]\,
I1 => \data_rw_o_reg_n_0_[10][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc1[0]\(13),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[13]_i_33_n_0\
);
\axi_rdata[13]_i_34\: unisim.vcomponents.LUT6
@@ -5508,9 +5508,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][13]\,
I1 => \data_rw_o_reg_n_0_[34][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[33][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[32][13]\,
O => \axi_rdata[13]_i_34_n_0\
);
@@ -5521,9 +5521,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][13]\,
I1 => \data_rw_o_reg_n_0_[90][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[89][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[88][13]\,
O => \axi_rdata[13]_i_35_n_0\
);
@@ -5534,9 +5534,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][13]\,
I1 => \data_rw_o_reg_n_0_[94][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[93][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[92][13]\,
O => \axi_rdata[13]_i_36_n_0\
);
@@ -5547,9 +5547,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][13]\,
I1 => \data_rw_o_reg_n_0_[86][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[85][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[84][13]\,
O => \axi_rdata[13]_i_37_n_0\
);
@@ -5560,9 +5560,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][13]\,
I1 => \data_rw_o_reg_n_0_[78][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc2[0]\(13),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[13]_i_39_n_0\
);
\axi_rdata[13]_i_42\: unisim.vcomponents.LUT6
@@ -5572,9 +5572,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][13]\,
I1 => \data_rw_o_reg_n_0_[98][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[97][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[96][13]\,
O => \axi_rdata[13]_i_42_n_0\
);
@@ -5585,9 +5585,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][13]\,
I1 => \data_rw_o_reg_n_0_[102][13]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[101][13]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[100][13]\,
O => \axi_rdata[13]_i_43_n_0\
);
@@ -5661,9 +5661,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[17]_0\,
+ I0 => \^axi_rdata_reg[17]_1\,
I1 => \s_datao_fmc1[4]\(6),
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[14]_i_33_n_0\,
O => \axi_rdata[14]_i_13_n_0\
@@ -5674,9 +5674,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
)
port map (
I0 => \data_rw_o_reg_n_0_[3][14]\,
- I1 => \^axi_rdata_reg[17]_0\,
+ I1 => \^axi_rdata_reg[17]_1\,
I2 => gem_status_vector_i(14),
- I3 => \^axi_rdata_reg[17]_1\,
+ I3 => \^axi_rdata_reg[17]_0\,
I4 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[14]_i_14_n_0\
);
@@ -5687,9 +5687,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[14]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(14),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[14]_i_17_n_0\
);
@@ -5700,9 +5700,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[14]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \s_datao_fmc2[4]\(6),
- I4 => \^axi_rdata_reg[17]_1\,
+ I4 => \^axi_rdata_reg[17]_0\,
O => \axi_rdata[14]_i_19_n_0\
);
\axi_rdata[14]_i_23\: unisim.vcomponents.LUT4
@@ -5710,9 +5710,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[17]_1\,
+ I0 => \^axi_rdata_reg[17]_0\,
I1 => \dac_ch_o_reg[0][31]\(14),
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[14]_i_23_n_0\
);
@@ -5723,9 +5723,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][14]\,
I1 => \data_rw_o_reg_n_0_[26][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[25][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[24][14]\,
O => \axi_rdata[14]_i_29_n_0\
);
@@ -5736,9 +5736,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][14]\,
I1 => \data_rw_o_reg_n_0_[30][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[29][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[28][14]\,
O => \axi_rdata[14]_i_30_n_0\
);
@@ -5749,9 +5749,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][14]\,
I1 => \data_rw_o_reg_n_0_[18][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[17][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[16][14]\,
O => \axi_rdata[14]_i_31_n_0\
);
@@ -5762,9 +5762,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][14]\,
I1 => \data_rw_o_reg_n_0_[22][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[21][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[20][14]\,
O => \axi_rdata[14]_i_32_n_0\
);
@@ -5775,9 +5775,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][14]\,
I1 => \data_rw_o_reg_n_0_[10][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc1[0]\(14),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[14]_i_33_n_0\
);
\axi_rdata[14]_i_34\: unisim.vcomponents.LUT6
@@ -5787,9 +5787,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][14]\,
I1 => \data_rw_o_reg_n_0_[34][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[33][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[32][14]\,
O => \axi_rdata[14]_i_34_n_0\
);
@@ -5800,9 +5800,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][14]\,
I1 => \data_rw_o_reg_n_0_[90][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[89][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[88][14]\,
O => \axi_rdata[14]_i_35_n_0\
);
@@ -5813,9 +5813,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][14]\,
I1 => \data_rw_o_reg_n_0_[94][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[93][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[92][14]\,
O => \axi_rdata[14]_i_36_n_0\
);
@@ -5826,9 +5826,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][14]\,
I1 => \data_rw_o_reg_n_0_[86][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[85][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[84][14]\,
O => \axi_rdata[14]_i_37_n_0\
);
@@ -5839,9 +5839,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][14]\,
I1 => \data_rw_o_reg_n_0_[78][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc2[0]\(14),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[14]_i_39_n_0\
);
\axi_rdata[14]_i_42\: unisim.vcomponents.LUT6
@@ -5851,9 +5851,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][14]\,
I1 => \data_rw_o_reg_n_0_[98][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[97][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[96][14]\,
O => \axi_rdata[14]_i_42_n_0\
);
@@ -5864,9 +5864,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][14]\,
I1 => \data_rw_o_reg_n_0_[102][14]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[101][14]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[100][14]\,
O => \axi_rdata[14]_i_43_n_0\
);
@@ -5940,22 +5940,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[17]_0\,
+ I0 => \^axi_rdata_reg[17]_1\,
I1 => \s_datao_fmc1[4]\(7),
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[15]_i_33_n_0\,
O => \axi_rdata[15]_i_13_n_0\
);
\axi_rdata[15]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"CC408840"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_1\,
+ I1 => \^axi_rdata_reg[17]_0\,
I2 => gem_status_vector_i(15),
- I3 => \^axi_rdata_reg[17]_0\,
+ I3 => \^axi_rdata_reg[17]_1\,
I4 => \data_rw_o_reg_n_0_[3][15]\,
O => \axi_rdata[15]_i_14_n_0\
);
@@ -5966,9 +5966,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[15]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(15),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[15]_i_17_n_0\
);
@@ -5979,9 +5979,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[15]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \s_datao_fmc2[4]\(7),
- I4 => \^axi_rdata_reg[17]_1\,
+ I4 => \^axi_rdata_reg[17]_0\,
O => \axi_rdata[15]_i_19_n_0\
);
\axi_rdata[15]_i_23\: unisim.vcomponents.LUT4
@@ -5989,9 +5989,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[17]_1\,
+ I0 => \^axi_rdata_reg[17]_0\,
I1 => \dac_ch_o_reg[0][31]\(15),
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[15]_i_23_n_0\
);
@@ -6002,9 +6002,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][15]\,
I1 => \data_rw_o_reg_n_0_[26][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[25][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[24][15]\,
O => \axi_rdata[15]_i_29_n_0\
);
@@ -6015,9 +6015,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][15]\,
I1 => \data_rw_o_reg_n_0_[30][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[29][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[28][15]\,
O => \axi_rdata[15]_i_30_n_0\
);
@@ -6028,9 +6028,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][15]\,
I1 => \data_rw_o_reg_n_0_[18][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[17][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[16][15]\,
O => \axi_rdata[15]_i_31_n_0\
);
@@ -6041,9 +6041,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][15]\,
I1 => \data_rw_o_reg_n_0_[22][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[21][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[20][15]\,
O => \axi_rdata[15]_i_32_n_0\
);
@@ -6054,9 +6054,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][15]\,
I1 => \data_rw_o_reg_n_0_[10][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc1[0]\(15),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[15]_i_33_n_0\
);
\axi_rdata[15]_i_34\: unisim.vcomponents.LUT6
@@ -6066,9 +6066,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][15]\,
I1 => \data_rw_o_reg_n_0_[34][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[33][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[32][15]\,
O => \axi_rdata[15]_i_34_n_0\
);
@@ -6079,9 +6079,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][15]\,
I1 => \data_rw_o_reg_n_0_[90][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[89][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[88][15]\,
O => \axi_rdata[15]_i_35_n_0\
);
@@ -6092,9 +6092,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][15]\,
I1 => \data_rw_o_reg_n_0_[94][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[93][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[92][15]\,
O => \axi_rdata[15]_i_36_n_0\
);
@@ -6105,9 +6105,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][15]\,
I1 => \data_rw_o_reg_n_0_[86][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[85][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[84][15]\,
O => \axi_rdata[15]_i_37_n_0\
);
@@ -6118,9 +6118,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][15]\,
I1 => \data_rw_o_reg_n_0_[78][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc2[0]\(15),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[15]_i_39_n_0\
);
\axi_rdata[15]_i_42\: unisim.vcomponents.LUT6
@@ -6130,9 +6130,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][15]\,
I1 => \data_rw_o_reg_n_0_[98][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[97][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[96][15]\,
O => \axi_rdata[15]_i_42_n_0\
);
@@ -6143,9 +6143,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][15]\,
I1 => \data_rw_o_reg_n_0_[102][15]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[101][15]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[100][15]\,
O => \axi_rdata[15]_i_43_n_0\
);
@@ -6219,22 +6219,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[17]_0\,
+ I0 => \^axi_rdata_reg[17]_1\,
I1 => \s_datao_fmc1[4]\(8),
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[16]_i_33_n_0\,
O => \axi_rdata[16]_i_13_n_0\
);
\axi_rdata[16]_i_14\: unisim.vcomponents.LUT4
generic map(
- INIT => X"C800"
+ INIT => X"C888"
)
port map (
I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_1\,
+ I1 => \^axi_rdata_reg[17]_0\,
I2 => \data_rw_o_reg_n_0_[3][16]\,
- I3 => \^axi_rdata_reg[17]_0\,
+ I3 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[16]_i_14_n_0\
);
\axi_rdata[16]_i_17\: unisim.vcomponents.LUT6
@@ -6244,9 +6244,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[16]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(16),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[16]_i_17_n_0\
);
@@ -6257,9 +6257,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[16]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \s_datao_fmc2[4]\(8),
- I4 => \^axi_rdata_reg[17]_1\,
+ I4 => \^axi_rdata_reg[17]_0\,
O => \axi_rdata[16]_i_19_n_0\
);
\axi_rdata[16]_i_23\: unisim.vcomponents.LUT4
@@ -6267,9 +6267,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[17]_1\,
+ I0 => \^axi_rdata_reg[17]_0\,
I1 => \dac_ch_o_reg[0][31]\(16),
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[16]_i_23_n_0\
);
@@ -6280,9 +6280,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][16]\,
I1 => \data_rw_o_reg_n_0_[26][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[25][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[24][16]\,
O => \axi_rdata[16]_i_29_n_0\
);
@@ -6293,9 +6293,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][16]\,
I1 => \data_rw_o_reg_n_0_[30][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[29][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[28][16]\,
O => \axi_rdata[16]_i_30_n_0\
);
@@ -6306,9 +6306,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][16]\,
I1 => \data_rw_o_reg_n_0_[18][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[17][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[16][16]\,
O => \axi_rdata[16]_i_31_n_0\
);
@@ -6319,9 +6319,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][16]\,
I1 => \data_rw_o_reg_n_0_[22][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[21][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[20][16]\,
O => \axi_rdata[16]_i_32_n_0\
);
@@ -6332,9 +6332,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][16]\,
I1 => \data_rw_o_reg_n_0_[10][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc1[0]\(16),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[16]_i_33_n_0\
);
\axi_rdata[16]_i_34\: unisim.vcomponents.LUT6
@@ -6344,9 +6344,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][16]\,
I1 => \data_rw_o_reg_n_0_[34][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[33][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[32][16]\,
O => \axi_rdata[16]_i_34_n_0\
);
@@ -6357,9 +6357,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][16]\,
I1 => \data_rw_o_reg_n_0_[90][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[89][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[88][16]\,
O => \axi_rdata[16]_i_35_n_0\
);
@@ -6370,9 +6370,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][16]\,
I1 => \data_rw_o_reg_n_0_[94][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[93][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[92][16]\,
O => \axi_rdata[16]_i_36_n_0\
);
@@ -6383,9 +6383,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][16]\,
I1 => \data_rw_o_reg_n_0_[86][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[85][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[84][16]\,
O => \axi_rdata[16]_i_37_n_0\
);
@@ -6396,9 +6396,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][16]\,
I1 => \data_rw_o_reg_n_0_[78][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc2[0]\(16),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[16]_i_39_n_0\
);
\axi_rdata[16]_i_42\: unisim.vcomponents.LUT6
@@ -6408,9 +6408,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][16]\,
I1 => \data_rw_o_reg_n_0_[98][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[97][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[96][16]\,
O => \axi_rdata[16]_i_42_n_0\
);
@@ -6421,9 +6421,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][16]\,
I1 => \data_rw_o_reg_n_0_[102][16]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[101][16]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[100][16]\,
O => \axi_rdata[16]_i_43_n_0\
);
@@ -6497,22 +6497,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[17]_0\,
+ I0 => \^axi_rdata_reg[17]_1\,
I1 => \s_datao_fmc1[4]\(9),
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[17]_i_33_n_0\,
O => \axi_rdata[17]_i_13_n_0\
);
\axi_rdata[17]_i_14\: unisim.vcomponents.LUT4
generic map(
- INIT => X"4088"
+ INIT => X"0080"
)
port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_1\,
- I2 => \data_rw_o_reg_n_0_[3][17]\,
- I3 => \^axi_rdata_reg[17]_0\,
+ I0 => \^axi_rdata_reg[17]_1\,
+ I1 => \data_rw_o_reg_n_0_[3][17]\,
+ I2 => \^axi_rdata_reg[17]_0\,
+ I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[17]_i_14_n_0\
);
\axi_rdata[17]_i_17\: unisim.vcomponents.LUT6
@@ -6522,9 +6522,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[17]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(17),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[17]_i_17_n_0\
);
@@ -6535,9 +6535,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[17]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \s_datao_fmc2[4]\(9),
- I4 => \^axi_rdata_reg[17]_1\,
+ I4 => \^axi_rdata_reg[17]_0\,
O => \axi_rdata[17]_i_19_n_0\
);
\axi_rdata[17]_i_23\: unisim.vcomponents.LUT4
@@ -6545,9 +6545,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[17]_1\,
+ I0 => \^axi_rdata_reg[17]_0\,
I1 => \dac_ch_o_reg[0][31]\(17),
- I2 => \^axi_rdata_reg[17]_0\,
+ I2 => \^axi_rdata_reg[17]_1\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[17]_i_23_n_0\
);
@@ -6558,9 +6558,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][17]\,
I1 => \data_rw_o_reg_n_0_[26][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[25][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[24][17]\,
O => \axi_rdata[17]_i_29_n_0\
);
@@ -6571,9 +6571,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][17]\,
I1 => \data_rw_o_reg_n_0_[30][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[29][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[28][17]\,
O => \axi_rdata[17]_i_30_n_0\
);
@@ -6584,9 +6584,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][17]\,
I1 => \data_rw_o_reg_n_0_[18][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[17][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[16][17]\,
O => \axi_rdata[17]_i_31_n_0\
);
@@ -6597,9 +6597,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][17]\,
I1 => \data_rw_o_reg_n_0_[22][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[21][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[20][17]\,
O => \axi_rdata[17]_i_32_n_0\
);
@@ -6610,9 +6610,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][17]\,
I1 => \data_rw_o_reg_n_0_[10][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc1[0]\(17),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[17]_i_33_n_0\
);
\axi_rdata[17]_i_34\: unisim.vcomponents.LUT6
@@ -6622,9 +6622,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][17]\,
I1 => \data_rw_o_reg_n_0_[34][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[33][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[32][17]\,
O => \axi_rdata[17]_i_34_n_0\
);
@@ -6635,9 +6635,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][17]\,
I1 => \data_rw_o_reg_n_0_[90][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[89][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[88][17]\,
O => \axi_rdata[17]_i_35_n_0\
);
@@ -6648,9 +6648,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][17]\,
I1 => \data_rw_o_reg_n_0_[94][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[93][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[92][17]\,
O => \axi_rdata[17]_i_36_n_0\
);
@@ -6661,9 +6661,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][17]\,
I1 => \data_rw_o_reg_n_0_[86][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[85][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[84][17]\,
O => \axi_rdata[17]_i_37_n_0\
);
@@ -6674,9 +6674,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][17]\,
I1 => \data_rw_o_reg_n_0_[78][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \s_datao_fmc2[0]\(17),
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
O => \axi_rdata[17]_i_39_n_0\
);
\axi_rdata[17]_i_42\: unisim.vcomponents.LUT6
@@ -6686,9 +6686,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][17]\,
I1 => \data_rw_o_reg_n_0_[98][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[97][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[96][17]\,
O => \axi_rdata[17]_i_42_n_0\
);
@@ -6699,9 +6699,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][17]\,
I1 => \data_rw_o_reg_n_0_[102][17]\,
- I2 => \^axi_rdata_reg[17]_1\,
+ I2 => \^axi_rdata_reg[17]_0\,
I3 => \data_rw_o_reg_n_0_[101][17]\,
- I4 => \^axi_rdata_reg[17]_0\,
+ I4 => \^axi_rdata_reg[17]_1\,
I5 => \data_rw_o_reg_n_0_[100][17]\,
O => \axi_rdata[17]_i_43_n_0\
);
@@ -6775,22 +6775,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[22]_0\,
+ I0 => \^axi_rdata_reg[22]_1\,
I1 => \s_datao_fmc1[4]\(10),
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \^axi_rdata_reg[18]_0\,
I4 => \axi_rdata[18]_i_33_n_0\,
O => \axi_rdata[18]_i_13_n_0\
);
\axi_rdata[18]_i_14\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0080"
+ INIT => X"C888"
)
port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \data_rw_o_reg_n_0_[3][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
+ I0 => \^axi_rdata_reg[18]_0\,
+ I1 => \^axi_rdata_reg[22]_0\,
+ I2 => \data_rw_o_reg_n_0_[3][18]\,
+ I3 => \^axi_rdata_reg[22]_1\,
O => \axi_rdata[18]_i_14_n_0\
);
\axi_rdata[18]_i_17\: unisim.vcomponents.LUT6
@@ -6800,9 +6800,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[18]_i_34_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(18),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[18]_i_17_n_0\
);
@@ -6813,9 +6813,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[18]_i_37_n_0\,
I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \s_datao_fmc2[4]\(10),
- I4 => \^axi_rdata_reg[22]_1\,
+ I4 => \^axi_rdata_reg[22]_0\,
O => \axi_rdata[18]_i_19_n_0\
);
\axi_rdata[18]_i_23\: unisim.vcomponents.LUT4
@@ -6823,9 +6823,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \dac_ch_o_reg[0][31]\(18),
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \^axi_rdata_reg[18]_0\,
O => \axi_rdata[18]_i_23_n_0\
);
@@ -6836,9 +6836,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][18]\,
I1 => \data_rw_o_reg_n_0_[26][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[25][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[24][18]\,
O => \axi_rdata[18]_i_29_n_0\
);
@@ -6849,9 +6849,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][18]\,
I1 => \data_rw_o_reg_n_0_[30][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[29][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[28][18]\,
O => \axi_rdata[18]_i_30_n_0\
);
@@ -6862,9 +6862,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][18]\,
I1 => \data_rw_o_reg_n_0_[18][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[17][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[16][18]\,
O => \axi_rdata[18]_i_31_n_0\
);
@@ -6875,9 +6875,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][18]\,
I1 => \data_rw_o_reg_n_0_[22][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[21][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[20][18]\,
O => \axi_rdata[18]_i_32_n_0\
);
@@ -6888,9 +6888,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][18]\,
I1 => \data_rw_o_reg_n_0_[10][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \s_datao_fmc1[0]\(18),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
O => \axi_rdata[18]_i_33_n_0\
);
\axi_rdata[18]_i_34\: unisim.vcomponents.LUT6
@@ -6900,9 +6900,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][18]\,
I1 => \data_rw_o_reg_n_0_[34][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[33][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[32][18]\,
O => \axi_rdata[18]_i_34_n_0\
);
@@ -6913,9 +6913,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][18]\,
I1 => \data_rw_o_reg_n_0_[90][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[89][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[88][18]\,
O => \axi_rdata[18]_i_35_n_0\
);
@@ -6926,9 +6926,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][18]\,
I1 => \data_rw_o_reg_n_0_[94][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[93][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[92][18]\,
O => \axi_rdata[18]_i_36_n_0\
);
@@ -6939,9 +6939,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][18]\,
I1 => \data_rw_o_reg_n_0_[86][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[85][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[84][18]\,
O => \axi_rdata[18]_i_37_n_0\
);
@@ -6952,9 +6952,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][18]\,
I1 => \data_rw_o_reg_n_0_[78][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \s_datao_fmc2[0]\(18),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
O => \axi_rdata[18]_i_39_n_0\
);
\axi_rdata[18]_i_42\: unisim.vcomponents.LUT6
@@ -6964,9 +6964,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][18]\,
I1 => \data_rw_o_reg_n_0_[98][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[97][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[96][18]\,
O => \axi_rdata[18]_i_42_n_0\
);
@@ -6977,9 +6977,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][18]\,
I1 => \data_rw_o_reg_n_0_[102][18]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[101][18]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[100][18]\,
O => \axi_rdata[18]_i_43_n_0\
);
@@ -7053,9 +7053,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[22]_0\,
+ I0 => \^axi_rdata_reg[22]_1\,
I1 => \s_datao_fmc1[4]\(11),
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \^axi_rdata_reg[23]_0\(2),
I4 => \axi_rdata[19]_i_33_n_0\,
O => \axi_rdata[19]_i_13_n_0\
@@ -7066,9 +7066,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
)
port map (
I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[22]_1\,
+ I1 => \^axi_rdata_reg[22]_0\,
I2 => \data_rw_o_reg_n_0_[3][19]\,
- I3 => \^axi_rdata_reg[22]_0\,
+ I3 => \^axi_rdata_reg[22]_1\,
O => \axi_rdata[19]_i_14_n_0\
);
\axi_rdata[19]_i_17\: unisim.vcomponents.LUT6
@@ -7078,9 +7078,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[19]_i_34_n_0\,
I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(19),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[19]_i_17_n_0\
);
@@ -7091,9 +7091,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[19]_i_37_n_0\,
I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \s_datao_fmc2[4]\(11),
- I4 => \^axi_rdata_reg[22]_1\,
+ I4 => \^axi_rdata_reg[22]_0\,
O => \axi_rdata[19]_i_19_n_0\
);
\axi_rdata[19]_i_23\: unisim.vcomponents.LUT4
@@ -7101,9 +7101,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \dac_ch_o_reg[0][31]\(19),
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[19]_i_23_n_0\
);
@@ -7114,9 +7114,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][19]\,
I1 => \data_rw_o_reg_n_0_[26][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[25][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[24][19]\,
O => \axi_rdata[19]_i_29_n_0\
);
@@ -7127,9 +7127,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][19]\,
I1 => \data_rw_o_reg_n_0_[30][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[29][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[28][19]\,
O => \axi_rdata[19]_i_30_n_0\
);
@@ -7140,9 +7140,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][19]\,
I1 => \data_rw_o_reg_n_0_[18][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[17][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[16][19]\,
O => \axi_rdata[19]_i_31_n_0\
);
@@ -7153,9 +7153,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][19]\,
I1 => \data_rw_o_reg_n_0_[22][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[21][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[20][19]\,
O => \axi_rdata[19]_i_32_n_0\
);
@@ -7166,9 +7166,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][19]\,
I1 => \data_rw_o_reg_n_0_[10][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \s_datao_fmc1[0]\(19),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
O => \axi_rdata[19]_i_33_n_0\
);
\axi_rdata[19]_i_34\: unisim.vcomponents.LUT6
@@ -7178,9 +7178,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][19]\,
I1 => \data_rw_o_reg_n_0_[34][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[33][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[32][19]\,
O => \axi_rdata[19]_i_34_n_0\
);
@@ -7191,9 +7191,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][19]\,
I1 => \data_rw_o_reg_n_0_[90][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[89][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[88][19]\,
O => \axi_rdata[19]_i_35_n_0\
);
@@ -7204,9 +7204,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][19]\,
I1 => \data_rw_o_reg_n_0_[94][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[93][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[92][19]\,
O => \axi_rdata[19]_i_36_n_0\
);
@@ -7217,9 +7217,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][19]\,
I1 => \data_rw_o_reg_n_0_[86][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[85][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[84][19]\,
O => \axi_rdata[19]_i_37_n_0\
);
@@ -7230,9 +7230,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][19]\,
I1 => \data_rw_o_reg_n_0_[78][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \s_datao_fmc2[0]\(19),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
O => \axi_rdata[19]_i_39_n_0\
);
\axi_rdata[19]_i_42\: unisim.vcomponents.LUT6
@@ -7242,9 +7242,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][19]\,
I1 => \data_rw_o_reg_n_0_[98][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[97][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[96][19]\,
O => \axi_rdata[19]_i_42_n_0\
);
@@ -7255,9 +7255,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][19]\,
I1 => \data_rw_o_reg_n_0_[102][19]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[101][19]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[100][19]\,
O => \axi_rdata[19]_i_43_n_0\
);
@@ -7328,7 +7328,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[1]_i_14\: unisim.vcomponents.LUT6
generic map(
- INIT => X"4455FA004400FA00"
+ INIT => X"EE555000EE005000"
)
port map (
I0 => \^axi_rdata_reg[9]_0\,
@@ -7589,9 +7589,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \dac_ch_o_reg[0][31]\(20),
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[20]_i_14_n_0\
);
@@ -7640,9 +7640,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[20]_i_34_n_0\,
I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(20),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[20]_i_20_n_0\
);
@@ -7652,21 +7652,21 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
)
port map (
I0 => \data_rw_o_reg_n_0_[11][20]\,
- I1 => \^axi_rdata_reg[22]_0\,
+ I1 => \^axi_rdata_reg[22]_1\,
I2 => \data_rw_o_reg_n_0_[10][20]\,
- I3 => \^axi_rdata_reg[22]_1\,
+ I3 => \^axi_rdata_reg[22]_0\,
I4 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[20]_i_23_n_0\
);
\axi_rdata[20]_i_24\: unisim.vcomponents.LUT4
generic map(
- INIT => X"C800"
+ INIT => X"0080"
)
port map (
- I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[22]_1\,
- I2 => \data_rw_o_reg_n_0_[3][20]\,
- I3 => \^axi_rdata_reg[22]_0\,
+ I0 => \^axi_rdata_reg[22]_1\,
+ I1 => \data_rw_o_reg_n_0_[3][20]\,
+ I2 => \^axi_rdata_reg[22]_0\,
+ I3 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[20]_i_24_n_0\
);
\axi_rdata[20]_i_25\: unisim.vcomponents.LUT6
@@ -7676,9 +7676,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][20]\,
I1 => \data_rw_o_reg_n_0_[98][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[97][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[96][20]\,
O => \axi_rdata[20]_i_25_n_0\
);
@@ -7689,9 +7689,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][20]\,
I1 => \data_rw_o_reg_n_0_[102][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[101][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[100][20]\,
O => \axi_rdata[20]_i_26_n_0\
);
@@ -7700,9 +7700,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"A808"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \data_rw_o_reg_n_0_[78][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \data_rw_o_reg_n_0_[79][20]\,
O => \axi_rdata[20]_i_27_n_0\
);
@@ -7713,9 +7713,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][20]\,
I1 => \data_rw_o_reg_n_0_[94][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[93][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[92][20]\,
O => \axi_rdata[20]_i_31_n_0\
);
@@ -7726,9 +7726,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][20]\,
I1 => \data_rw_o_reg_n_0_[90][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[89][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[88][20]\,
O => \axi_rdata[20]_i_32_n_0\
);
@@ -7739,9 +7739,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][20]\,
I1 => \data_rw_o_reg_n_0_[86][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[85][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[84][20]\,
O => \axi_rdata[20]_i_33_n_0\
);
@@ -7752,9 +7752,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][20]\,
I1 => \data_rw_o_reg_n_0_[34][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[33][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[32][20]\,
O => \axi_rdata[20]_i_34_n_0\
);
@@ -7765,9 +7765,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][20]\,
I1 => \data_rw_o_reg_n_0_[26][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[25][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[24][20]\,
O => \axi_rdata[20]_i_35_n_0\
);
@@ -7778,9 +7778,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][20]\,
I1 => \data_rw_o_reg_n_0_[30][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[29][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[28][20]\,
O => \axi_rdata[20]_i_36_n_0\
);
@@ -7791,9 +7791,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][20]\,
I1 => \data_rw_o_reg_n_0_[18][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[17][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[16][20]\,
O => \axi_rdata[20]_i_37_n_0\
);
@@ -7804,9 +7804,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][20]\,
I1 => \data_rw_o_reg_n_0_[22][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[21][20]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[20][20]\,
O => \axi_rdata[20]_i_38_n_0\
);
@@ -7867,9 +7867,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \dac_ch_o_reg[0][31]\(21),
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[21]_i_14_n_0\
);
@@ -7918,9 +7918,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[21]_i_34_n_0\,
I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(21),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[21]_i_20_n_0\
);
@@ -7930,21 +7930,21 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
)
port map (
I0 => \data_rw_o_reg_n_0_[11][21]\,
- I1 => \^axi_rdata_reg[22]_0\,
+ I1 => \^axi_rdata_reg[22]_1\,
I2 => \data_rw_o_reg_n_0_[10][21]\,
- I3 => \^axi_rdata_reg[22]_1\,
+ I3 => \^axi_rdata_reg[22]_0\,
I4 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[21]_i_23_n_0\
);
\axi_rdata[21]_i_24\: unisim.vcomponents.LUT4
generic map(
- INIT => X"C800"
+ INIT => X"C888"
)
port map (
I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[22]_1\,
+ I1 => \^axi_rdata_reg[22]_0\,
I2 => \data_rw_o_reg_n_0_[3][21]\,
- I3 => \^axi_rdata_reg[22]_0\,
+ I3 => \^axi_rdata_reg[22]_1\,
O => \axi_rdata[21]_i_24_n_0\
);
\axi_rdata[21]_i_25\: unisim.vcomponents.LUT6
@@ -7954,9 +7954,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][21]\,
I1 => \data_rw_o_reg_n_0_[98][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[97][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[96][21]\,
O => \axi_rdata[21]_i_25_n_0\
);
@@ -7967,9 +7967,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][21]\,
I1 => \data_rw_o_reg_n_0_[102][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[101][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[100][21]\,
O => \axi_rdata[21]_i_26_n_0\
);
@@ -7978,9 +7978,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"A808"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \data_rw_o_reg_n_0_[78][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \data_rw_o_reg_n_0_[79][21]\,
O => \axi_rdata[21]_i_27_n_0\
);
@@ -7991,9 +7991,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][21]\,
I1 => \data_rw_o_reg_n_0_[94][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[93][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[92][21]\,
O => \axi_rdata[21]_i_31_n_0\
);
@@ -8004,9 +8004,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][21]\,
I1 => \data_rw_o_reg_n_0_[90][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[89][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[88][21]\,
O => \axi_rdata[21]_i_32_n_0\
);
@@ -8017,9 +8017,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][21]\,
I1 => \data_rw_o_reg_n_0_[86][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[85][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[84][21]\,
O => \axi_rdata[21]_i_33_n_0\
);
@@ -8030,9 +8030,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][21]\,
I1 => \data_rw_o_reg_n_0_[34][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[33][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[32][21]\,
O => \axi_rdata[21]_i_34_n_0\
);
@@ -8043,9 +8043,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][21]\,
I1 => \data_rw_o_reg_n_0_[26][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[25][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[24][21]\,
O => \axi_rdata[21]_i_35_n_0\
);
@@ -8056,9 +8056,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][21]\,
I1 => \data_rw_o_reg_n_0_[30][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[29][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[28][21]\,
O => \axi_rdata[21]_i_36_n_0\
);
@@ -8069,9 +8069,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][21]\,
I1 => \data_rw_o_reg_n_0_[18][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[17][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[16][21]\,
O => \axi_rdata[21]_i_37_n_0\
);
@@ -8082,9 +8082,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][21]\,
I1 => \data_rw_o_reg_n_0_[22][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[21][21]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[20][21]\,
O => \axi_rdata[21]_i_38_n_0\
);
@@ -8145,9 +8145,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \dac_ch_o_reg[0][31]\(22),
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[22]_i_14_n_0\
);
@@ -8196,9 +8196,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[22]_i_34_n_0\,
I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \dac_ch_o_reg[0][31]_0\(22),
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \^axi_rdata_reg[23]_0\(3),
O => \axi_rdata[22]_i_20_n_0\
);
@@ -8208,21 +8208,21 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
)
port map (
I0 => \data_rw_o_reg_n_0_[11][22]\,
- I1 => \^axi_rdata_reg[22]_0\,
+ I1 => \^axi_rdata_reg[22]_1\,
I2 => \data_rw_o_reg_n_0_[10][22]\,
- I3 => \^axi_rdata_reg[22]_1\,
+ I3 => \^axi_rdata_reg[22]_0\,
I4 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[22]_i_23_n_0\
);
\axi_rdata[22]_i_24\: unisim.vcomponents.LUT4
generic map(
- INIT => X"4088"
+ INIT => X"0080"
)
port map (
- I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[22]_1\,
- I2 => \data_rw_o_reg_n_0_[3][22]\,
- I3 => \^axi_rdata_reg[22]_0\,
+ I0 => \^axi_rdata_reg[22]_1\,
+ I1 => \data_rw_o_reg_n_0_[3][22]\,
+ I2 => \^axi_rdata_reg[22]_0\,
+ I3 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[22]_i_24_n_0\
);
\axi_rdata[22]_i_25\: unisim.vcomponents.LUT6
@@ -8232,9 +8232,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[99][22]\,
I1 => \data_rw_o_reg_n_0_[98][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[97][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[96][22]\,
O => \axi_rdata[22]_i_25_n_0\
);
@@ -8245,9 +8245,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[103][22]\,
I1 => \data_rw_o_reg_n_0_[102][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[101][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[100][22]\,
O => \axi_rdata[22]_i_26_n_0\
);
@@ -8256,9 +8256,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"A808"
)
port map (
- I0 => \^axi_rdata_reg[22]_1\,
+ I0 => \^axi_rdata_reg[22]_0\,
I1 => \data_rw_o_reg_n_0_[78][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
+ I2 => \^axi_rdata_reg[22]_1\,
I3 => \data_rw_o_reg_n_0_[79][22]\,
O => \axi_rdata[22]_i_27_n_0\
);
@@ -8269,9 +8269,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[95][22]\,
I1 => \data_rw_o_reg_n_0_[94][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[93][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[92][22]\,
O => \axi_rdata[22]_i_31_n_0\
);
@@ -8282,9 +8282,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[91][22]\,
I1 => \data_rw_o_reg_n_0_[90][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[89][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[88][22]\,
O => \axi_rdata[22]_i_32_n_0\
);
@@ -8295,9 +8295,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[87][22]\,
I1 => \data_rw_o_reg_n_0_[86][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[85][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[84][22]\,
O => \axi_rdata[22]_i_33_n_0\
);
@@ -8308,9 +8308,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[35][22]\,
I1 => \data_rw_o_reg_n_0_[34][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[33][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[32][22]\,
O => \axi_rdata[22]_i_34_n_0\
);
@@ -8321,9 +8321,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[27][22]\,
I1 => \data_rw_o_reg_n_0_[26][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[25][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[24][22]\,
O => \axi_rdata[22]_i_35_n_0\
);
@@ -8334,9 +8334,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[31][22]\,
I1 => \data_rw_o_reg_n_0_[30][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[29][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[28][22]\,
O => \axi_rdata[22]_i_36_n_0\
);
@@ -8347,9 +8347,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[19][22]\,
I1 => \data_rw_o_reg_n_0_[18][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[17][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[16][22]\,
O => \axi_rdata[22]_i_37_n_0\
);
@@ -8360,9 +8360,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[23][22]\,
I1 => \data_rw_o_reg_n_0_[22][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
+ I2 => \^axi_rdata_reg[22]_0\,
I3 => \data_rw_o_reg_n_0_[21][22]\,
- I4 => \^axi_rdata_reg[22]_0\,
+ I4 => \^axi_rdata_reg[22]_1\,
I5 => \data_rw_o_reg_n_0_[20][22]\,
O => \axi_rdata[22]_i_38_n_0\
);
@@ -8492,13 +8492,13 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[23]_i_25\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0080"
+ INIT => X"C888"
)
port map (
- I0 => \^axi_rdata_reg[23]_0\(0),
- I1 => \data_rw_o_reg_n_0_[3][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \^axi_rdata_reg[23]_0\(2),
+ I0 => \^axi_rdata_reg[23]_0\(2),
+ I1 => \^axi_rdata_reg[23]_0\(1),
+ I2 => \data_rw_o_reg_n_0_[3][23]\,
+ I3 => \^axi_rdata_reg[23]_0\(0),
O => \axi_rdata[23]_i_25_n_0\
);
\axi_rdata[23]_i_26\: unisim.vcomponents.LUT6
@@ -8924,15 +8924,15 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[24]_i_9\: unisim.vcomponents.LUT6
generic map(
- INIT => X"BB88B888B888B888"
+ INIT => X"88888888B8888888"
)
port map (
I0 => \axi_rdata[24]_i_17_n_0\,
I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][24]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
+ I2 => \^axi_rdata_reg[23]_0\(0),
+ I3 => \data_rw_o_reg_n_0_[3][24]\,
+ I4 => \^axi_rdata_reg[23]_0\(1),
+ I5 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[24]_i_9_n_0\
);
\axi_rdata[25]_i_1\: unisim.vcomponents.LUT4
@@ -9165,7 +9165,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[25]_i_9\: unisim.vcomponents.LUT6
generic map(
- INIT => X"BB88B88888888888"
+ INIT => X"BB88B888B888B888"
)
port map (
I0 => \axi_rdata[25]_i_17_n_0\,
@@ -9406,7 +9406,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[26]_i_9\: unisim.vcomponents.LUT6
generic map(
- INIT => X"BB88B88888888888"
+ INIT => X"BB88B888B888B888"
)
port map (
I0 => \axi_rdata[26]_i_17_n_0\,
@@ -9888,7 +9888,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[28]_i_9\: unisim.vcomponents.LUT6
generic map(
- INIT => X"8B888888B888B888"
+ INIT => X"BB88B888B888B888"
)
port map (
I0 => \axi_rdata[28]_i_17_n_0\,
@@ -10129,15 +10129,15 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[29]_i_9\: unisim.vcomponents.LUT6
generic map(
- INIT => X"BB88B88888888888"
+ INIT => X"88888888B8888888"
)
port map (
I0 => \axi_rdata[29]_i_17_n_0\,
I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][29]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
+ I2 => \^axi_rdata_reg[23]_0\(0),
+ I3 => \data_rw_o_reg_n_0_[3][29]\,
+ I4 => \^axi_rdata_reg[23]_0\(1),
+ I5 => \^axi_rdata_reg[23]_0\(2),
O => \axi_rdata[29]_i_9_n_0\
);
\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
@@ -10155,15 +10155,15 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[2]_i_14\: unisim.vcomponents.LUT6
generic map(
- INIT => X"4455FA004400FA00"
+ INIT => X"00000000F8C83808"
)
port map (
- I0 => \^axi_rdata_reg[9]_0\,
- I1 => \data_rw_o_reg_n_0_[3][2]\,
- I2 => gem_status_vector_i(2),
- I3 => \^axi_rdata_reg[2]_0\,
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_ins_reg[3]\(2),
+ I0 => \s_ins_reg[3]\(2),
+ I1 => \^axi_rdata_reg[2]_1\,
+ I2 => \^axi_rdata_reg[2]_0\,
+ I3 => gem_status_vector_i(2),
+ I4 => \data_rw_o_reg_n_0_[3][2]\,
+ I5 => \^axi_rdata_reg[9]_0\,
O => \axi_rdata[2]_i_14_n_0\
);
\axi_rdata[2]_i_17\: unisim.vcomponents.LUT6
@@ -10628,7 +10628,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[30]_i_9\: unisim.vcomponents.LUT6
generic map(
- INIT => X"8B888888B888B888"
+ INIT => X"BB88B888B888B888"
)
port map (
I0 => \axi_rdata[30]_i_17_n_0\,
@@ -10651,15 +10651,15 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[31]_i_10\: unisim.vcomponents.LUT6
generic map(
- INIT => X"88888888B8888888"
+ INIT => X"BB88B888B888B888"
)
port map (
I0 => \axi_rdata[31]_i_18_n_0\,
I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \data_rw_o_reg_n_0_[3][31]\,
- I4 => \^axi_rdata_reg[23]_0\(1),
- I5 => \^axi_rdata_reg[23]_0\(2),
+ I2 => \^axi_rdata_reg[23]_0\(2),
+ I3 => \^axi_rdata_reg[23]_0\(1),
+ I4 => \data_rw_o_reg_n_0_[3][31]\,
+ I5 => \^axi_rdata_reg[23]_0\(0),
O => \axi_rdata[31]_i_10_n_0\
);
\axi_rdata[31]_i_12\: unisim.vcomponents.LUT6
@@ -11418,7 +11418,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[5]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"44C800C8"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[9]_0\,
@@ -11673,7 +11673,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[6]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"CC408840"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[9]_0\,
@@ -11928,7 +11928,7 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
);
\axi_rdata[7]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"CC408840"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[9]_0\,
@@ -12186,23 +12186,23 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[12]_1\,
+ I0 => \^axi_rdata_reg[12]_0\,
I1 => \s_datao_fmc1[4]\(0),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^axi_rdata_reg[9]_0\,
I4 => \axi_rdata[8]_i_33_n_0\,
O => \axi_rdata[8]_i_13_n_0\
);
\axi_rdata[8]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"44C800C8"
+ INIT => X"0000B800"
)
port map (
- I0 => \^axi_rdata_reg[9]_0\,
+ I0 => \data_rw_o_reg_n_0_[3][8]\,
I1 => \^axi_rdata_reg[12]_0\,
I2 => gem_status_vector_i(8),
I3 => \^axi_rdata_reg[12]_1\,
- I4 => \data_rw_o_reg_n_0_[3][8]\,
+ I4 => \^axi_rdata_reg[9]_0\,
O => \axi_rdata[8]_i_14_n_0\
);
\axi_rdata[8]_i_17\: unisim.vcomponents.LUT6
@@ -12212,9 +12212,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[8]_i_34_n_0\,
I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \dac_ch_o_reg[0][31]_0\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^axi_rdata_reg[10]_0\,
O => \axi_rdata[8]_i_17_n_0\
);
@@ -12225,9 +12225,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[8]_i_37_n_0\,
I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \s_datao_fmc2[4]\(0),
- I4 => \^axi_rdata_reg[12]_0\,
+ I4 => \^axi_rdata_reg[12]_1\,
O => \axi_rdata[8]_i_19_n_0\
);
\axi_rdata[8]_i_23\: unisim.vcomponents.LUT4
@@ -12235,9 +12235,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[12]_0\,
+ I0 => \^axi_rdata_reg[12]_1\,
I1 => \dac_ch_o_reg[0][31]\(8),
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \^axi_rdata_reg[9]_0\,
O => \axi_rdata[8]_i_23_n_0\
);
@@ -12248,9 +12248,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]\(8),
I1 => \^[2].[2].s_reqs_reg[10][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]\(8),
O => \axi_rdata[8]_i_29_n_0\
);
@@ -12261,9 +12261,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]\(8),
I1 => \^[3].[2].s_reqs_reg[14][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]\(8),
O => \axi_rdata[8]_i_30_n_0\
);
@@ -12274,9 +12274,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^q\(8),
I1 => \^[0].[2].s_reqs_reg[2][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]\(8),
O => \axi_rdata[8]_i_31_n_0\
);
@@ -12287,9 +12287,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]\(8),
I1 => \^[1].[2].s_reqs_reg[6][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]\(8),
O => \axi_rdata[8]_i_32_n_0\
);
@@ -12300,9 +12300,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][8]\,
I1 => \data_rw_o_reg_n_0_[10][8]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc1[0]\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[8]_i_33_n_0\
);
\axi_rdata[8]_i_34\: unisim.vcomponents.LUT6
@@ -12312,9 +12312,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]\(8),
I1 => \^[4].[2].s_reqs_reg[18][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]\(8),
O => \axi_rdata[8]_i_34_n_0\
);
@@ -12325,9 +12325,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(8),
I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(8),
O => \axi_rdata[8]_i_35_n_0\
);
@@ -12338,9 +12338,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(8),
I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(8),
O => \axi_rdata[8]_i_36_n_0\
);
@@ -12351,9 +12351,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[0].[3].s_reqs_reg[3][value][11]\(8),
I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(8),
O => \axi_rdata[8]_i_37_n_0\
);
@@ -12364,9 +12364,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][8]\,
I1 => \data_rw_o_reg_n_0_[78][8]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc2[0]\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[8]_i_39_n_0\
);
\axi_rdata[8]_i_42\: unisim.vcomponents.LUT6
@@ -12376,9 +12376,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(8),
I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(8),
O => \axi_rdata[8]_i_42_n_0\
);
@@ -12389,9 +12389,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(8),
I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(8),
O => \axi_rdata[8]_i_43_n_0\
);
@@ -12465,22 +12465,22 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"04FF0400"
)
port map (
- I0 => \^axi_rdata_reg[12]_1\,
+ I0 => \^axi_rdata_reg[12]_0\,
I1 => \s_datao_fmc1[4]\(1),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^axi_rdata_reg[9]_0\,
I4 => \axi_rdata[9]_i_33_n_0\,
O => \axi_rdata[9]_i_13_n_0\
);
\axi_rdata[9]_i_14\: unisim.vcomponents.LUT5
generic map(
- INIT => X"44C800C8"
+ INIT => X"CCC888C8"
)
port map (
I0 => \^axi_rdata_reg[9]_0\,
- I1 => \^axi_rdata_reg[12]_0\,
+ I1 => \^axi_rdata_reg[12]_1\,
I2 => gem_status_vector_i(9),
- I3 => \^axi_rdata_reg[12]_1\,
+ I3 => \^axi_rdata_reg[12]_0\,
I4 => \data_rw_o_reg_n_0_[3][9]\,
O => \axi_rdata[9]_i_14_n_0\
);
@@ -12491,9 +12491,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[9]_i_34_n_0\,
I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \dac_ch_o_reg[0][31]_0\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^axi_rdata_reg[10]_0\,
O => \axi_rdata[9]_i_17_n_0\
);
@@ -12504,9 +12504,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \axi_rdata[9]_i_37_n_0\,
I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \s_datao_fmc2[4]\(1),
- I4 => \^axi_rdata_reg[12]_0\,
+ I4 => \^axi_rdata_reg[12]_1\,
O => \axi_rdata[9]_i_19_n_0\
);
\axi_rdata[9]_i_23\: unisim.vcomponents.LUT4
@@ -12514,9 +12514,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
INIT => X"0004"
)
port map (
- I0 => \^axi_rdata_reg[12]_0\,
+ I0 => \^axi_rdata_reg[12]_1\,
I1 => \dac_ch_o_reg[0][31]\(9),
- I2 => \^axi_rdata_reg[12]_1\,
+ I2 => \^axi_rdata_reg[12]_0\,
I3 => \^axi_rdata_reg[9]_0\,
O => \axi_rdata[9]_i_23_n_0\
);
@@ -12527,9 +12527,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]\(9),
I1 => \^[2].[2].s_reqs_reg[10][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]\(9),
O => \axi_rdata[9]_i_29_n_0\
);
@@ -12540,9 +12540,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]\(9),
I1 => \^[3].[2].s_reqs_reg[14][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]\(9),
O => \axi_rdata[9]_i_30_n_0\
);
@@ -12553,9 +12553,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^q\(9),
I1 => \^[0].[2].s_reqs_reg[2][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]\(9),
O => \axi_rdata[9]_i_31_n_0\
);
@@ -12566,9 +12566,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]\(9),
I1 => \^[1].[2].s_reqs_reg[6][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]\(9),
O => \axi_rdata[9]_i_32_n_0\
);
@@ -12579,9 +12579,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[11][9]\,
I1 => \data_rw_o_reg_n_0_[10][9]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc1[0]\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[9]_i_33_n_0\
);
\axi_rdata[9]_i_34\: unisim.vcomponents.LUT6
@@ -12591,9 +12591,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]\(9),
I1 => \^[4].[2].s_reqs_reg[18][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]\(9),
O => \axi_rdata[9]_i_34_n_0\
);
@@ -12604,9 +12604,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(9),
I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(9),
O => \axi_rdata[9]_i_35_n_0\
);
@@ -12617,9 +12617,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(9),
I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(9),
O => \axi_rdata[9]_i_36_n_0\
);
@@ -12630,9 +12630,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[0].[3].s_reqs_reg[3][value][11]\(9),
I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(9),
O => \axi_rdata[9]_i_37_n_0\
);
@@ -12643,9 +12643,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \data_rw_o_reg_n_0_[79][9]\,
I1 => \data_rw_o_reg_n_0_[78][9]\,
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \s_datao_fmc2[0]\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
O => \axi_rdata[9]_i_39_n_0\
);
\axi_rdata[9]_i_42\: unisim.vcomponents.LUT6
@@ -12655,9 +12655,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(9),
I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(9),
O => \axi_rdata[9]_i_42_n_0\
);
@@ -12668,9 +12668,9 @@ axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(9),
I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_0\,
+ I2 => \^axi_rdata_reg[12]_1\,
I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_1\,
+ I4 => \^axi_rdata_reg[12]_0\,
I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(9),
O => \axi_rdata[9]_i_43_n_0\
);
@@ -107280,14 +107280,14 @@ cmp_general_fmc1: entity work.system_design_fasec_hwtest_0_0_general_fmc
\FMC1_LA_P_b[32]\(21 downto 20) => FMC1_LA_P_b(32 downto 31),
\FMC1_LA_P_b[32]\(19 downto 0) => FMC1_LA_P_b(19 downto 0),
Q(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0\(11 downto 0),
- \axi_araddr_reg[2]_rep\ => cmp_axi4lite_slave_n_523,
- \axi_araddr_reg[2]_rep__0\ => cmp_axi4lite_slave_n_521,
- \axi_araddr_reg[2]_rep__1\ => cmp_axi4lite_slave_n_519,
+ \axi_araddr_reg[2]_rep\ => cmp_axi4lite_slave_n_524,
+ \axi_araddr_reg[2]_rep__0\ => cmp_axi4lite_slave_n_522,
+ \axi_araddr_reg[2]_rep__1\ => cmp_axi4lite_slave_n_518,
\axi_araddr_reg[2]_rep__2\ => cmp_axi4lite_slave_n_517,
\axi_araddr_reg[2]_rep__3\ => cmp_axi4lite_slave_n_220,
- \axi_araddr_reg[3]_rep\ => cmp_axi4lite_slave_n_524,
- \axi_araddr_reg[3]_rep__0\ => cmp_axi4lite_slave_n_522,
- \axi_araddr_reg[3]_rep__1\ => cmp_axi4lite_slave_n_518,
+ \axi_araddr_reg[3]_rep\ => cmp_axi4lite_slave_n_523,
+ \axi_araddr_reg[3]_rep__0\ => cmp_axi4lite_slave_n_521,
+ \axi_araddr_reg[3]_rep__1\ => cmp_axi4lite_slave_n_519,
\axi_araddr_reg[3]_rep__2\ => cmp_axi4lite_slave_n_516,
\axi_araddr_reg[3]_rep__3\ => cmp_axi4lite_slave_n_219,
\axi_araddr_reg[4]\(2 downto 0) => axi_araddr(4 downto 2),
@@ -107469,14 +107469,14 @@ cmp_general_fmc2: entity work.system_design_fasec_hwtest_0_0_general_fmc_0
\FMC2_LA_P_b[32]\(21 downto 20) => FMC2_LA_P_b(32 downto 31),
\FMC2_LA_P_b[32]\(19 downto 0) => FMC2_LA_P_b(19 downto 0),
Q(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15\(11 downto 0),
- \axi_araddr_reg[2]_rep\ => cmp_axi4lite_slave_n_523,
- \axi_araddr_reg[2]_rep__0\ => cmp_axi4lite_slave_n_521,
- \axi_araddr_reg[2]_rep__1\ => cmp_axi4lite_slave_n_519,
+ \axi_araddr_reg[2]_rep\ => cmp_axi4lite_slave_n_524,
+ \axi_araddr_reg[2]_rep__0\ => cmp_axi4lite_slave_n_522,
+ \axi_araddr_reg[2]_rep__1\ => cmp_axi4lite_slave_n_518,
\axi_araddr_reg[2]_rep__2\ => cmp_axi4lite_slave_n_517,
\axi_araddr_reg[2]_rep__3\ => cmp_axi4lite_slave_n_220,
- \axi_araddr_reg[3]_rep\ => cmp_axi4lite_slave_n_524,
- \axi_araddr_reg[3]_rep__0\ => cmp_axi4lite_slave_n_522,
- \axi_araddr_reg[3]_rep__1\ => cmp_axi4lite_slave_n_518,
+ \axi_araddr_reg[3]_rep\ => cmp_axi4lite_slave_n_523,
+ \axi_araddr_reg[3]_rep__0\ => cmp_axi4lite_slave_n_521,
+ \axi_araddr_reg[3]_rep__1\ => cmp_axi4lite_slave_n_519,
\axi_araddr_reg[3]_rep__2\ => cmp_axi4lite_slave_n_516,
\axi_araddr_reg[3]_rep__3\ => cmp_axi4lite_slave_n_219,
\axi_araddr_reg[4]_rep\ => cmp_axi4lite_slave_n_520,
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v
index 694357843077c5187df750cb64d332df6a787118..bc9decb51f34faddf375eab9cbd3e2c5c1679b3c 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Jun 21 08:34:34 2017
+// Date : Wed Oct 11 12:13:22 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl
index 27733e60d2d693c97bbcb4ab3692ab87b85e5d65..43c9d63cd1c6850f1f63a62935f0eb174c680639 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Jun 21 08:34:34 2017
+-- Date : Wed Oct 11 12:13:22 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd
similarity index 90%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd
index be34fac6ed5b7e38ecaae245ab14efeb592f2401..3b740503da23003c388ccda78085cd903c84d15c 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/axis_to_i2c_wbs.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/axis_to_i2c_wbs.vhd
@@ -5,7 +5,7 @@
-- Author : Pieter Van Trappen
-- Company : CERN TE-ABT-EC
-- Created : 2016-08-19
--- Last update: 2017-03-23
+-- Last update: 2017-10-11
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -36,6 +36,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
library hdl_lib;
use hdl_lib.main_pkg.all;
@@ -125,10 +128,10 @@ begin
-- Instantiation of components
cmp_axis_wbm_bridge : axis_wbm_bridge
generic map (
- g_AXI_AWIDTH => C_S00_AXI_ADDR_WIDTH,
- g_WB_AWIDTH => c_WB_AWIDTH,
- g_AXI_DWIDTH => C_S00_AXI_DATA_WIDTH,
- g_WB_DWIDTH => c_WB_DWIDTH,
+ g_AXI_AWIDTH => C_S00_AXI_ADDR_WIDTH,
+ g_WB_AWIDTH => c_WB_AWIDTH,
+ g_AXI_DWIDTH => C_S00_AXI_DATA_WIDTH,
+ g_WB_DWIDTH => c_WB_DWIDTH,
g_WB_BYTEADDR => true)
port map (
wb_clk_o => wb_clk_o,
@@ -194,9 +197,25 @@ begin
wb_rty_i <= '0';
-- I2C signals (signals have external pull-ups)
- i2c_scl_io <= 'Z' when scl_padoen_o = '1' else scl_pad_o;
- scl_pad_i <= i2c_scl_io;
- i2c_sda_io <= 'Z' when sda_padoen_o = '1' else sda_pad_o;
- sda_pad_i <= i2c_sda_io;
-
+ -- hard instantiation needed cause Vivado OOC run!
+ iobuf_i2c_scl : IOBUF
+ generic map (
+ DRIVE => 12,
+ IOSTANDARD => "DEFAULT",
+ SLEW => "FAST")
+ port map (
+ O => scl_pad_i,
+ IO => i2c_scl_io,
+ I => scl_pad_o,
+ T => scl_padoen_o);
+ iobuf_i2c_sda : IOBUF
+ generic map (
+ DRIVE => 12,
+ IOSTANDARD => "DEFAULT",
+ SLEW => "FAST")
+ port map (
+ O => sda_pad_i,
+ IO => i2c_sda_io,
+ I => sda_pad_o,
+ T => sda_padoen_o);
end rtl;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_bit_ctrl.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_bit_ctrl.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_byte_ctrl.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_byte_ctrl.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/modules/i2c_master_top.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/modules/i2c_master_top.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd
similarity index 99%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd
index 6a42dfb18e832a01ab6e4456cb6e446ed0ee32eb..276cbb5411b377d10b5b897a24a89d41d47da0c9 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_1/sim/axis_to_i2c_wbs_tb.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_1_2/sim/axis_to_i2c_wbs_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Pieter Van Trappen <pieter@>
-- Company :
-- Created : 2016-08-22
--- Last update: 2016-08-26
+-- Last update: 2017-08-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -312,7 +312,7 @@ begin -- architecture behavioural
end if;
v_bvalid_r := s00_axi_bvalid;
end process axi_slave_test_writeResponse;
-
+
end architecture behavioural;
-------------------------------------------------------------------------------
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
index 6d6777b60ec6921f9f576bf9bdd705e40b0bc0e1..ee33a82527ff3d43c4207855f0a61fb8cc1f01ef 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
@@ -294,8 +294,8 @@ begin
s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
-- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
- s_data(c_FASEC_BASE+6) <= x"594A1327"; -- tcl-script will put unix build time
- s_data(c_FASEC_BASE+7) <= x"2f398cc1"; -- tcl-script will put git commit id
+ s_data(c_FASEC_BASE+6) <= x"DEADBEE1"; -- tcl-script will put unix build time
+ s_data(c_FASEC_BASE+7) <= x"DEADBEE2"; -- tcl-script will put git commit id
-- copy in rw data, 'for generate' only possible with constants!
gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
gen_fasec : if c_FASECMEM(i).ro = '0' generate
@@ -452,4 +452,3 @@ begin
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready);
end rtl;
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
index e7467d927e91fe34403fad4a849698851eb7307c..dc5e3acf8985eb7232bf18f88df0c6ecf828ce8b 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
@@ -705,24 +705,24 @@
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
- <spirit:instanceName>axi_wb_i2c_master_0</spirit:instanceName>
- <spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.1.1"/>
+ <spirit:instanceName>wrc_1p_kintex7_0</spirit:instanceName>
+ <spirit:componentRef spirit:library="wrc" spirit:name="wrc_1p_kintex7" spirit:vendor="CERN" spirit:version="3.2.1"/>
<spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_axi_wb_i2c_master_0_1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_wrc_1p_kintex7_0_0</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
- <spirit:instanceName>axi_wb_i2c_master_2</spirit:instanceName>
- <spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.1.1"/>
+ <spirit:instanceName>axi_wb_i2c_master_0</spirit:instanceName>
+ <spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.1.2"/>
<spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_axi_wb_i2c_master_2_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_axi_wb_i2c_master_0_1</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
- <spirit:instanceName>wrc_1p_kintex7_0</spirit:instanceName>
- <spirit:componentRef spirit:library="wrc" spirit:name="wrc_1p_kintex7" spirit:vendor="CERN" spirit:version="3.2.1"/>
+ <spirit:instanceName>axi_wb_i2c_master_2</spirit:instanceName>
+ <spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.1.2"/>
<spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_wrc_1p_kintex7_0_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_axi_wb_i2c_master_2_0</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
@@ -843,8 +843,6 @@
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="m_axi_s2mm_aclk"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axis_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aclk"/>
- <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
- <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ACLK"/>
@@ -858,6 +856,8 @@
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="M00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ACLK"/>
+ <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
+ <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
</spirit:adHocConnection>
@@ -875,8 +875,6 @@
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="axi_resetn"/>
<spirit:internalPortReference spirit:componentRef="xadc_axis_fifo_adapter_0" spirit:portRef="AXIS_RESET_N"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aresetn"/>
- <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
- <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M05_ARESETN"/>
@@ -889,6 +887,8 @@
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ARESETN"/>
+ <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
+ <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
@@ -4992,6 +4992,12 @@
<spirit:addressOffset>0x40400000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
+ <spirit:segment>
+ <spirit:name>SEG_wrc_1p_kintex7_0_Reg</spirit:name>
+ <spirit:displayName>/wrc_1p_kintex7_0/s00_axi/Reg</spirit:displayName>
+ <spirit:addressOffset>0x80000000</spirit:addressOffset>
+ <spirit:range>64K</spirit:range>
+ </spirit:segment>
<spirit:segment>
<spirit:name>SEG_axi_wb_i2c_master_0_Reg</spirit:name>
<spirit:displayName>/axi_wb_i2c_master_0/s00_axi/Reg</spirit:displayName>
@@ -5004,12 +5010,6 @@
<spirit:addressOffset>0x43C00000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
- <spirit:segment>
- <spirit:name>SEG_wrc_1p_kintex7_0_Reg</spirit:name>
- <spirit:displayName>/wrc_1p_kintex7_0/s00_axi/Reg</spirit:displayName>
- <spirit:addressOffset>0x80000000</spirit:addressOffset>
- <spirit:range>64K</spirit:range>
- </spirit:segment>
<spirit:segment>
<spirit:name>SEG_fasec_hwtest_0_S00_AXI_reg</spirit:name>
<spirit:displayName>/fasec_hwtest_0/S00_AXI/S00_AXI_reg</spirit:displayName>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
index 6d468c743b61034ae778d391eca7e34afeb8265d..2f0f88a8f0590eb99958c46c1dce630df9d34539 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
@@ -2,9 +2,9 @@
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1498026522"/>
- <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1498026522"/>
- <Generation Name="SIMULATION" State="GENERATED" Timestamp="1498026522"/>
+ <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1507716626"/>
+ <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1507716626"/>
+ <Generation Name="SIMULATION" State="GENERATED" Timestamp="1507716626"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
diff --git a/FASEC_prototype.xpr b/FASEC_prototype.xpr
index 9cb79efcf5e93e394c149c245f4021bce5adb0ac..54eb29a9ea1dd32cc8785fdc9ce6b7f597ab4a71 100644
--- a/FASEC_prototype.xpr
+++ b/FASEC_prototype.xpr
@@ -10,12 +10,12 @@
<Option Name="Part" Val="xc7z030ffg676-2"/>
<Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../../local/EDA/xilinx_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
- <Option Name="CompiledLibDirModelSim" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/modelsim"/>
- <Option Name="CompiledLibDirQuesta" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/questa"/>
- <Option Name="CompiledLibDirIES" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/ies"/>
- <Option Name="CompiledLibDirVCS" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/vcs"/>
- <Option Name="CompiledLibDirRiviera" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/riviera"/>
- <Option Name="CompiledLibDirActivehdl" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/activehdl"/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
@@ -36,13 +36,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
- <Option Name="WTXSimExportSim" Val="83"/>
- <Option Name="WTModelSimExportSim" Val="83"/>
- <Option Name="WTQuestaExportSim" Val="83"/>
- <Option Name="WTIesExportSim" Val="83"/>
- <Option Name="WTVcsExportSim" Val="83"/>
- <Option Name="WTRivieraExportSim" Val="83"/>
- <Option Name="WTActivehdlExportSim" Val="83"/>
+ <Option Name="WTXSimExportSim" Val="84"/>
+ <Option Name="WTModelSimExportSim" Val="84"/>
+ <Option Name="WTQuestaExportSim" Val="84"/>
+ <Option Name="WTIesExportSim" Val="84"/>
+ <Option Name="WTVcsExportSim" Val="84"/>
+ <Option Name="WTRivieraExportSim" Val="84"/>
+ <Option Name="WTActivehdlExportSim" Val="84"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@@ -53,79 +53,65 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci">
- <Proxy FileSetName="system_design_axi_uartlite_0_0"/>
- </CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci">
- <Proxy FileSetName="system_design_axi_wb_i2c_master_2_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci">
+ <Proxy FileSetName="system_design_rst_processing_system7_0_100M_2"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci">
- <Proxy FileSetName="system_design_xlconcat_0_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci">
+ <Proxy FileSetName="system_design_processing_system7_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci">
<Proxy FileSetName="system_design_rst_wrc_1p_kintex7_0_62M_0"/>
</CompFileExtendedInfo>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci">
+ <Proxy FileSetName="system_design_axi_wb_i2c_master_0_1"/>
+ </CompFileExtendedInfo>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci">
+ <Proxy FileSetName="system_design_axi_wb_i2c_master_2_0"/>
+ </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xci">
<Proxy FileSetName="system_design_xlconstant_6_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci">
- <Proxy FileSetName="system_design_processing_system7_0_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci">
+ <Proxy FileSetName="system_design_axi_uartlite_0_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci">
- <Proxy FileSetName="system_design_fasec_hwtest_0_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci">
+ <Proxy FileSetName="system_design_wrc_1p_kintex7_0_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci">
- <Proxy FileSetName="system_design_rst_processing_system7_0_100M_2"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci">
+ <Proxy FileSetName="system_design_xlconcat_0_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci">
- <Proxy FileSetName="system_design_xbar_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci">
+ <Proxy FileSetName="system_design_axi_dma_0_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci">
- <Proxy FileSetName="system_design_xlconstant_3_2"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci">
+ <Proxy FileSetName="system_design_xadc_axis_fifo_adapter_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci">
<Proxy FileSetName="system_design_xadc_wiz_0_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci">
- <Proxy FileSetName="system_design_xadc_axis_fifo_adapter_0_0"/>
- </CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci">
- <Proxy FileSetName="system_design_axi_dma_0_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci">
+ <Proxy FileSetName="system_design_xlconstant_3_2"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci">
- <Proxy FileSetName="system_design_wrc_1p_kintex7_0_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci">
+ <Proxy FileSetName="system_design_xbar_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci">
- <Proxy FileSetName="system_design_axi_wb_i2c_master_0_1"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci">
+ <Proxy FileSetName="system_design_fasec_hwtest_0_0"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_fasec_hwtest_0_0.xml"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci">
<Proxy FileSetName="system_design_auto_pc_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_1/system_design_auto_pc_1.xci">
<Proxy FileSetName="system_design_auto_pc_1"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="sim/system_design_fasec_hwtest_0_0.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="FASEC_hwtest.srcs/constrs_1/new/hw_ip_constraints.xdc"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="synth/system_design_fasec_hwtest_0_0.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci">
<Proxy FileSetName="system_design_auto_pc_2"/>
</CompFileExtendedInfo>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design.hwh"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design_bd.tcl"/>
@@ -174,12 +160,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
- <FileSet Name="system_design_fasec_hwtest_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_design_fasec_hwtest_0_0">
- <Config>
- <Option Name="TopModule" Val="system_design_fasec_hwtest_0_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
<FileSet Name="system_design_rst_processing_system7_0_100M_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_design_rst_processing_system7_0_100M_2">
<Config>
<Option Name="TopModule" Val="system_design_rst_processing_system7_0_100M_2"/>
@@ -258,6 +238,12 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
+ <FileSet Name="system_design_fasec_hwtest_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_design_fasec_hwtest_0_0">
+ <Config>
+ <Option Name="TopModule" Val="system_design_fasec_hwtest_0_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
<FileSet Name="system_design_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_design_auto_pc_0">
<Config>
<Option Name="TopModule" Val="system_design_auto_pc_0"/>
@@ -299,12 +285,11 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
- <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="system_design_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_design_processing_system7_0_0" Part="xc7z030ffg676-2" ConstrsSet="system_design_processing_system7_0_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/system_design_processing_system7_0_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
@@ -313,13 +298,6 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
- <Run Id="system_design_fasec_hwtest_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_design_fasec_hwtest_0_0" Part="xc7z030ffg676-2" ConstrsSet="system_design_fasec_hwtest_0_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/system_design_fasec_hwtest_0_0_synth_1" IncludeInArchive="true">
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
- <Step Id="synth_design"/>
- </Strategy>
- <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
- </Run>
<Run Id="system_design_rst_processing_system7_0_100M_2_synth_1" Type="Ft3:Synth" SrcSet="system_design_rst_processing_system7_0_100M_2" Part="xc7z030ffg676-2" ConstrsSet="system_design_rst_processing_system7_0_100M_2" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/system_design_rst_processing_system7_0_100M_2_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
@@ -411,6 +389,15 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
+ <Run Id="system_design_fasec_hwtest_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_design_fasec_hwtest_0_0" Part="xc7z030ffg676-2" ConstrsSet="system_design_fasec_hwtest_0_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/system_design_fasec_hwtest_0_0_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ </Run>
<Run Id="system_design_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="system_design_auto_pc_0" Part="xc7z030ffg676-2" ConstrsSet="system_design_auto_pc_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/system_design_auto_pc_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
@@ -438,7 +425,7 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
@@ -451,7 +438,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream" PostStepTclHook="$PSRCDIR/tcl/copy_bitstream.tcl"/>
</Strategy>
- <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="system_design_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="system_design_processing_system7_0_0" Description="Default settings for Implementation." SynthRun="system_design_processing_system7_0_0_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
@@ -467,20 +453,6 @@
<Step Id="write_bitstream"/>
</Strategy>
</Run>
- <Run Id="system_design_fasec_hwtest_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="system_design_fasec_hwtest_0_0" Description="Default settings for Implementation." SynthRun="system_design_fasec_hwtest_0_0_synth_1" IncludeInArchive="false">
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
- <Step Id="init_design"/>
- <Step Id="opt_design"/>
- <Step Id="power_opt_design"/>
- <Step Id="place_design"/>
- <Step Id="post_place_power_opt_design"/>
- <Step Id="phys_opt_design"/>
- <Step Id="route_design"/>
- <Step Id="post_route_phys_opt_design"/>
- <Step Id="write_bitstream"/>
- </Strategy>
- </Run>
<Run Id="system_design_rst_processing_system7_0_100M_2_impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="system_design_rst_processing_system7_0_100M_2" Description="Default settings for Implementation." SynthRun="system_design_rst_processing_system7_0_100M_2_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
@@ -663,6 +635,22 @@
<Step Id="write_bitstream"/>
</Strategy>
</Run>
+ <Run Id="system_design_fasec_hwtest_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="system_design_fasec_hwtest_0_0" Description="Default settings for Implementation." SynthRun="system_design_fasec_hwtest_0_0_synth_1" IncludeInArchive="false">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
<Run Id="system_design_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="system_design_auto_pc_0" Description="Default settings for Implementation." SynthRun="system_design_auto_pc_0_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
diff --git a/ip_cores/cores b/ip_cores/cores
index 2c7828b3d72d4ef35ba550caf951a66651f8aa6b..c4a8f33c6ab5749a172660044e073c4a610e3f12 160000
--- a/ip_cores/cores
+++ b/ip_cores/cores
@@ -1 +1 @@
-Subproject commit 2c7828b3d72d4ef35ba550caf951a66651f8aa6b
+Subproject commit c4a8f33c6ab5749a172660044e073c4a610e3f12
diff --git a/ip_upgrade.log b/ip_upgrade.log
index 8a0e8008561dfdf86cc6e0ef6997b7c67a048bc5..1663272a39df35af3950d18606045cc64bd9864a 100644
--- a/ip_upgrade.log
+++ b/ip_upgrade.log
@@ -1,3 +1,66 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
+| Date : Wed Oct 11 12:10:04 2017
+| Host : lapte24154 running 64-bit openSUSE Leap 42.2
+| Command : upgrade_ip
+| Device : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the update of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.6 (Rev. 34)) to current project options.
+
+
+
+
+
+
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
+| Date : Wed Oct 11 12:10:04 2017
+| Host : lapte24154 running 64-bit openSUSE Leap 42.2
+| Command : upgrade_ip
+| Device : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_design_axi_wb_i2c_master_2_0 from cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5) to cern.ch:ip:axi_wb_i2c_master:3.1.2 (Rev. 6)
+
+
+
+
+
+
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
+| Date : Wed Oct 11 12:10:04 2017
+| Host : lapte24154 running 64-bit openSUSE Leap 42.2
+| Command : upgrade_ip
+| Device : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_1'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_1 from cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5) to cern.ch:ip:axi_wb_i2c_master:3.1.2 (Rev. 6)
+
+
+
+
+
+
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016