Zynq PS core and .xdc constraints modified for fasec V2; wb_i2c_master_2 added...
Zynq PS core and .xdc constraints modified for fasec V2; wb_i2c_master_2 added for mdio pullups - don't use in software
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- FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc 5 additions, 0 deletions..._prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
- FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef 0 additions, 0 deletions...e.srcs/sources_1/bd/system_design/hdl/system_design.hwdef
- FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd 1577 additions, 226 deletions...ype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
- FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd 36 additions, 2 deletions.../sources_1/bd/system_design/hdl/system_design_wrapper.vhd
- FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh 438 additions, 70 deletions...s/sources_1/bd/system_design/hw_handoff/system_design.hwh
- FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl 102 additions, 89 deletions...ources_1/bd/system_design/hw_handoff/system_design_bd.tcl
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp 0 additions, 0 deletions...gn/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml 6 additions, 6 deletions...gn/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v 1 addition, 1 deletion...em_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl 1 addition, 1 deletion...design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v 1 addition, 1 deletion...ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl 1 addition, 1 deletion...system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp 0 additions, 0 deletions...gn/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml 6 additions, 6 deletions...gn/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v 1 addition, 1 deletion...em_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl 1 addition, 1 deletion...design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v 1 addition, 1 deletion...ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl 1 addition, 1 deletion...system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v 14 additions, 11 deletions.../ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/synth/system_design_auto_pc_2.v 15 additions, 12 deletions...p/system_design_auto_pc_2/synth/system_design_auto_pc_2.v
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