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Created with Raphaël 2.2.015Mar2Oct23Sep24Jul9Apr1Aug25Jul26Jun2216Mar723Feb1612Jan20Dec1812Oct1121Jun2031May2415121113Apr1227Mar232221161514228Feb171015Dec30Nov292543224Oct20191813Sep31Aug3026329Jul27Update .ohwr.yamlmastermasterUpdate .ohwr.yamlUpdate .ohwr.yamlAdd .ohwr.yamlreadme updated ref. wrpcupdated readme; added petalinux-oe meta-user layer for referenceMerge branch 'FASECV2_fmcs_xadc_wrc_v20181' into masterupdated cores submodule to master branch, no changes; meanwhile white rabbit and new FMC external i2c successfully testedblock-design modified for testing FMC1 external i2c connection (to patch-panel):fasec_hwtest IP was old and obsolete, updated; all output files generatedporting Eino's project (thus 2016.4) to Vivado 2018.1, including:Use latest 2016 version of coresChecking PRSNT signals in submodules FASEC_hwtest, if FMC is not present interrupts are not generatedUpdated submodule FASEC_hwtest and generated new bitstreamUpdated with submodule FIDSIP that ORs the CMPin and extenedcmpin in hardware. This avoids problems with signals that are longer than the extended signalChanged subrepo hdl_lib to user userled fixUpdate ub hdl_lib submodulepower controller UCD90120 project files added to ./misc folderzynq ps i2c internal pullups removedZynq PS core and .xdc constraints modified for fasec V2; wb_i2c_master_2 added for mdio pullups - don't use in softwareafter synthesisfmcs_xadc_wrcfmcs_xadc_wrcfasec_hwtest updated cause of unwanted wrc signals to outputsafter synthesisxdc constraints updated for i2c signalsupdate of axi_wb_i2c_master modules again to support vivado i2c interface (iic)update of axi_wb_i2c_master modules because of tricell errors resulting in broken i2c; still to be done for wrcfasec_hwtest module bugfix; set_registers tcl script changed because of out of context IPs; after synthesisafter synthesis; using out of context synthesis now btwfasec_hwtest submodule update, negated comparators inputreadme and tcl files updatedafter synthesis with new lm32 wswrpc submodule updated for new lm32 sw, confirmed workingFMC1_GP1_i now connected to wrpc pps instead of dmtd; after synthesisafter synthesisfasec_hwtest from cores submodules update, ledblink 100ms etc.after synthesissubmodule cores updated for fasec_hwtestafter synthesis, I should really start putting timing constraints..submodule cores updated for fasec_hwtest v3.2.2, outputs generatedoutput products generated