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DIOT Zynq Ultrascale-based System Board
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DIOT Zynq Ultrascale-based System Board
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first-gateware-version
#257
· opened
Mar 15, 2022
by
Alén Arias Vázquez
Major
CLOSED
1
1
updated
Sep 21, 2022
Replace C100 with higher voltage rating
#231
· opened
Feb 04, 2021
by
Grzegorz Daniluk
v2.0
Done
Major
CLOSED
1
updated
Sep 15, 2021
The reset pin of the flash chips is connected to ps_por_b which is 3.3V while the flash are 1.8V
#230
· opened
Dec 14, 2020
by
Grzegorz Daniluk
v2.0
Done
Major
CLOSED
0
updated
Sep 14, 2021
[L14] X:124mm Y:30mm move SFP.MGT_Tx_P/N so that it lays fully over continuous GND in L13.
#228
· opened
Sep 04, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Sep 08, 2020
[fpga-pl-mgts] SATA_TX vs SATAC_TX have P/N swapped!
#227
· opened
Aug 31, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Sep 08, 2020
[L1] IC22, IC32 layout
3 of 3 tasks completed
#225
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 31, 2020
check if SFP inserted in the cate will not conflict with the front panel extraction handle
#218
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
4
updated
Aug 31, 2020
[L14] X:199.75mm Y:25.825mm potentially unrouted net MGT2_RxC_P - consisting of 2 traces barely connected together
#217
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
1
updated
Aug 31, 2020
FMC mounting holes should be connected to chassis ground (not signal GND)
#206
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
4
updated
Aug 28, 2020
power via hole size
#201
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
stitch gnd top and bottom polygons next to DDR chips
#199
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Major
CLOSED
1
updated
Aug 28, 2020
polygons on signal layer
#198
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
8
updated
Jul 21, 2021
P1V8 power plane
#197
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Major
CLOSED
2
updated
Sep 01, 2020
create xsignals between DDR chips for command signal group
#195
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
2
updated
Sep 02, 2020
polygon pour cutout beneat FPGA and FMC connector
#194
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Major
CLOSED
1
updated
Aug 28, 2020
[L14] 3 ESD strips on the lower edge are not connected to anything
#191
· opened
Jul 02, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
1
updated
Aug 28, 2020
[L14] check all MGT diff pairs routing to ensure they have smooth corners
#190
· opened
Jul 02, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
[L12] X:109mm Y:50mm MGT_CLKREF.CLK_P/N have sharp corners
#188
· opened
Jul 02, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
[L7] some clock lines near IC4 are missing GND return vias (like it's done for 7_PE_CLK_P/N)
3 of 3 tasks completed
#186
· opened
Jul 02, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
[L5] X:116mm Y:39mm sharp corner on otherwise smooth-cornered transceiver lane
#185
· opened
Jul 02, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 28, 2020
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