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DIOT Zynq Ultrascale-based System Board
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[fpga-bank-87-88] FPGA_CLK_OUT can't be LVDS out from HD bank
#138
· opened
Mar 22, 2020
by
Grzegorz Daniluk
Done
Major
CLOSED
5
updated
Apr 02, 2020
[Cpcis_connectors_P4_P5_P6] indexing of LVDS
#26
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Apr 02, 2020
[power-supply-1] remove no ERC directives from valid signal lines
#116
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Apr 02, 2020
[BOM] Reducing Bill-Of-Materials
19 of 19 tasks completed
#11
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
7
updated
Mar 30, 2020
[power-supply-2] P3V3 output has a label “5A” while it can deliver 2A max
#128
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
16
updated
Mar 30, 2020
[clocks] Si5341 revision
#46
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
6
updated
Mar 30, 2020
[General] Two Altium variants of this design
#5
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
9
updated
Mar 30, 2020
[Cpcis_connectors_P1_P2_P3] indexing of LVDS
#18
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
6
updated
Mar 30, 2020
[clocks] UsrCLK1/UsrCLK2 clocking scheme
#47
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 30, 2020
[clocks] bias network shall be added on FPGA-PL.CLKREF
#45
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
4
updated
Mar 30, 2020
[fpga-config] Power IC27 from P5VREG (see screenshot)
#74
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 30, 2020
[fpga-config] IC27 configuration
#75
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 30, 2020
[power-supply-1] Split the use of 5VREG and P5V0_MP
#117
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 30, 2020
[ddr4-pl] decoupling caps
#111
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
5
updated
Mar 30, 2020
FMC_PG_C2M is pulled up twice: in fmc-connector and fpga-bank-27-28 sheets
#137
· opened
Mar 19, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 29, 2020
[power-supply-3] IC32, IC22 feedback dividers
#132
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
6
updated
Mar 29, 2020
[power-supply-3] VTT generation for DDR4
#131
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
6
updated
Mar 29, 2020
[fpga-bank-27-28] remove FMC.CLK_DIR and FMC.CLK_BIDIR_2/3
#98
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
4
updated
Mar 29, 2020
[fpga-bank-27-28] many "no ERC" directives
#97
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
4
updated
Mar 29, 2020
[fpga-config] resistance for Q1 (RTC crystal) should be 4.7M
#72
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
6
updated
Mar 29, 2020
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