[clocks] UsrCLK1/UsrCLK2 clocking scheme
According to the specification, 2 User clocks (UsrCLK1/UsrCLK2) should be provided from Si5341 through fanouts to CPCIs backplane: UsrCLK1 to slots 1-4; UsrCLK2 to slots 5-9. This is not the case in current schematics, where 1 clock (cpcis_clk_in_1_p/n) goes through fanout to all slots (1-9).