[clocks] bias network shall be added on FPGA-PL.CLKREF
A bias network shall be added on FPGA-PL.CLKREF pair to ensure compatibility with SSTL12 standard. See Xilinx AR #66786.
A bias network shall be added on FPGA-PL.CLKREF pair to ensure compatibility with SSTL12 standard. See Xilinx AR #66786.