[fpga-config] IC27 configuration
TH0 and TH1 are open and TOL = GND -> input threshold = 0.5V. Our voltage divider will pass that when P3V3 = 0.9V which doesn't seem right, I think we should be using 11.3k and 2.15k to get 0.5V when the input is 3.3*0.95.
CDLY2 capacitor should have a larger value such that it's guaranteed to be deasserted after the PS_POR_B.