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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit a23c7dbd authored by Adrian Byszuk's avatar Adrian Byszuk
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GW: add RTL support for Chip2Chip/Aurora subsystem

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gw/projects/diot_v2/src/c2c_link.vhd 0 → 100644
View file @ a23c7dbd
-------------------------------------------------------------------------------
--! @file c2c_link.vhd
--! @author Adrian Byszuk
--! @copyright CERN SY-EPC-CCE
--! @date 05-07-2022
--! @brief Chip2Chip link control and status
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief Chip2Chip link control and status
--! @details
--! Provides software with basic control and diagnostic capabilities.
--! Intended to be easily integrated with Xilinx Block Design.
--! Supports up to 8 links, which is maximum in a standard DIOT crate.
entity c2c_link is
generic (
addr_width_g : positive := 6
);
port (
--! @name AXI4Lite slave bus (naming convention compatible with Xilinx IP Integrator)
s_axi_aclk : in std_ulogic;
s_axi_aresetn : in std_ulogic;
--
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_awaddr : in std_logic_vector(addr_width_g-1 downto 0);
--
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
--
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
--
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_araddr : in std_logic_vector(addr_width_g-1 downto 0);
--
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
--! @name Aurora/Chip2Chip signals (for meaning of some signals see the IP documentation)
--! Output reset vector is split to avoid stupid block design slicing
reset_0 : out std_logic; --! PMA reset to link 0
reset_1 : out std_logic; --! PMA reset to link 1
reset_2 : out std_logic; --! PMA reset to link 2
reset_3 : out std_logic; --! PMA reset to link 3
reset_4 : out std_logic; --! PMA reset to link 4
reset_5 : out std_logic; --! PMA reset to link 5
reset_6 : out std_logic; --! PMA reset to link 6
reset_7 : out std_logic; --! PMA reset to link 7
channel_up : in std_logic_vector(7 downto 0); --! Aurora channel_up status
hard_err : in std_logic_vector(7 downto 0); --! Aurora hard_err status
gt_pll_lock : in std_logic_vector(7 downto 0); --! MGT PLL lock status
link_status : in std_logic_vector(7 downto 0); --! Chip2Chip link up status
config_error : in std_logic_vector(7 downto 0); --! Chip2Chip endpoint config error
link_error : in std_logic_vector(7 downto 0); --! Chip2Chip link error
multi_bit_error : in std_logic_vector(7 downto 0) --! Chip2Chip multi_bit error status
);
end entity c2c_link;
--! RTL implementation of c2c_link
architecture rtl of c2c_link is
--! @name Attributes required to silence Vivado BD GUI
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF reset_0: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_0: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_1: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_1: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_2: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_2: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_3: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_3: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_4: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_4: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_5: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_5: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_6: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_6: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_7: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_7: SIGNAL is "POLARITY ACTIVE_HIGH";
--! @}
begin
--! Wishbone registers (autogenerated)
x_regs : entity work.link_ctrl_regs
port map (
aclk => s_axi_aclk,
areset_n => s_axi_aresetn,
awvalid => s_axi_awvalid,
awready => s_axi_awready,
awaddr => s_axi_awaddr,
awprot => "000",
wvalid => s_axi_wvalid,
wready => s_axi_wready,
wdata => s_axi_wdata,
wstrb => s_axi_wstrb,
bvalid => s_axi_bvalid,
bready => s_axi_bready,
bresp => s_axi_bresp,
arvalid => s_axi_arvalid,
arready => s_axi_arready,
araddr => s_axi_araddr,
arprot => "000",
rvalid => s_axi_rvalid,
rready => s_axi_rready,
rdata => s_axi_rdata,
rresp => s_axi_rresp,
link_0_ctrl_reset_o => reset_0,
link_0_status_channel_up_i => channel_up(0),
link_0_status_hard_err_i => hard_err(0),
link_0_status_gt_pll_lock_i => gt_pll_lock(0),
link_0_status_link_status_i => link_status(0),
link_0_status_config_error_i => config_error(0),
link_0_status_link_error_i => link_error(0),
link_0_status_multi_bit_error_i => multi_bit_error(0),
link_1_ctrl_reset_o => reset_1,
link_1_status_channel_up_i => channel_up(1),
link_1_status_hard_err_i => hard_err(1),
link_1_status_gt_pll_lock_i => gt_pll_lock(1),
link_1_status_link_status_i => link_status(1),
link_1_status_config_error_i => config_error(1),
link_1_status_link_error_i => link_error(1),
link_1_status_multi_bit_error_i => multi_bit_error(1),
link_2_ctrl_reset_o => reset_2,
link_2_status_channel_up_i => channel_up(2),
link_2_status_hard_err_i => hard_err(2),
link_2_status_gt_pll_lock_i => gt_pll_lock(2),
link_2_status_link_status_i => link_status(2),
link_2_status_config_error_i => config_error(2),
link_2_status_link_error_i => link_error(2),
link_2_status_multi_bit_error_i => multi_bit_error(2),
link_3_ctrl_reset_o => reset_3,
link_3_status_channel_up_i => channel_up(3),
link_3_status_hard_err_i => hard_err(3),
link_3_status_gt_pll_lock_i => gt_pll_lock(3),
link_3_status_link_status_i => link_status(3),
link_3_status_config_error_i => config_error(3),
link_3_status_link_error_i => link_error(3),
link_3_status_multi_bit_error_i => multi_bit_error(3),
link_4_ctrl_reset_o => reset_4,
link_4_status_channel_up_i => channel_up(4),
link_4_status_hard_err_i => hard_err(4),
link_4_status_gt_pll_lock_i => gt_pll_lock(4),
link_4_status_link_status_i => link_status(4),
link_4_status_config_error_i => config_error(4),
link_4_status_link_error_i => link_error(4),
link_4_status_multi_bit_error_i => multi_bit_error(4),
link_5_ctrl_reset_o => reset_5,
link_5_status_channel_up_i => channel_up(5),
link_5_status_hard_err_i => hard_err(5),
link_5_status_gt_pll_lock_i => gt_pll_lock(5),
link_5_status_link_status_i => link_status(5),
link_5_status_config_error_i => config_error(5),
link_5_status_link_error_i => link_error(5),
link_5_status_multi_bit_error_i => multi_bit_error(5),
link_6_ctrl_reset_o => reset_6,
link_6_status_channel_up_i => channel_up(6),
link_6_status_hard_err_i => hard_err(6),
link_6_status_gt_pll_lock_i => gt_pll_lock(6),
link_6_status_link_status_i => link_status(6),
link_6_status_config_error_i => config_error(6),
link_6_status_link_error_i => link_error(6),
link_6_status_multi_bit_error_i => multi_bit_error(6),
link_7_ctrl_reset_o => reset_7,
link_7_status_channel_up_i => channel_up(7),
link_7_status_hard_err_i => hard_err(7),
link_7_status_gt_pll_lock_i => gt_pll_lock(7),
link_7_status_link_status_i => link_status(7),
link_7_status_config_error_i => config_error(7),
link_7_status_link_error_i => link_error(7),
link_7_status_multi_bit_error_i => multi_bit_error(7)
);
end architecture rtl;
gw/projects/diot_v2/src/c2c_link_regs.cheby 0 → 100644
View file @ a23c7dbd
memory-map:
bus: axi4-lite-32
name: link_ctrl_regs
description: Aurora link control/status
x-hdl:
bus-granularity: byte
children:
- repeat:
name: link
description: Data to be sent to DAC
count: 8
children:
- reg:
name: ctrl
description: Control register
width: 32
access: rw
type: unsigned
children:
- field:
name: reset
description: Reset the Aurora link
range: 0
preset: 0
x-hdl:
type: autoclear
- reg:
name: status
description: Status register
type: unsigned
width: 32
access: ro
children:
- field:
name: channel_up
description: Aurora channel is up and running
range: 0
- field:
name: hard_err
description: Aurora hard error - reset required
range: 1
- field:
name: gt_pll_lock
description: MGT PLL is locked
range: 2
- field:
name: link_status
description: Chip2Chip link is up and running
range: 3
- field:
name: config_error
description: Chip2Chip config error (see Xilinx PG067)
range: 4
- field:
name: link_error
description: Chip2Chip link error (see Xilinx PG067)
range: 5
- field:
name: multi_bit_error
description: Chip2Chip multi-bit error (see Xilinx PG067)
range: 6
gw/projects/diot_v2/src/c2c_link_regs.vhd 0 → 100644
View file @ a23c7dbd
This diff is collapsed.
gw/projects/diot_v2/src/ps2pl_glue.vhd
View file @ a23c7dbd
...@@ -50,11 +50,12 @@ entity ps2pl_glue is ...@@ -50,11 +50,12 @@ entity ps2pl_glue is
ps_emio_o : out std_logic_vector(15 downto 0); ps_emio_o : out std_logic_vector(15 downto 0);
ps_emio_i : in std_logic_vector(94 downto 0); ps_emio_i : in std_logic_vector(94 downto 0);
ps_emio_t_i : in std_logic_vector(15 downto 0); ps_emio_t_i : in std_logic_vector(15 downto 0);
ps_irq_o : out std_logic_vector(1 downto 0);
--! @name I2C bus IRQs --! @name I2C bus and other IRQs
wrflash_i2c_irq_i : in std_logic; wrflash_i2c_irq_i : in std_logic;
bckpl_i2c_irq_i : in std_logic; bckpl_i2c_irq_i : in std_logic;
aurora_dma_irq_i : in std_logic;
ps_irq_o : out std_logic_vector(2 downto 0);
--! @name Constants module --! @name Constants module
--! Addr of the PHY device(slave). A constant number --! Addr of the PHY device(slave). A constant number
...@@ -93,6 +94,7 @@ architecture Behavioral of ps2pl_glue is ...@@ -93,6 +94,7 @@ architecture Behavioral of ps2pl_glue is
ATTRIBUTE X_INTERFACE_INFO of ps_irq_o: SIGNAL is "xilinx.com:signal:interrupt:1.0 ps_irq_o INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO of ps_irq_o: SIGNAL is "xilinx.com:signal:interrupt:1.0 ps_irq_o INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO of wrflash_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 wrflash_i2c_irq_i INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO of wrflash_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 wrflash_i2c_irq_i INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO of bckpl_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 bckpl_i2c_irq_i INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO of bckpl_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 bckpl_i2c_irq_i INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO of aurora_dma_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 aurora_dma_irq_i INTERRUPT";
--! @} --! @}
-- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096 -- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
...@@ -187,6 +189,6 @@ begin ...@@ -187,6 +189,6 @@ begin
f_rst_t_o <= ps_emio_t_i(15); f_rst_t_o <= ps_emio_t_i(15);
-- I2C irqs -- I2C irqs
ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i; ps_irq_o <= aurora_dma_irq_i & bckpl_i2c_irq_i & wrflash_i2c_irq_i;
end Behavioral; end Behavioral;
gw/projects/diot_v2/src/run_cheby.sh 0 → 100755
View file @ a23c7dbd
#!/bin/sh
NAME="c2c_link_regs"
# commands must be executed from script directory, where both script and .cheby files are
cd "$(dirname "$(readlink -f "$0")")"
cheby --print-simple --gen-hdl=$NAME.vhd --gen-doc=$NAME.html -i $NAME.cheby
gw/projects/diot_v2/tcl/project_cfg.tcl
View file @ a23c7dbd
...@@ -4,7 +4,6 @@ set project_name "diot_v2" ...@@ -4,7 +4,6 @@ set project_name "diot_v2"
set entity_top "diot_v2_top" set entity_top "diot_v2_top"
# Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus] # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
set max_threads 8 set max_threads 8
set project_language "VHDL"
set lib_default xil_defaultlib set lib_default xil_defaultlib
# Common IP directory # Common IP directory
...@@ -20,6 +19,8 @@ add_vhdl_src ${lib_default} ../src/${entity_top}.vhd ...@@ -20,6 +19,8 @@ add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
# Vhdl Src # Vhdl Src
add_vhdl_src ${lib_default} ../src/ps2pl_glue.vhd add_vhdl_src ${lib_default} ../src/ps2pl_glue.vhd
add_vhdl_src ${lib_default} ../src/c2c_link_regs.vhd
add_vhdl_src ${lib_default} ../src/c2c_link.vhd
# Add Constraints # Add Constraints
add_constraint diot_v2.xdc add_constraint diot_v2.xdc
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