gw: cleanup glue logic and add Doxygen comments

96953ab8 · Adrian Byszuk · 4218388b · 4218388b · 96953ab8 · 96953ab8
Commit 96953ab8 authored Jun 30, 2022 by Adrian Byszuk
4 changed files
--- a/gw/projects/diot_v2/src/constants.vhd
+++ b/gw/projects/diot_v2/src/constants.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/28/2021 04:30:23 PM
-- Design Name:
-- Module Name: constants - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
--==============================================================================
--! Entity declaration for constants
--==============================================================================
-entity constants is
-    generic (
-        g_phyaddr           : integer := 9;
-        g_config_vector     : integer := 0;
-        g_config_valid      : integer := 0;
-        g_signal_detect     : integer := 1
-    );
-    port (
-        pl_clk_i            : in std_logic;
-        --! Vector indicating status. We need bits 0 and 1 of the vector
-        status_vector       : in std_logic_vector(15 downto 0);
-        --! Management clock, (<= 2.5MHz)
-        mdc_i               : in std_logic;
-          mdc_clk_led       : out std_logic;
-        --! Reset of the module, coming from PS
-        pl_resetn_i         : in std_logic;
-        reset_o             : out std_logic;
-        --! Autoneg
-        an_config_o         : out std_logic;
-        an_config_vec_o     : out std_logic_vector(15 downto 0);
-        tx_disable_o        : out std_logic;
-        --! EMIO GPIOs
-        p_pres_i            : in  std_logic_vector(1 downto 0);
-        pwr_cycle_req_o     : out std_logic;
-        bckpl_servmod_i     : in  std_logic_vector(7 downto 0);
-        bckpl_servmod_o     : out std_logic_vector(7 downto 0);
-        bckpl_servmod_t_o   : out std_logic_vector(7 downto 0);
-        bckpl_rst_n_o       : out std_logic;
-        psu_alert_i         : in  std_logic;
-        f_rst_i             : in  std_logic;
-        f_rst_o             : out std_logic;
-        f_rst_t_o           : out std_logic;
-        ps_emio_o           : out std_logic_vector(15 downto 0);
-        ps_emio_i           : in  std_logic_vector(15 downto 0);
-        ps_emio_t_i         : in  std_logic_vector(15 downto 0);
-        --! I2C busses
-        wrflash_i2c_irq_i  : in std_logic;
-        bckpl_i2c_irq_i    : in std_logic;
-        ps_irq_o           : out std_logic_vector(1 downto 0);
-        --! Constants module
-        --! Addr of the PHY device(slave). A constant number
-        phyaddr                 : out std_logic_vector(4 downto 0);
-        configuration_vector    : out std_logic_vector(4 downto 0);
-        configuration_valid     : out std_logic_vector(0 downto 0);
-        --!'1' (if not connected to an optical module), otherwise, default is '0'
-        signal_detect           : out std_logic_vector(0 downto 0);
-        --! Slices module
-        link_status_led         : out std_logic;
-        link_sync_led           : out std_logic;
-        clk_src_sel_o           : out std_logic_vector(1 downto 0)
-    );
-end constants;
-
--==============================================================================
--! Architecture declaration
--==============================================================================
-architecture Behavioral of constants is
-
-    --! Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
-    signal s_cnt       : unsigned(11 downto 0);
-    signal s_mdc_led_o : std_logic;
-    type t_pwr_state is (IDLE, RST);
-    signal pwr_state : t_pwr_state;
-    signal ps_emio2_d0 : std_logic;
-    signal ps_emio2_p  : std_logic;
-
--==============================================================================
--! Architecture begin
--==============================================================================
-begin
-
-    an_config_o <= '0';
-    an_config_vec_o <= x"D801";
-    tx_disable_o <= '0';
-
-    phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
-    configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
-    configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
-    signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
-
-    reset_o <= '1' when (pl_resetn_i = '0') else '0';
-
-    link_status_led <= status_vector(0);
-    link_sync_led   <= status_vector(1);
-    clk_src_sel_o   <= "11";
-
-    p_calc_mdc: process(mdc_i, pl_resetn_i)
-    begin
-        if (pl_resetn_i = '0') then
-            s_cnt <= (others=>'0');
-            s_mdc_led_o <= '0';
-        elsif (rising_edge(mdc_i)) then
-            if (s_cnt = 4096-2) then
-                s_cnt     <= (others=>'0');
-                s_mdc_led_o <= '1';
-            else
-                s_mdc_led_o <= '0';
-                s_cnt <= s_cnt + 1;
-            end if;
-        end if;
-    end process p_calc_mdc;
-
-    mdc_clk_led <= s_mdc_led_o;
-
-    --! EMIO -> PL GPIO
-    ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
-    ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else '0';
-
-    p_pwr: process(pl_clk_i)
-    begin
-        if rising_edge(pl_clk_i) then
-            ps_emio2_d0 <= ps_emio_i(2);
-            if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
-                pwr_state <= IDLE;
-                pwr_cycle_req_o <= '0';
-            else
-                if pwr_state = IDLE then
-                    pwr_cycle_req_o <= '0';
-                    if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
-                        pwr_state <= RST;
-                    end if;
-                elsif pwr_state = RST then
-                    pwr_cycle_req_o <= '1';
-                end if;
-            end if;
-        end if;
-    end process p_pwr;
-
-    --! EMIO 83..90
-    ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
-    bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
-    bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
-
-    --! EMIO 91
-    ps_emio_o(13) <= ps_emio_i(13);
-    bckpl_rst_n_o <= ps_emio_i(13);
-
-    --! EMIO 92
-    ps_emio_o(14) <= psu_alert_i;
-
-    --! EMIO 93
-    ps_emio_o(15) <= f_rst_i;
-    f_rst_o <= ps_emio_i(15);
-    f_rst_t_o <= ps_emio_t_i(15);
-
-    --! I2C irqs
-    ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i;
-
-end Behavioral;
--==============================================================================
-- architecture end
--==============================================================================
--- a/gw/projects/diot_v2/src/ps2pl_glue.vhd
+++ b/gw/projects/diot_v2/src/ps2pl_glue.vhd
+-------------------------------------------------------------------------------
+--! @file       ps2pl_glue.vhd
+--! @author     Adrian Byszuk <adrian.byszuk@cern.ch>
+--! @company    CERN
+--! @date       2021-06-28
+--! @brief      PS to PL glue logic and hardcoded config
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--! @brief PS to PL glue logic and hardcoded config signals
+entity ps2pl_glue is
+  generic (
+    g_phyaddr       : natural := 9; --! Ethernet PHY MDIO address
+    g_config_vector : natural := 0; --! Ethernet IP configuration vector
+    g_config_valid  : std_logic_vector := "0"; --! Configuration vector is valid
+    g_signal_detect : std_logic_vector := "1" --! SFP signal detected status
+  );
+  Port (
+    --! @name Fundamental clock and reset
+    pl_clk_i    : in std_logic; --! PL clock
+    pl_resetn_i : in std_logic; --! Reset of the module, coming from PS
+    reset_o     : out std_logic; --! Reset to the PL
+
+    --! @name Ethernet config and status
+    --! MAC status. Check Xilinx docs for detailed info
+    status_vector_i : in std_logic_vector(15 downto 0);
+    mdc_i           : in std_logic; --! Management clock, (<= 2.5MHz)
+    mdc_clk_led_o   : out std_logic; --! MDC activity LED
+    an_config_o     : out std_logic;
+    --! Config data for autonegotiation
+    an_config_vec_o : out std_logic_vector(15 downto 0);
+    tx_disable_o    : out std_logic;
+    --! @}
+
+    --! @name EMIO GPIOs
+    p_pres_i          : in  std_logic_vector(1 downto 0);
+    pwr_cycle_req_o   : out std_logic;
+    bckpl_servmod_i   : in  std_logic_vector(7 downto 0);
+    bckpl_servmod_o   : out std_logic_vector(7 downto 0);
+    bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
+    bckpl_rst_n_o     : out std_logic;
+    psu_alert_i       : in  std_logic;
+    f_rst_i           : in  std_logic;
+    f_rst_o           : out std_logic;
+    f_rst_t_o         : out std_logic;
+    ps_emio_o         : out std_logic_vector(15 downto 0);
+    ps_emio_i         : in  std_logic_vector(94 downto 0);
+    ps_emio_t_i       : in  std_logic_vector(15 downto 0);
+    ps_irq_o          : out std_logic_vector(1 downto 0);
+
+    --! @name I2C bus IRQs
+    wrflash_i2c_irq_i : in std_logic;
+    bckpl_i2c_irq_i   : in std_logic;
+
+    --! @name Constants module
+    --! Addr of the PHY device(slave). A constant number
+    phyaddr_o              : out std_logic_vector(4 downto 0);
+    --! PHY IP configuration vector (consult with Xilinx documentation)
+    configuration_vector_o : out std_logic_vector(4 downto 0);
+    --! Configuration vector is valid
+    configuration_valid_o  : out std_logic_vector(0 downto 0);
+    --! Optical signal detected ('1' if not connected to an optical module)
+    signal_detect_o : out std_logic_vector(0 downto 0);
+
+    --! @name Slices module
+    link_status_led_o : out std_logic;
+    link_sync_led_o   : out std_logic;
+    clk_src_sel_o     : out std_logic_vector(1 downto 0)
+  );
+end ps2pl_glue;
+
+architecture Behavioral of ps2pl_glue is
+
+  --! @name Port attributes for Xilinx IP Integrator
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+
+  ATTRIBUTE X_INTERFACE_INFO OF pl_clk_i: signal IS "xilinx.com:signal:clock:1.0 pl_clk_i CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER of pl_clk_i: SIGNAL is "ASSOCIATED_RESET pl_resetn_i";
+
+  ATTRIBUTE X_INTERFACE_INFO OF pl_resetn_i: SIGNAL IS "xilinx.com:signal:reset:1.0 pl_resetn_i RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER of pl_resetn_i: SIGNAL is "POLARITY ACTIVE_LOW";
+
+  ATTRIBUTE X_INTERFACE_INFO OF reset_o: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER of reset_o: SIGNAL is "POLARITY ACTIVE_HIGH";
+
+  ATTRIBUTE X_INTERFACE_INFO OF mdc_i: signal IS "xilinx.com:signal:clock:1.0 mdc_i CLK";
+
+  ATTRIBUTE X_INTERFACE_INFO of ps_irq_o: SIGNAL is "xilinx.com:signal:interrupt:1.0 ps_irq_o INTERRUPT";
+  ATTRIBUTE X_INTERFACE_INFO of wrflash_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 wrflash_i2c_irq_i INTERRUPT";
+  ATTRIBUTE X_INTERFACE_INFO of bckpl_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 bckpl_i2c_irq_i INTERRUPT";
+  --! @}
+
+  -- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
+  signal s_cnt     : unsigned(11 downto 0);
+  signal s_mdc_led : std_logic;
+
+  type t_pwr_state is (IDLE, RST);
+  signal pwr_state : t_pwr_state;
+  signal ps_emio2_d0 : std_logic;
+  signal ps_emio2_p  : std_logic;
+
+begin
+
+  an_config_o     <= '0';
+  an_config_vec_o <= x"D801";
+  tx_disable_o    <= '0';
+
+  phyaddr_o              <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr_o'length));
+  configuration_vector_o <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector_o'length));
+  configuration_valid_o  <= g_config_valid;
+  signal_detect_o        <= g_signal_detect;
+
+  reset_o <= '1' when (pl_resetn_i = '0') else
+             '0';
+
+  link_status_led_o <= status_vector_i(0);
+  link_sync_led_o   <= status_vector_i(1);
+  clk_src_sel_o     <= "11";
+
+  calc_mdc: process(mdc_i, pl_resetn_i)
+  begin
+
+    if (pl_resetn_i = '0') then
+      s_cnt <= (others => '0');
+      s_mdc_led <= '0';
+
+    elsif (rising_edge(mdc_i)) then
+
+      if (s_cnt = 4096-2) then
+        s_cnt 	<= (others=>'0');
+        s_mdc_led <= '1';
+      else
+        s_mdc_led <= '0';
+        s_cnt <= s_cnt + 1;
+      end if;
+    end if;
+
+  end process;
+
+  mdc_clk_led_o <= s_mdc_led;
+
+  -- EMIO -> PL GPIO
+  ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
+
+  ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else
+                '0';
+  process(pl_clk_i)
+  begin
+    if rising_edge(pl_clk_i) then
+      ps_emio2_d0 <= ps_emio_i(2);
+      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
+        pwr_state <= IDLE;
+        pwr_cycle_req_o <= '0';
+      else
+
+        if pwr_state = IDLE then
+          pwr_cycle_req_o <= '0';
+          if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
+            pwr_state <= RST;
+          end if;
+
+        elsif pwr_state = RST then
+          pwr_cycle_req_o <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- EMIO 83..90
+  ps_emio_o(12 downto 5)        <= bckpl_servmod_i(7 downto 0);
+  bckpl_servmod_o(7 downto 0)   <= ps_emio_i(12 downto 5);
+  bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
+
+  -- EMIO 91
+  ps_emio_o(13) <= ps_emio_i(13);
+  bckpl_rst_n_o <= ps_emio_i(13);
+  -- EMIO 92
+  ps_emio_o(14) <= psu_alert_i;
+  -- EMIO 93
+  ps_emio_o(15) <= f_rst_i;
+  f_rst_o       <= ps_emio_i(15);
+  f_rst_t_o     <= ps_emio_t_i(15);
+
+  -- I2C irqs
+  ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i;
+
+end Behavioral;
--- a/gw/projects/diot_v2/tcl/create_bd.tcl
+++ b/gw/projects/diot_v2/tcl/create_bd.tcl
@@ -78,11 +78,8 @@ proc create_block_design { parentCell design_name target_path } {
        CONFIG.IIC_FREQ_KHZ {100} \
    ] $axi_iic_1

-    # Create instance: constants_and_slices, and set properties
-    set constants_and_slices [ create_bd_cell -type module -reference constants constants_and_slices ]
-    set_property -dict [ list \
-        CONFIG.POLARITY {ACTIVE_HIGH} \
-    ] [ get_bd_pins /constants_and_slices/reset_o ]
+    # Create instance: ps2pl_glue, and set properties
+    set ps2pl_glue [ create_bd_cell -type module -reference ps2pl_glue ps2pl_glue ]

    # Create instance: gig_ethernet_pcs_pma_0, and set properties
    set gig_ethernet_pcs_pma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:gig_ethernet_pcs_pma gig_ethernet_pcs_pma_0 ]
@@ -132,7 +129,7 @@ proc create_block_design { parentCell design_name target_path } {
    connect_bd_intf_net [get_bd_intf_pins zynqmp_ps/IIC_1] [get_bd_intf_ports i2c_emio]

    # PL RST CLK 0
-    connect_bd_net -net pl_resetn0 [get_bd_ports pl_reset_led] [get_bd_pins constants_and_slices/pl_resetn_i] [get_bd_pins RST_PS_CLK0/ext_reset_in] \
+    connect_bd_net -net pl_resetn0 [get_bd_ports pl_reset_led] [get_bd_pins ps2pl_glue/pl_resetn_i] [get_bd_pins RST_PS_CLK0/ext_reset_in] \
    [get_bd_pins zynqmp_ps/pl_resetn0]
    connect_bd_net [get_bd_pins RST_PS_CLK0/interconnect_aresetn] [get_bd_pins lpd_axi_interconnect/ARESETN]
    connect_bd_net -net RST_PS_CLK0_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_iic_1/s_axi_aresetn] \
@@ -140,42 +137,42 @@ proc create_block_design { parentCell design_name target_path } {
    [get_bd_pins lpd_axi_interconnect/S00_ARESETN] [get_bd_pins RST_PS_CLK0/peripheral_aresetn] [get_bd_pins fpga_dev/S_AXI_ARESETN]

    # PL CLK 0 DOMAIN
-    connect_bd_net -net pl_clk0 [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_iic_1/s_axi_aclk] [get_bd_pins constants_and_slices/pl_clk_i] \
+    connect_bd_net -net pl_clk0 [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_iic_1/s_axi_aclk] [get_bd_pins ps2pl_glue/pl_clk_i] \
    [get_bd_pins gig_ethernet_pcs_pma_0/independent_clock_bufg] [get_bd_pins lpd_axi_interconnect/ACLK] [get_bd_pins lpd_axi_interconnect/M00_ACLK] \
    [get_bd_pins lpd_axi_interconnect/M01_ACLK] [get_bd_pins lpd_axi_interconnect/M02_ACLK] [get_bd_pins lpd_axi_interconnect/S00_ACLK] \
    [get_bd_pins RST_PS_CLK0/slowest_sync_clk] [get_bd_pins zynqmp_ps/maxihpm0_lpd_aclk] [get_bd_pins zynqmp_ps/pl_clk0] [get_bd_pins fpga_dev/S_AXI_ACLK]

-    # Constants and Slices connections
-    connect_bd_net [get_bd_pins constants_and_slices/wrflash_i2c_irq_i] [get_bd_pins axi_iic_0/iic2intc_irpt]
-    connect_bd_net [get_bd_pins constants_and_slices/bckpl_i2c_irq_i] [get_bd_pins axi_iic_1/iic2intc_irpt]
-    connect_bd_net [get_bd_pins constants_and_slices/configuration_valid] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_valid]
-    connect_bd_net [get_bd_pins constants_and_slices/configuration_vector] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_vector]
-    connect_bd_net [get_bd_pins constants_and_slices/link_status_led] [get_bd_ports link_status_led]
-    connect_bd_net [get_bd_pins constants_and_slices/link_sync_led] [get_bd_ports link_sync_led]
-    connect_bd_net [get_bd_pins constants_and_slices/mdc_clk_led] [get_bd_ports mdc_clk_led]
-    connect_bd_net [get_bd_pins constants_and_slices/phyaddr] [get_bd_pins gig_ethernet_pcs_pma_0/phyaddr]
-    connect_bd_net [get_bd_pins constants_and_slices/signal_detect] [get_bd_pins gig_ethernet_pcs_pma_0/signal_detect]
-    connect_bd_net [get_bd_pins constants_and_slices/an_config_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_val] [get_bd_pins gig_ethernet_pcs_pma_0/an_restart_config]
-    connect_bd_net [get_bd_pins constants_and_slices/an_config_vec_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_vector]
-    connect_bd_net [get_bd_pins constants_and_slices/bckpl_rst_n_o] [get_bd_ports bckpl_rst_n_o]
-    connect_bd_net [get_bd_pins constants_and_slices/clk_src_sel_o] [get_bd_ports clk_src_sel_o]
-    connect_bd_net [get_bd_pins constants_and_slices/ps_emio_o] [get_bd_pins zynqmp_ps/emio_gpio_i]
-    connect_bd_net [get_bd_pins constants_and_slices/ps_irq_o] [get_bd_pins zynqmp_ps/pl_ps_irq0]
-    connect_bd_net [get_bd_pins constants_and_slices/pwr_cycle_req_o] [get_bd_ports pwr_cycle_req_o_0]
-    connect_bd_net [get_bd_pins constants_and_slices/reset_o] [get_bd_pins gig_ethernet_pcs_pma_0/reset]
-    connect_bd_net [get_bd_pins constants_and_slices/tx_disable_o] [get_bd_ports tx_disable_o]
-    connect_bd_net [get_bd_pins constants_and_slices/status_vector] [get_bd_pins gig_ethernet_pcs_pma_0/status_vector]
-    connect_bd_net [get_bd_pins constants_and_slices/p_pres_i] [get_bd_ports p_pres_i_0]
-    connect_bd_net [get_bd_pins constants_and_slices/psu_alert_i] [get_bd_ports psu_alert_i]
-    connect_bd_net [get_bd_pins constants_and_slices/mdc_i] [get_bd_pins gig_ethernet_pcs_pma_0/mdc] [get_bd_pins zynqmp_ps/emio_enet0_mdio_mdc]
-    connect_bd_net [get_bd_pins constants_and_slices/ps_emio_i] [get_bd_pins zynqmp_ps/emio_gpio_o]
-    connect_bd_net [get_bd_pins constants_and_slices/ps_emio_t_i] [get_bd_pins zynqmp_ps/emio_gpio_t]
-    connect_bd_net [get_bd_pins constants_and_slices/f_rst_i] [get_bd_ports f_rst_i]
-    connect_bd_net [get_bd_pins constants_and_slices/f_rst_o] [get_bd_ports f_rst_o]
-    connect_bd_net [get_bd_pins constants_and_slices/f_rst_t_o] [get_bd_ports f_rst_t]
-    connect_bd_net [get_bd_pins constants_and_slices/bckpl_servmod_i] [get_bd_ports bckpl_servmod_i]
-    connect_bd_net [get_bd_pins constants_and_slices/bckpl_servmod_o] [get_bd_ports bckpl_servmod_o]
-    connect_bd_net [get_bd_pins constants_and_slices/bckpl_servmod_t_o] [get_bd_ports bckpl_servmod_t]
+    # PS to PL glue logic connections
+    connect_bd_net [get_bd_pins ps2pl_glue/wrflash_i2c_irq_i] [get_bd_pins axi_iic_0/iic2intc_irpt]
+    connect_bd_net [get_bd_pins ps2pl_glue/bckpl_i2c_irq_i] [get_bd_pins axi_iic_1/iic2intc_irpt]
+    connect_bd_net [get_bd_pins ps2pl_glue/configuration_valid_o] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_valid]
+    connect_bd_net [get_bd_pins ps2pl_glue/configuration_vector_o] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_vector]
+    connect_bd_net [get_bd_pins ps2pl_glue/link_status_led_o] [get_bd_ports link_status_led]
+    connect_bd_net [get_bd_pins ps2pl_glue/link_sync_led_o] [get_bd_ports link_sync_led]
+    connect_bd_net [get_bd_pins ps2pl_glue/mdc_clk_led_o] [get_bd_ports mdc_clk_led]
+    connect_bd_net [get_bd_pins ps2pl_glue/phyaddr_o] [get_bd_pins gig_ethernet_pcs_pma_0/phyaddr]
+    connect_bd_net [get_bd_pins ps2pl_glue/signal_detect_o] [get_bd_pins gig_ethernet_pcs_pma_0/signal_detect]
+    connect_bd_net [get_bd_pins ps2pl_glue/an_config_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_val] [get_bd_pins gig_ethernet_pcs_pma_0/an_restart_config]
+    connect_bd_net [get_bd_pins ps2pl_glue/an_config_vec_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_vector]
+    connect_bd_net [get_bd_pins ps2pl_glue/bckpl_rst_n_o] [get_bd_ports bckpl_rst_n_o]
+    connect_bd_net [get_bd_pins ps2pl_glue/clk_src_sel_o] [get_bd_ports clk_src_sel_o]
+    connect_bd_net [get_bd_pins ps2pl_glue/ps_emio_o] [get_bd_pins zynqmp_ps/emio_gpio_i]
+    connect_bd_net [get_bd_pins ps2pl_glue/ps_irq_o] [get_bd_pins zynqmp_ps/pl_ps_irq0]
+    connect_bd_net [get_bd_pins ps2pl_glue/pwr_cycle_req_o] [get_bd_ports pwr_cycle_req_o_0]
+    connect_bd_net [get_bd_pins ps2pl_glue/reset_o] [get_bd_pins gig_ethernet_pcs_pma_0/reset]
+    connect_bd_net [get_bd_pins ps2pl_glue/tx_disable_o] [get_bd_ports tx_disable_o]
+    connect_bd_net [get_bd_pins ps2pl_glue/status_vector_i] [get_bd_pins gig_ethernet_pcs_pma_0/status_vector]
+    connect_bd_net [get_bd_pins ps2pl_glue/p_pres_i] [get_bd_ports p_pres_i_0]
+    connect_bd_net [get_bd_pins ps2pl_glue/psu_alert_i] [get_bd_ports psu_alert_i]
+    connect_bd_net [get_bd_pins ps2pl_glue/mdc_i] [get_bd_pins gig_ethernet_pcs_pma_0/mdc] [get_bd_pins zynqmp_ps/emio_enet0_mdio_mdc]
+    connect_bd_net [get_bd_pins ps2pl_glue/ps_emio_i] [get_bd_pins zynqmp_ps/emio_gpio_o]
+    connect_bd_net [get_bd_pins ps2pl_glue/ps_emio_t_i] [get_bd_pins zynqmp_ps/emio_gpio_t]
+    connect_bd_net [get_bd_pins ps2pl_glue/f_rst_i] [get_bd_ports f_rst_i]
+    connect_bd_net [get_bd_pins ps2pl_glue/f_rst_o] [get_bd_ports f_rst_o]
+    connect_bd_net [get_bd_pins ps2pl_glue/f_rst_t_o] [get_bd_ports f_rst_t]
+    connect_bd_net [get_bd_pins ps2pl_glue/bckpl_servmod_i] [get_bd_ports bckpl_servmod_i]
+    connect_bd_net [get_bd_pins ps2pl_glue/bckpl_servmod_o] [get_bd_ports bckpl_servmod_o]
+    connect_bd_net [get_bd_pins ps2pl_glue/bckpl_servmod_t_o] [get_bd_ports bckpl_servmod_t]

    # Create address segments
    assign_bd_address -offset 0x80000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynqmp_ps/Data] [get_bd_addr_segs fpga_dev/S_AXI/reg0] -force

--- a/gw/projects/diot_v2/tcl/project_cfg.tcl
+++ b/gw/projects/diot_v2/tcl/project_cfg.tcl
@@ -19,7 +19,7 @@ set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
 add_vhdl_src ${lib_default} ../src/${entity_top}.vhd

 # Vhdl Src
-add_vhdl_src ${lib_default} ../src/constants.vhd
+add_vhdl_src ${lib_default} ../src/ps2pl_glue.vhd

 # Add Constraints
 add_constraint diot_v2.xdc