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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit a23c7dbd authored by Adrian Byszuk's avatar Adrian Byszuk
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GW: add RTL support for Chip2Chip/Aurora subsystem

parent 96953ab8
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gw/projects/diot_v2/src/c2c_link.vhd 0 → 100644
View file @ a23c7dbd
-------------------------------------------------------------------------------
--! @file c2c_link.vhd
--! @author Adrian Byszuk
--! @copyright CERN SY-EPC-CCE
--! @date 05-07-2022
--! @brief Chip2Chip link control and status
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief Chip2Chip link control and status
--! @details
--! Provides software with basic control and diagnostic capabilities.
--! Intended to be easily integrated with Xilinx Block Design.
--! Supports up to 8 links, which is maximum in a standard DIOT crate.
entity c2c_link is
generic (
addr_width_g : positive := 6
);
port (
--! @name AXI4Lite slave bus (naming convention compatible with Xilinx IP Integrator)
s_axi_aclk : in std_ulogic;
s_axi_aresetn : in std_ulogic;
--
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_awaddr : in std_logic_vector(addr_width_g-1 downto 0);
--
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
--
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
--
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_araddr : in std_logic_vector(addr_width_g-1 downto 0);
--
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
--! @name Aurora/Chip2Chip signals (for meaning of some signals see the IP documentation)
--! Output reset vector is split to avoid stupid block design slicing
reset_0 : out std_logic; --! PMA reset to link 0
reset_1 : out std_logic; --! PMA reset to link 1
reset_2 : out std_logic; --! PMA reset to link 2
reset_3 : out std_logic; --! PMA reset to link 3
reset_4 : out std_logic; --! PMA reset to link 4
reset_5 : out std_logic; --! PMA reset to link 5
reset_6 : out std_logic; --! PMA reset to link 6
reset_7 : out std_logic; --! PMA reset to link 7
channel_up : in std_logic_vector(7 downto 0); --! Aurora channel_up status
hard_err : in std_logic_vector(7 downto 0); --! Aurora hard_err status
gt_pll_lock : in std_logic_vector(7 downto 0); --! MGT PLL lock status
link_status : in std_logic_vector(7 downto 0); --! Chip2Chip link up status
config_error : in std_logic_vector(7 downto 0); --! Chip2Chip endpoint config error
link_error : in std_logic_vector(7 downto 0); --! Chip2Chip link error
multi_bit_error : in std_logic_vector(7 downto 0) --! Chip2Chip multi_bit error status
);
end entity c2c_link;
--! RTL implementation of c2c_link
architecture rtl of c2c_link is
--! @name Attributes required to silence Vivado BD GUI
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF reset_0: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_0: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_1: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_1: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_2: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_2: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_3: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_3: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_4: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_4: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_5: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_5: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_6: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_6: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_7: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_7: SIGNAL is "POLARITY ACTIVE_HIGH";
--! @}
begin
--! Wishbone registers (autogenerated)
x_regs : entity work.link_ctrl_regs
port map (
aclk => s_axi_aclk,
areset_n => s_axi_aresetn,
awvalid => s_axi_awvalid,
awready => s_axi_awready,
awaddr => s_axi_awaddr,
awprot => "000",
wvalid => s_axi_wvalid,
wready => s_axi_wready,
wdata => s_axi_wdata,
wstrb => s_axi_wstrb,
bvalid => s_axi_bvalid,
bready => s_axi_bready,
bresp => s_axi_bresp,
arvalid => s_axi_arvalid,
arready => s_axi_arready,
araddr => s_axi_araddr,
arprot => "000",
rvalid => s_axi_rvalid,
rready => s_axi_rready,
rdata => s_axi_rdata,
rresp => s_axi_rresp,
link_0_ctrl_reset_o => reset_0,
link_0_status_channel_up_i => channel_up(0),
link_0_status_hard_err_i => hard_err(0),
link_0_status_gt_pll_lock_i => gt_pll_lock(0),
link_0_status_link_status_i => link_status(0),
link_0_status_config_error_i => config_error(0),
link_0_status_link_error_i => link_error(0),
link_0_status_multi_bit_error_i => multi_bit_error(0),
link_1_ctrl_reset_o => reset_1,
link_1_status_channel_up_i => channel_up(1),
link_1_status_hard_err_i => hard_err(1),
link_1_status_gt_pll_lock_i => gt_pll_lock(1),
link_1_status_link_status_i => link_status(1),
link_1_status_config_error_i => config_error(1),
link_1_status_link_error_i => link_error(1),
link_1_status_multi_bit_error_i => multi_bit_error(1),
link_2_ctrl_reset_o => reset_2,
link_2_status_channel_up_i => channel_up(2),
link_2_status_hard_err_i => hard_err(2),
link_2_status_gt_pll_lock_i => gt_pll_lock(2),
link_2_status_link_status_i => link_status(2),
link_2_status_config_error_i => config_error(2),
link_2_status_link_error_i => link_error(2),
link_2_status_multi_bit_error_i => multi_bit_error(2),
link_3_ctrl_reset_o => reset_3,
link_3_status_channel_up_i => channel_up(3),
link_3_status_hard_err_i => hard_err(3),
link_3_status_gt_pll_lock_i => gt_pll_lock(3),
link_3_status_link_status_i => link_status(3),
link_3_status_config_error_i => config_error(3),
link_3_status_link_error_i => link_error(3),
link_3_status_multi_bit_error_i => multi_bit_error(3),
link_4_ctrl_reset_o => reset_4,
link_4_status_channel_up_i => channel_up(4),
link_4_status_hard_err_i => hard_err(4),
link_4_status_gt_pll_lock_i => gt_pll_lock(4),
link_4_status_link_status_i => link_status(4),
link_4_status_config_error_i => config_error(4),
link_4_status_link_error_i => link_error(4),
link_4_status_multi_bit_error_i => multi_bit_error(4),
link_5_ctrl_reset_o => reset_5,
link_5_status_channel_up_i => channel_up(5),
link_5_status_hard_err_i => hard_err(5),
link_5_status_gt_pll_lock_i => gt_pll_lock(5),
link_5_status_link_status_i => link_status(5),
link_5_status_config_error_i => config_error(5),
link_5_status_link_error_i => link_error(5),
link_5_status_multi_bit_error_i => multi_bit_error(5),
link_6_ctrl_reset_o => reset_6,
link_6_status_channel_up_i => channel_up(6),
link_6_status_hard_err_i => hard_err(6),
link_6_status_gt_pll_lock_i => gt_pll_lock(6),
link_6_status_link_status_i => link_status(6),
link_6_status_config_error_i => config_error(6),
link_6_status_link_error_i => link_error(6),
link_6_status_multi_bit_error_i => multi_bit_error(6),
link_7_ctrl_reset_o => reset_7,
link_7_status_channel_up_i => channel_up(7),
link_7_status_hard_err_i => hard_err(7),
link_7_status_gt_pll_lock_i => gt_pll_lock(7),
link_7_status_link_status_i => link_status(7),
link_7_status_config_error_i => config_error(7),
link_7_status_link_error_i => link_error(7),
link_7_status_multi_bit_error_i => multi_bit_error(7)
);
end architecture rtl;
gw/projects/diot_v2/src/c2c_link_regs.cheby 0 → 100644
View file @ a23c7dbd
memory-map:
bus: axi4-lite-32
name: link_ctrl_regs
description: Aurora link control/status
x-hdl:
bus-granularity: byte
children:
- repeat:
name: link
description: Data to be sent to DAC
count: 8
children:
- reg:
name: ctrl
description: Control register
width: 32
access: rw
type: unsigned
children:
- field:
name: reset
description: Reset the Aurora link
range: 0
preset: 0
x-hdl:
type: autoclear
- reg:
name: status
description: Status register
type: unsigned
width: 32
access: ro
children:
- field:
name: channel_up
description: Aurora channel is up and running
range: 0
- field:
name: hard_err
description: Aurora hard error - reset required
range: 1
- field:
name: gt_pll_lock
description: MGT PLL is locked
range: 2
- field:
name: link_status
description: Chip2Chip link is up and running
range: 3
- field:
name: config_error
description: Chip2Chip config error (see Xilinx PG067)
range: 4
- field:
name: link_error
description: Chip2Chip link error (see Xilinx PG067)
range: 5
- field:
name: multi_bit_error
description: Chip2Chip multi-bit error (see Xilinx PG067)
range: 6
gw/projects/diot_v2/src/c2c_link_regs.vhd 0 → 100644
View file @ a23c7dbd
-- Do not edit. Generated by cheby 1.5.dev0 using these options:
-- --print-simple --gen-hdl=c2c_link_regs.vhd --gen-doc=c2c_link_regs.html -i c2c_link_regs.cheby
-- Generated on Mon Jul 11 18:17:36 2022 by adrian
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity link_ctrl_regs is
port (
aclk : in std_logic;
areset_n : in std_logic;
awvalid : in std_logic;
awready : out std_logic;
awaddr : in std_logic_vector(5 downto 0);
awprot : in std_logic_vector(2 downto 0);
wvalid : in std_logic;
wready : out std_logic;
wdata : in std_logic_vector(31 downto 0);
wstrb : in std_logic_vector(3 downto 0);
bvalid : out std_logic;
bready : in std_logic;
bresp : out std_logic_vector(1 downto 0);
arvalid : in std_logic;
arready : out std_logic;
araddr : in std_logic_vector(5 downto 0);
arprot : in std_logic_vector(2 downto 0);
rvalid : out std_logic;
rready : in std_logic;
rdata : out std_logic_vector(31 downto 0);
rresp : out std_logic_vector(1 downto 0);
-- Control register
-- Reset the Aurora link
link_0_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_0_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_0_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_0_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_0_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_0_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_0_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_0_status_multi_bit_error_i : in std_logic;
-- Control register
-- Reset the Aurora link
link_1_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_1_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_1_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_1_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_1_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_1_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_1_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_1_status_multi_bit_error_i : in std_logic;
-- Control register
-- Reset the Aurora link
link_2_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_2_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_2_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_2_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_2_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_2_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_2_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_2_status_multi_bit_error_i : in std_logic;
-- Control register
-- Reset the Aurora link
link_3_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_3_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_3_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_3_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_3_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_3_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_3_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_3_status_multi_bit_error_i : in std_logic;
-- Control register
-- Reset the Aurora link
link_4_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_4_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_4_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_4_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_4_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_4_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_4_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_4_status_multi_bit_error_i : in std_logic;
-- Control register
-- Reset the Aurora link
link_5_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_5_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_5_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_5_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_5_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_5_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_5_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_5_status_multi_bit_error_i : in std_logic;
-- Control register
-- Reset the Aurora link
link_6_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_6_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_6_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_6_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_6_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_6_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_6_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_6_status_multi_bit_error_i : in std_logic;
-- Control register
-- Reset the Aurora link
link_7_ctrl_reset_o : out std_logic;
-- Status register
-- Aurora channel is up and running
link_7_status_channel_up_i : in std_logic;
-- Aurora hard error - reset required
link_7_status_hard_err_i : in std_logic;
-- MGT PLL is locked
link_7_status_gt_pll_lock_i : in std_logic;
-- Chip2Chip link is up and running
link_7_status_link_status_i : in std_logic;
-- Chip2Chip config error (see Xilinx PG067)
link_7_status_config_error_i : in std_logic;
-- Chip2Chip link error (see Xilinx PG067)
link_7_status_link_error_i : in std_logic;
-- Chip2Chip multi-bit error (see Xilinx PG067)
link_7_status_multi_bit_error_i : in std_logic
);
end link_ctrl_regs;
architecture syn of link_ctrl_regs is
signal wr_req : std_logic;
signal wr_ack : std_logic;
signal wr_addr : std_logic_vector(5 downto 2);
signal wr_data : std_logic_vector(31 downto 0);
signal axi_awset : std_logic;
signal axi_wset : std_logic;
signal axi_wdone : std_logic;
signal rd_req : std_logic;
signal rd_ack : std_logic;
signal rd_addr : std_logic_vector(5 downto 2);
signal rd_data : std_logic_vector(31 downto 0);
signal axi_arset : std_logic;
signal axi_rdone : std_logic;
signal link_0_ctrl_reset_reg : std_logic;
signal link_0_ctrl_wreq : std_logic;
signal link_0_ctrl_wack : std_logic;
signal link_1_ctrl_reset_reg : std_logic;
signal link_1_ctrl_wreq : std_logic;
signal link_1_ctrl_wack : std_logic;
signal link_2_ctrl_reset_reg : std_logic;
signal link_2_ctrl_wreq : std_logic;
signal link_2_ctrl_wack : std_logic;
signal link_3_ctrl_reset_reg : std_logic;
signal link_3_ctrl_wreq : std_logic;
signal link_3_ctrl_wack : std_logic;
signal link_4_ctrl_reset_reg : std_logic;
signal link_4_ctrl_wreq : std_logic;
signal link_4_ctrl_wack : std_logic;
signal link_5_ctrl_reset_reg : std_logic;
signal link_5_ctrl_wreq : std_logic;
signal link_5_ctrl_wack : std_logic;
signal link_6_ctrl_reset_reg : std_logic;
signal link_6_ctrl_wreq : std_logic;
signal link_6_ctrl_wack : std_logic;
signal link_7_ctrl_reset_reg : std_logic;
signal link_7_ctrl_wreq : std_logic;
signal link_7_ctrl_wack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(5 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
begin
-- AW, W and B channels
awready <= not axi_awset;
wready <= not axi_wset;
bvalid <= axi_wdone;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
wr_req <= '0';
axi_awset <= '0';
axi_wset <= '0';
axi_wdone <= '0';
else
wr_req <= '0';
if awvalid = '1' and axi_awset = '0' then
wr_addr <= awaddr(5 downto 2);
axi_awset <= '1';
wr_req <= axi_wset;
end if;
if wvalid = '1' and axi_wset = '0' then
wr_data <= wdata;
axi_wset <= '1';
wr_req <= axi_awset or awvalid;
end if;
if (axi_wdone and bready) = '1' then
axi_wset <= '0';
axi_awset <= '0';
axi_wdone <= '0';
end if;
if wr_ack = '1' then
axi_wdone <= '1';
end if;
end if;
end if;
end process;
bresp <= "00";
-- AR and R channels
arready <= not axi_arset;
rvalid <= axi_rdone;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
rd_req <= '0';
axi_arset <= '0';
axi_rdone <= '0';
rdata <= (others => '0');
else
rd_req <= '0';
if arvalid = '1' and axi_arset = '0' then
rd_addr <= araddr(5 downto 2);
axi_arset <= '1';
rd_req <= '1';
end if;
if (axi_rdone and rready) = '1' then
axi_arset <= '0';
axi_rdone <= '0';
end if;
if rd_ack = '1' then
axi_rdone <= '1';
rdata <= rd_data;
end if;
end if;
end if;
end process;
rresp <= "00";
-- pipelining for wr-in+rd-out
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
rd_ack <= '0';
wr_req_d0 <= '0';
else
rd_ack <= rd_ack_d0;
rd_data <= rd_dat_d0;
wr_req_d0 <= wr_req;
wr_adr_d0 <= wr_addr;
wr_dat_d0 <= wr_data;
end if;
end if;
end process;
-- Register link_0_ctrl
link_0_ctrl_reset_o <= link_0_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_0_ctrl_reset_reg <= '0';
link_0_ctrl_wack <= '0';
else
if link_0_ctrl_wreq = '1' then
link_0_ctrl_reset_reg <= wr_dat_d0(0);
else
link_0_ctrl_reset_reg <= '0';
end if;
link_0_ctrl_wack <= link_0_ctrl_wreq;
end if;
end if;
end process;
-- Register link_0_status
-- Register link_1_ctrl
link_1_ctrl_reset_o <= link_1_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_1_ctrl_reset_reg <= '0';
link_1_ctrl_wack <= '0';
else
if link_1_ctrl_wreq = '1' then
link_1_ctrl_reset_reg <= wr_dat_d0(0);
else
link_1_ctrl_reset_reg <= '0';
end if;
link_1_ctrl_wack <= link_1_ctrl_wreq;
end if;
end if;
end process;
-- Register link_1_status
-- Register link_2_ctrl
link_2_ctrl_reset_o <= link_2_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_2_ctrl_reset_reg <= '0';
link_2_ctrl_wack <= '0';
else
if link_2_ctrl_wreq = '1' then
link_2_ctrl_reset_reg <= wr_dat_d0(0);
else
link_2_ctrl_reset_reg <= '0';
end if;
link_2_ctrl_wack <= link_2_ctrl_wreq;
end if;
end if;
end process;
-- Register link_2_status
-- Register link_3_ctrl
link_3_ctrl_reset_o <= link_3_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_3_ctrl_reset_reg <= '0';
link_3_ctrl_wack <= '0';
else
if link_3_ctrl_wreq = '1' then
link_3_ctrl_reset_reg <= wr_dat_d0(0);
else
link_3_ctrl_reset_reg <= '0';
end if;
link_3_ctrl_wack <= link_3_ctrl_wreq;
end if;
end if;
end process;
-- Register link_3_status
-- Register link_4_ctrl
link_4_ctrl_reset_o <= link_4_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_4_ctrl_reset_reg <= '0';
link_4_ctrl_wack <= '0';
else
if link_4_ctrl_wreq = '1' then
link_4_ctrl_reset_reg <= wr_dat_d0(0);
else
link_4_ctrl_reset_reg <= '0';
end if;
link_4_ctrl_wack <= link_4_ctrl_wreq;
end if;
end if;
end process;
-- Register link_4_status
-- Register link_5_ctrl
link_5_ctrl_reset_o <= link_5_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_5_ctrl_reset_reg <= '0';
link_5_ctrl_wack <= '0';
else
if link_5_ctrl_wreq = '1' then
link_5_ctrl_reset_reg <= wr_dat_d0(0);
else
link_5_ctrl_reset_reg <= '0';
end if;
link_5_ctrl_wack <= link_5_ctrl_wreq;
end if;
end if;
end process;
-- Register link_5_status
-- Register link_6_ctrl
link_6_ctrl_reset_o <= link_6_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_6_ctrl_reset_reg <= '0';
link_6_ctrl_wack <= '0';
else
if link_6_ctrl_wreq = '1' then
link_6_ctrl_reset_reg <= wr_dat_d0(0);
else
link_6_ctrl_reset_reg <= '0';
end if;
link_6_ctrl_wack <= link_6_ctrl_wreq;
end if;
end if;
end process;
-- Register link_6_status
-- Register link_7_ctrl
link_7_ctrl_reset_o <= link_7_ctrl_reset_reg;
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
link_7_ctrl_reset_reg <= '0';
link_7_ctrl_wack <= '0';
else
if link_7_ctrl_wreq = '1' then
link_7_ctrl_reset_reg <= wr_dat_d0(0);
else
link_7_ctrl_reset_reg <= '0';
end if;
link_7_ctrl_wack <= link_7_ctrl_wreq;
end if;
end if;
end process;
-- Register link_7_status
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, link_0_ctrl_wack, link_1_ctrl_wack, link_2_ctrl_wack, link_3_ctrl_wack, link_4_ctrl_wack, link_5_ctrl_wack, link_6_ctrl_wack, link_7_ctrl_wack) begin
link_0_ctrl_wreq <= '0';
link_1_ctrl_wreq <= '0';
link_2_ctrl_wreq <= '0';
link_3_ctrl_wreq <= '0';
link_4_ctrl_wreq <= '0';
link_5_ctrl_wreq <= '0';
link_6_ctrl_wreq <= '0';
link_7_ctrl_wreq <= '0';
case wr_adr_d0(5 downto 2) is
when "0000" =>
-- Reg link_0_ctrl
link_0_ctrl_wreq <= wr_req_d0;
wr_ack <= link_0_ctrl_wack;
when "0001" =>
-- Reg link_0_status
wr_ack <= wr_req_d0;
when "0010" =>
-- Reg link_1_ctrl
link_1_ctrl_wreq <= wr_req_d0;
wr_ack <= link_1_ctrl_wack;
when "0011" =>
-- Reg link_1_status
wr_ack <= wr_req_d0;
when "0100" =>
-- Reg link_2_ctrl
link_2_ctrl_wreq <= wr_req_d0;
wr_ack <= link_2_ctrl_wack;
when "0101" =>
-- Reg link_2_status
wr_ack <= wr_req_d0;
when "0110" =>
-- Reg link_3_ctrl
link_3_ctrl_wreq <= wr_req_d0;
wr_ack <= link_3_ctrl_wack;
when "0111" =>
-- Reg link_3_status
wr_ack <= wr_req_d0;
when "1000" =>
-- Reg link_4_ctrl
link_4_ctrl_wreq <= wr_req_d0;
wr_ack <= link_4_ctrl_wack;
when "1001" =>
-- Reg link_4_status
wr_ack <= wr_req_d0;
when "1010" =>
-- Reg link_5_ctrl
link_5_ctrl_wreq <= wr_req_d0;
wr_ack <= link_5_ctrl_wack;
when "1011" =>
-- Reg link_5_status
wr_ack <= wr_req_d0;
when "1100" =>
-- Reg link_6_ctrl
link_6_ctrl_wreq <= wr_req_d0;
wr_ack <= link_6_ctrl_wack;
when "1101" =>
-- Reg link_6_status
wr_ack <= wr_req_d0;
when "1110" =>
-- Reg link_7_ctrl
link_7_ctrl_wreq <= wr_req_d0;
wr_ack <= link_7_ctrl_wack;
when "1111" =>
-- Reg link_7_status
wr_ack <= wr_req_d0;
when others =>
wr_ack <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (rd_addr, rd_req, link_0_status_channel_up_i, link_0_status_hard_err_i, link_0_status_gt_pll_lock_i, link_0_status_link_status_i, link_0_status_config_error_i, link_0_status_link_error_i, link_0_status_multi_bit_error_i, link_1_status_channel_up_i, link_1_status_hard_err_i, link_1_status_gt_pll_lock_i, link_1_status_link_status_i, link_1_status_config_error_i, link_1_status_link_error_i, link_1_status_multi_bit_error_i, link_2_status_channel_up_i, link_2_status_hard_err_i, link_2_status_gt_pll_lock_i, link_2_status_link_status_i, link_2_status_config_error_i, link_2_status_link_error_i, link_2_status_multi_bit_error_i, link_3_status_channel_up_i, link_3_status_hard_err_i, link_3_status_gt_pll_lock_i, link_3_status_link_status_i, link_3_status_config_error_i, link_3_status_link_error_i, link_3_status_multi_bit_error_i, link_4_status_channel_up_i, link_4_status_hard_err_i, link_4_status_gt_pll_lock_i, link_4_status_link_status_i, link_4_status_config_error_i, link_4_status_link_error_i, link_4_status_multi_bit_error_i, link_5_status_channel_up_i, link_5_status_hard_err_i, link_5_status_gt_pll_lock_i, link_5_status_link_status_i, link_5_status_config_error_i, link_5_status_link_error_i, link_5_status_multi_bit_error_i, link_6_status_channel_up_i, link_6_status_hard_err_i, link_6_status_gt_pll_lock_i, link_6_status_link_status_i, link_6_status_config_error_i, link_6_status_link_error_i, link_6_status_multi_bit_error_i, link_7_status_channel_up_i, link_7_status_hard_err_i, link_7_status_gt_pll_lock_i, link_7_status_link_status_i, link_7_status_config_error_i, link_7_status_link_error_i, link_7_status_multi_bit_error_i) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case rd_addr(5 downto 2) is
when "0000" =>
-- Reg link_0_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "0001" =>
-- Reg link_0_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_0_status_channel_up_i;
rd_dat_d0(1) <= link_0_status_hard_err_i;
rd_dat_d0(2) <= link_0_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_0_status_link_status_i;
rd_dat_d0(4) <= link_0_status_config_error_i;
rd_dat_d0(5) <= link_0_status_link_error_i;
rd_dat_d0(6) <= link_0_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when "0010" =>
-- Reg link_1_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "0011" =>
-- Reg link_1_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_1_status_channel_up_i;
rd_dat_d0(1) <= link_1_status_hard_err_i;
rd_dat_d0(2) <= link_1_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_1_status_link_status_i;
rd_dat_d0(4) <= link_1_status_config_error_i;
rd_dat_d0(5) <= link_1_status_link_error_i;
rd_dat_d0(6) <= link_1_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when "0100" =>
-- Reg link_2_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "0101" =>
-- Reg link_2_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_2_status_channel_up_i;
rd_dat_d0(1) <= link_2_status_hard_err_i;
rd_dat_d0(2) <= link_2_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_2_status_link_status_i;
rd_dat_d0(4) <= link_2_status_config_error_i;
rd_dat_d0(5) <= link_2_status_link_error_i;
rd_dat_d0(6) <= link_2_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when "0110" =>
-- Reg link_3_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "0111" =>
-- Reg link_3_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_3_status_channel_up_i;
rd_dat_d0(1) <= link_3_status_hard_err_i;
rd_dat_d0(2) <= link_3_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_3_status_link_status_i;
rd_dat_d0(4) <= link_3_status_config_error_i;
rd_dat_d0(5) <= link_3_status_link_error_i;
rd_dat_d0(6) <= link_3_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when "1000" =>
-- Reg link_4_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "1001" =>
-- Reg link_4_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_4_status_channel_up_i;
rd_dat_d0(1) <= link_4_status_hard_err_i;
rd_dat_d0(2) <= link_4_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_4_status_link_status_i;
rd_dat_d0(4) <= link_4_status_config_error_i;
rd_dat_d0(5) <= link_4_status_link_error_i;
rd_dat_d0(6) <= link_4_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when "1010" =>
-- Reg link_5_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "1011" =>
-- Reg link_5_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_5_status_channel_up_i;
rd_dat_d0(1) <= link_5_status_hard_err_i;
rd_dat_d0(2) <= link_5_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_5_status_link_status_i;
rd_dat_d0(4) <= link_5_status_config_error_i;
rd_dat_d0(5) <= link_5_status_link_error_i;
rd_dat_d0(6) <= link_5_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when "1100" =>
-- Reg link_6_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "1101" =>
-- Reg link_6_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_6_status_channel_up_i;
rd_dat_d0(1) <= link_6_status_hard_err_i;
rd_dat_d0(2) <= link_6_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_6_status_link_status_i;
rd_dat_d0(4) <= link_6_status_config_error_i;
rd_dat_d0(5) <= link_6_status_link_error_i;
rd_dat_d0(6) <= link_6_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when "1110" =>
-- Reg link_7_ctrl
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= '0';
rd_dat_d0(31 downto 1) <= (others => '0');
when "1111" =>
-- Reg link_7_status
rd_ack_d0 <= rd_req;
rd_dat_d0(0) <= link_7_status_channel_up_i;
rd_dat_d0(1) <= link_7_status_hard_err_i;
rd_dat_d0(2) <= link_7_status_gt_pll_lock_i;
rd_dat_d0(3) <= link_7_status_link_status_i;
rd_dat_d0(4) <= link_7_status_config_error_i;
rd_dat_d0(5) <= link_7_status_link_error_i;
rd_dat_d0(6) <= link_7_status_multi_bit_error_i;
rd_dat_d0(31 downto 7) <= (others => '0');
when others =>
rd_ack_d0 <= rd_req;
end case;
end process;
end syn;
gw/projects/diot_v2/src/ps2pl_glue.vhd
View file @ a23c7dbd
......@@ -50,11 +50,12 @@ entity ps2pl_glue is
ps_emio_o : out std_logic_vector(15 downto 0);
ps_emio_i : in std_logic_vector(94 downto 0);
ps_emio_t_i : in std_logic_vector(15 downto 0);
ps_irq_o : out std_logic_vector(1 downto 0);
--! @name I2C bus IRQs
--! @name I2C bus and other IRQs
wrflash_i2c_irq_i : in std_logic;
bckpl_i2c_irq_i : in std_logic;
aurora_dma_irq_i : in std_logic;
ps_irq_o : out std_logic_vector(2 downto 0);
--! @name Constants module
--! Addr of the PHY device(slave). A constant number
......@@ -93,6 +94,7 @@ architecture Behavioral of ps2pl_glue is
ATTRIBUTE X_INTERFACE_INFO of ps_irq_o: SIGNAL is "xilinx.com:signal:interrupt:1.0 ps_irq_o INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO of wrflash_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 wrflash_i2c_irq_i INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO of bckpl_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 bckpl_i2c_irq_i INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO of aurora_dma_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 aurora_dma_irq_i INTERRUPT";
--! @}
-- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
......@@ -187,6 +189,6 @@ begin
f_rst_t_o <= ps_emio_t_i(15);
-- I2C irqs
ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i;
ps_irq_o <= aurora_dma_irq_i & bckpl_i2c_irq_i & wrflash_i2c_irq_i;
end Behavioral;
gw/projects/diot_v2/src/run_cheby.sh 0 → 100755
View file @ a23c7dbd
#!/bin/sh
NAME="c2c_link_regs"
# commands must be executed from script directory, where both script and .cheby files are
cd "$(dirname "$(readlink -f "$0")")"
cheby --print-simple --gen-hdl=$NAME.vhd --gen-doc=$NAME.html -i $NAME.cheby
gw/projects/diot_v2/tcl/project_cfg.tcl
View file @ a23c7dbd
......@@ -4,7 +4,6 @@ set project_name "diot_v2"
set entity_top "diot_v2_top"
# Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
set max_threads 8
set project_language "VHDL"
set lib_default xil_defaultlib
# Common IP directory
......@@ -20,6 +19,8 @@ add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
# Vhdl Src
add_vhdl_src ${lib_default} ../src/ps2pl_glue.vhd
add_vhdl_src ${lib_default} ../src/c2c_link_regs.vhd
add_vhdl_src ${lib_default} ../src/c2c_link.vhd
# Add Constraints
add_constraint diot_v2.xdc
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